Power limit of a via

[JFK422]

Hi

So I am designing a PCB and I need to pass about 4.5W through a via. I'm uncertain on how to set the diameter. At the moment I have a inner one (of the hole) of 0.3mm and a outer one of 0.62mm. I've calculated so far, that i need about 0.5mm traces for the ammount of current. (about 1.2A)

Thanks for any help

[T3sl4co1l]

What 4.5W, do you mean thermal conduction?

1.2A is nothing for most any via size.  Assume the via I.D. circumference is lined with 0.5 to 1oz of copper: in other words, the equivalent trace width of the via is about 1.5 times the I.D..

Tim

[KL27x]

^Good to know, on thickness of the plating.

if the id is 1, the circumference is 2 pi R or 1*D*pi. . That's 3.17 x the ID. So why only 1.5X? Is that to leave extra margin because the plating makes the drill hole smaller, or what?

The ratings for current a trace can handle take into account heat dissipation. If the trace is very short and connects to pads (heatsinks) on either end, it is going to handle much more than that without cooking. A via is typically 64 mils long on a standard board. And it has larger pads on either end. So I bet you can go much smaller on vias than w/e Ian's formula says.

I'm not sure of the reasons why, but in some of the datasheets for parts I have used, they recommend multiple small vias in order to increase current capacity, rather than making one huge one. This is how I do it, for no other reason that copypasta one via is easier than changing the size. Maybe it has to do with laminar airflow. I wouldn't expect much air flow through a via. Making the via larger takes away area you could be using for top and bottom pad/plane.

FWIW, I just came across another thread where forum id Rerouter posted this:

Unless your using a special process via plating thickness is generally half your board copper thickness, e.g. a 1 Oz board begins as a 0.5 Oz board, they then put it through some chemical baths so the copper can plate to the via hole walls, then plate the entire thing with another 0.5 Oz of copper, making a 1 Oz board with 0.5 Oz via thickness

[T3sl4co1l]

I'm not sure of the reasons why, but in some of the datasheets for parts I have used, they recommend multiple small vias in order to increase current capacity, rather than making one huge one. This is how I do it, for no other reason that copypasta one via is easier than changing the size.

Solder wicking -- it tends not to flow into small holes ( <= 12 mils, particularly in a lead-free process), and if it does, it doesn't steal much solder from the pad.

This only applies to via-in-pad situations.

Tim

[KL27x]

I suspect it is more than this, though. In addition to the observations I have already posted, when doing multiple redundant vias, you do not have to observe minimum clearance rules of really any kind. You can pack them together. I wonder if there's a mathematically best via size and spacing for getting the most copper into a certain area, keeping thickness of plating the same. I mean, I'm sure there is. In a single giant hole, you could put many smaller vias, right? Say you made a single-file ring of small vias just inside the circumference of one giant hole. If the vias were close enough to almost touch each other, that's already more copper, and you haven't even filed in the rest of that hole. And you got all that much more copper plane/pad for heatsinking, where the single hole has nothing but nothing. Question is, how big can you make a via before you are going backwards?

I'm not sure I have ever even seen a lone, super large via, on any product/pcb, before. I suppose it would look like an unpopulated thru hole, but with soldermask over parts of the pad.

[T3sl4co1l]

Smaller is better, yes.

If the fab limits hole spacing to 10 mils (edge to edge), then density starts going back down for hole sizes on the same order.  It's unlikely you'll have a fab that can do holes smaller than that, anyway, so 12 to 20 mil holes are probably best.

It doesn't take many vias to match the cross section of a trace, so just for routing purposes, this isn't a concern.  It does apply to thermal vias.

Vias can also be filled with solder.  It's desirable to use somewhat larger vias, so the solder wicks effectively.  Solder is much less conductive than copper, but because it's that many times thicker, it increases the conductivity (thermal and electrical) by about 2-3x.  This makes it feasible to dissipate perhaps 10W from a D2PAK, by clamping a heatsink to the back side of the PCB.

Tim

[ocset]

Dave Jones, author of this site , has a great PCB manual which covers such things...i attach it here.

[Neomys Sapiens]

If the trace is very short and connects to pads (heatsinks) on either end, it is going to handle much more than that without cooking.

Maybe that's a bit general, as it only holds true as long as the component(s) sitting on the pads is not contributing more heat than the trace. Which is often the case.

[coppice]

I'm not sure of the reasons why, but in some of the datasheets for parts I have used, they recommend multiple small vias in order to increase current capacity, rather than making one huge one.

Via choice is often as much about controlling inductance as achieving a required resistance. A scattering of small vias does a far better job of bonding the layers together, from an overall transmission point of view.

[T3sl4co1l]

If the trace is very short and connects to pads (heatsinks) on either end, it is going to handle much more than that without cooking.

Maybe that's a bit general, as it only holds true as long as the component(s) sitting on the pads is not contributing more heat than the trace. Which is often the case.

Hmm, depends -- pads themselves are more material, at the very least the pad plus component plating (a thin metal coating on chip resistors, comparable to PCB foil I suppose, and more for leadformed components), plus some solder.  That's more bulk, less resistance.  Plus the pad is often wider than the trace.

On the other hand, the pad is often nonuniform, as the current flows towards a small lead rising off the pad, and that necking causes more current density, which can dissipate more heat despite the greater bulk at the pad.

Fortunately, material thermal conductivity, relative to current density and electrical conductivity, is enough that the temp rise at a given pad is only a few C, even with thermal spokes.  Hardly a concern.

Tim