Power MOSFET as analog switch

[forrestc]

I've been using a relay matrix in an automatic test environment.  Replacing reed relays is getting old, and as a result, I am considering swtiching to a self-built power mosfet array.  I'm trying to determine what unexpected side effects of doing this I'm going to encounter.

The architecture I'm working with is a photodiode output optocoupler driving a back to back pair of n channel mosfets with a suitably low Vgs(th) that the photodiode can turn them on suitably.   As we can take a fair bit of time to do the switching itself I'm not particularly worried about the turnon/turnoff effects related to the gate charge as long as the photodiode optocoupler has enough drive to turn them on in some reasonbly short period of time, and with a strong enough drive so that the mosfet is either fully on, or close to fully on.     Because this is isolated, I don't really have to worry about Vgs(max), since G and S on both mosfets are tied to the same output on the optocoupler.

What I am concerned about is the effects of things like Coss in both on and off states, and other effects.   I'm guessing for the DC signals we're measuring and/or providing (voltages, currents, resistances), this isn't going to be a problem.   What I'm curious about is what happens when you start passing non-DC signals through a mosfet since we do have a couple of switching tests which we like to do at a fairly high frequency.   I'm assuming due to Coss at some point you might find that even an off mosfet is rather transparent to a signal.  (i.e. @100khz and 100pf it might look like only around 16K instead of 'off').   

I'm also working through what this capacitance might look like in a large array.   I.E. 8 colums x 512 rows of switches (yes, around 4K pairs of fets in the array).

I'd appreciate any thoughts and/or hints or general theory I need to watch out for or similar.

[Ian.M]

That's pretty much the topology of an off-the-shelf PhotoMOS isolator or DC rated SSR.  Maybe look at some spec sheets for off-state capacitance and any dV/dt limits to get some idea what you are up against?

[BrianHG]

I don't know how much current or voltage on the switch side you need, but:
for 60v, 500ma use -> TLP222AF
for 40v, 2 amps use -> TLP241A
for 60v 2.5amps use -> TLP3542,  3 amps -> TLP3545
Getting pricey:  Depending on what you are charging, these still may be worth it...
100v 2 amps -> TLP3546
60v 6 amps -> CPC1907B
60v 9 amps -> CPC1709J

[forrestc]

I don't know how much current or voltage on the switch side you need, but:
for 60v, 500ma use -> TLP222AF
for 40v, 2 amps use -> TLP241A
for 60v 2.5amps use -> TLP3542,  3 amps -> TLP3545
Getting pricey:  Depending on what you are charging, these still may be worth it...
100v 2 amps -> TLP3546
60v 6 amps -> CPC1907B
60v 9 amps -> CPC1709J

I need a minimum of 120V (I deal with voltages up to +60V and down to -60V both of which can be attached to the array at the same time), at at least 1A.   But for a bit of headroom, I'm designing for 120V 2A or more.   I'd also like to keep resistance across the switchpoint under 1 ohm, or better.   I could probably live with 2 ohms if I had to.

The current design is actually a TLP3906 driving two FDS86252s.  This is about $1.63 per switch point.    I'm considering right now if the performance of the FDS86252's are overkill and whether I really want/need the lower ohms and whether the capacitance of the FDS8252's is going to be a problem for the tests I'm likely to use this matrix for.

[Cerebus]

Also, consider using 3 switch topology (2 bidirectional switched in series, with center node connected to ground with a third switch). This greatly increases off-state attenuation.

An alternative is to have a T switch, but instead of ground, feed back a buffered version of the single signal that is switched through. In some situations, particularly for AC, this leads to better 'off' isolation than simply trying to short any stray signal to ground. It effectively bootstraps your second series switch, including its capacitance, to an even higher impedance than it already is. Of course this setup is only acceptable if you can tolerate the possible reverse 'feedthrough' to your inputs via the C_ds of the input side switch..

[forrestc]

Also, consider using 3 switch topology (2 bidirectional switched in series, with center node connected to ground with a third switch). This greatly increases off-state attenuation.

An alternative is to have a T switch, but instead of ground, feed back a buffered version of the single signal that is switched through. In some situations, particularly for AC, this leads to better 'off' isolation than simply trying to short any stray signal to ground. It effectively bootstraps your second series switch, including its capacitance, to an even higher impedance than it already is. Of course this setup is only acceptable if you can tolerate the possible reverse 'feedthrough' to your inputs via the C_ds of the input side switch..

The problem is that in my application, there isn't any 'ground' in many of the applications:

An example:  These will be used for wiremapping.   This basically means scanning a ohmmeter across a hundred or so pairs of contacts to verify everything is open/shorted as necessary.   The 'signal' is coming from the ohmmeter and is largely DC (current source).     

The architecture of doing this with a mux is that you have a certain number of 'rows' and 'columns'.  In this case, we're talking about a 450 row x 8 column matrix.    The ohmeter is connected to two of the rows, and also all of the connector pins on the cables to be mapped are connected to additional rows.     You then turn on the fets/relays between each of the two ohmmeter rows and two of the columns.  You then turn on additional fets/relays to connect each connector pin 'rows' as needed to measure the resistance.   In essence when on you're going through a total of 4 fets each way, which is why low Ron is important in this application.

Another example of my concern is that assuming a 100pf output capacitance on the FET, it seems like just between any two columns (when everythng is off), you'd have 25 pf per row of capacitance (4 fets in series) * 450 rows, or 0.01uF across each pair of rows.

I'm also concerned about passing even modestly 'high' frequency through this array, say even 50khz, for testing for proper connection of a signal transformer.   It seems like the capacitance would cause no end of grief.

Oddly, COTS fet matrix products (aka the PXI-2535) seem immune to these effects, so either I'm overthinking this, or I'm not seeing the big picture, or the specs/manuals for the FET matrixes which are available commercially ignore this...   

[jbb]

The architecture of doing this with a mux is that you have a certain number of 'rows' and 'columns'.  In this case, we're talking about a 450 row x 8 column matrix.   

Another example of my concern is that assuming a 100pf output capacitance on the FET, it seems like just between any two columns (when everythng is off), you'd have 25 pf per row of capacitance (4 fets in series) * 450 rows, or 0.01uF across each pair of rows.

I'm also concerned about passing even modestly 'high' frequency through this array, say even 50khz, for testing for proper connection of a signal transformer.   It seems like the capacitance would cause no end of grief.

Oddly, COTS fet matrix products (aka the PXI-2535) seem immune to these effects, so either I'm overthinking this, or I'm not seeing the big picture, or the specs/manuals for the FET matrixes which are available commercially ignore this...   

You might be able to improve this by subdividing the array.  For example, if you make a 50 row * 8 column card, you could then deploy a bank of 9 cards and use a second stage of switches to get select which card(s) you need tied to the main bus.

Some modelling will be required to determine what's appropriate.  There are a lot of options.