Precision Power Supply - Designed and Built by a noob

[Kugelsicher]

Hi all,
I'm designing a precision power supply and would appreciate any feedback. The schematic of the analog section is attached. I'll post anything else that's requested.

The design specs are:
28 V, 2.2 A, constant voltage (with settable current limit), constant current (with settable voltage limit), single range (I'd rather not have to dissipate 60 W at low voltage / high amperage but it's difficult to find a multi-output transformer; also, how the heck do you handle the voltage/current drops caused by range switching), sense terminals, 1 mV and 1 mA setting steps, 1mV and 100uA read back resolution, isolated of course, ground terminal on front along with +V, -V, +S, -S.

It will be digitally controlled and feature a touch-screen (A Nextion screen with a built-in processor to handle all the intensive graphics so that I can control the rest with an AVR, which I have experience with) and a physical number pad (with V, mV, A, mA buttons for easy setting). I think that I can handle the digital design and I can definitely handle the programming but feature suggestions are welcome.

What I do need help with is the analog design. Specifically: Is the design overly complicated? Is this how it's done? Also, I'm having stability issues; are my LTSpice stability models correct?
I'm using the Art of Electronics as a guide where I can: the current balance circuit on the paralleled power transistors; the AC to DC supply; the transformer selection (which is toroidal, whoo); etc.

Alrighty, thanks if you've gotten this far. I'm going to go over what's happening in the attached schematic. This is gonna be long winded but I'd rather avoid confusion.
First, all of the op amps are driven by a separate supply that provides +8V and -8V relative to the ground on the schematic.
Starting at the top left, the sense terminals and main input terminals go to differential amps that divide by 12, to get the full scale reading in range of the ADC and DAC.
The output of these two op amps go to an analog switch (DG419) which selects an input. The rest of the circuitry on the top half of the schematic is just for deciding which input is selected (main or sense). This is controlled by the CRL input on the DG419, High on CRL selects the main terminals, Low on CRL selects the sense terminals. On the top, far right is a FET whose gate is connected to the microcontroller (uC); when the gate is high, that FET turns off the FET that it's connected to, which prevents the sense terminals from being selected. If the gate is low, there are two further requirements for the sense terminals to be selected. First, the op amp to the right of the sense-input-divide-by-12 op amp compares the main and sense voltages (both divided by 12); selection of the sense input is blocked if the sense voltage is higher than the main input terminal voltage (prevents funny business, there should be voltage drop). Second, the amount of voltage drop between the main terminals and the sense terminals is compared to a value that is set by the 8-bit DAC that is below the divide-by-12 op amps. If the amount of voltage drop exceeds the set threshold, then selection of the sense terminals is blocked (this prevents more funny business. for instance, if 4-wire mode is selected but the sense terminals aren't connected yet).

The description is unfinished and I haven't posted the LTSpice data yet; but happily, I've already gotten a couple of replys with lists of problems. So, I'm going to address those first and then update everything with the up-to-date information. Feel free to keep adding suggestions.

Thank you for any suggestions, corrections or guidance,
Matthew

[Kleinstein]

The circuit looks overly complicated in some areas, but it still misses frequency compensation. So chances are it will oscillate, at least with a capacitive load. The chosen type of regulation, with the load on the drain side, usually needs an well chosen capacitor at the output too make it stable at all. Combining the CC and CV control part needs at least one diode - just directly adding the signals does not work well. Also the OPs won't like the the 10 nF caps at the OPs output. That is too much capacitive load.

Having two MOSFETs in parallel is not working reliable with such small source resistors. Current sharing is rather difficult with MOSFETs. The chosen MOSFET type (IRFP7537) is not at all suitable: it a dedicated switching type. The only good thing about it is, that the FBSOA directly shows that it is not suitable for linear operation at more than about 5 V. A more suitable type would be something like IRFP250, or switch to BJTs like 2N3055 / TIP35 which are easier to parallel. With just 60 W worst case dissipation one might get away with a single large FET / BJT.


The chosen OPs (mainly TL08x) are also not really precision types (but this a the least problem).

[Kugelsicher]

Hi blueskull,
Thank you for the help. I've pondered each of your suggestions. For clarity, I'll reply to them in the same order.

1. Yup, that's an excellent idea. I had heard/read that somewhere; but I dismissed it as a short cut used on cheap power supplies. I thought this because of the problems that could be created by a simple implementation (which is the only kind I considered at the time). Specifically, if the resistor values are large, there would be a change in op amp gain when not using the sense terminals; and, if low value resistors are used, the sense lines could have significant current through them (causing a loss of precision) and the resistors could see large power dissipation. Your suggestion made me think a bit harder about how to implement it. I think I've found something that avoids the mentioned problems. The changes will be on the updated schematic. Thanks again!

2. I'm not sure about this one. Kleinstein said the same thing; so I've got to be missing something. My understanding is that under normal operation, one feedback loop will be in control and the other comparator op amp will be saturated with a high output. That shouldn't effect the other comparator op amp's ability to control the loop though because it can still swing to a negative voltage that is equal in magnitude to the other op amp's positive voltage, resulting in zero volts at the output which would fully turn off those N-Chan FETs. Also, these are single supply op amps that can get closer to the neg rail than the positive and there's a constant current sink (part of the paralleled FETs' current balance circuitry), both will pull the output below ground.

3. I do want the supply to go down to 0 V; but, I think the supply will already do that. I did fail to mention that the op amps are driven by a separate supply that provides +8V and -8V relative to the ground on the schematic. Otherwise, perhaps FETs have trouble with high impedance at very low current?

If I've misunderstood something please let me know.

[Kugelsicher]

Hello Kleinstein,
Thank you for taking the time to go over so much.
I'm aware of the lack of frequency compensation. I just don't understand it enough to do it properly yet. I'm figuring out LTSpice and re-familiarizing myself with complex analysis. Also, I've prototyped it and oh buddy does it oscillate. It's basically an oscillator with a very stable DC offset.

Like I said to blueskull, who brought up the same issue, I don't understand the purpose of a diode on output of one of the comparator op amps; if that's even the location that you're suggesting. Please tell me what I'm missing. My understanding is that under normal operation, one feedback loop will be in control and the other comparator op amp will be saturated with a high output. That shouldn't effect the other comparator op amp's ability to control the loop though because it can still swing to a negative voltage that is equal in magnitude to the other op amp's positive voltage, resulting in zero volts at the output which would fully turn off those N-Chan FETs. Also, these are single supply op amps that can get closer to the neg rail than the positive and there's a constant current sink (part of the paralleled FETs' current balance circuitry), both will pull the output below ground.

I've removed the 10 nF caps from the OPs on the revised schematic.

The Art of Electronics cued me in on the pitfalls of paralleling power MOSFETs. There is some current balancing circuitry already in the design. Did you just miss it or is there something wrong with it?

I'm sure you're right about me choosing the wrong MOSFETs. I'm going to research that and find suitable replacements.

Lastly, the OPs are TLC08x, which are significantly different to TL08x; although, that may have just been a typo. What are the critical specs for this application? I suspect voltage/current noise, temperature stability but I think the TLC08x is pretty good in those categories. I picked it as a general OP to buy 20 of a while ago (when I knew even less) for its reasonable offset voltage (390uV typ. 2mV max), excellent I-bias (1.5pA typ, 100pA max), single supply capability, and cheapness.

[Kleinstein]

Sorry one the OPs: the TLC08x look much better than TL08x, however there higher speed can also cause some problems in some places. But the choice of OPs is usually one of the last points to look at in a power supply design.

The current sharing part might actually work - I ignored it in my first analysis as an additional fast over-current limit. This might be needed in such a circuit, as the normal CC loop might be rather slow to react.

The switchover between the CC and CV mode can work with just the two resistors. However using just to resistors is unusual. One disadvantage is that the OP in saturation will couple supply ripple to the output. With well regulated and suitable limited supply the two resistor solution also has some good points to it. The more normal way is to replace at least one of the resistors (usually the one for the CC mode) with a diode. This makes the cross over region smaller. The version with two diode and a current source to provide some positive current to work against also allows for extra independent limiting of the OPs swing to improve the CC-CV cross over.

Anyway a 10 K series resistor might be a little high to drive 2 powerful MOSFETs.

The link to the LT magazin does not really help with this supply. Its about a different concept for a supply aimed at low heat loss but also low precision. Still some Application notes and similar infos from LT and Ti / National Semi are a good source of information.

While transformers with multiple taps are difficult to find, one can often find some with at least a split winding. Especially for the low planed voltage, there is a relatively simple way of using 2 voltages and this way reducing the worst case power loss to a little more than about half. The idea is similar to a class G audio amplifier. However it can be added later. With a reduced loss, one might not need 2 parallel MOSFETs any more - so it might even simplify the circuit.

[bg9gas]

You can try using tda7293 as the final stage current amplifier