hysteresis plays no useful purpose here because even if the comparator would "misfire" at 50 Hz (i.e. every other cycle) the capacitor voltage would be higher than the center tap voltage and that alone would prevent the center tap mosfet conduction.
I'll try to show that tomorrow...
i'll look forward to it.
sorry... I've been too busy yesterday... anyway here it is
The circuit uses a couple of BJTs to detect when the 100Hz (or 120Hz) rectified AC gets to 0V. Then on the collector of Q6 you get a short (compared to the AC line period) positive pulse.
Each positive pulse then gets to one input of the two NAND gates U5 and U6.
Depending on the status of the voltage comparator U2 output (and inverted U1 one) the positive pulse becomes a negative one at the output of either U5 or U6.
If the flip-flop is not yet in the required status, the pulse changes that, switching off one of the mosfets and leaving the other get to the on state.
The circuit has been simulated with LT1013, LM358, LM393 (with pull-up resistors on the output) but should work with any rail-to-rail I/O opamp and probably with most single supply one. I also added some hysteresis as suggested by Kleinstein to reduce unneeded tap switching.
It looks like the peak current on switching from the low tap to the high one gets at once about 4 times higher than the full load peaks and then gets back to normal in 3-4 cycles. The output voltage ramps up at a speed of few milliVolts per µs so shouldn't cause too much trouble for the voltage regulator stage.
Possible improvements might include usage of N-MOSFET (greater choice, low cost and low Rds-on) and switching them off via an optocoupler.
With few modifications, including back-to-back MOSFETs switches and a bit more complex logic, two transformers and bridges (or a single one with dual split winding secondaries) might be stacked in series to get 4 voltage levels.
I'm also attaching the .asc file (see below). Apart from
CD4000_v.lib and
logic gates symbols it uses just LTspice stock components.
The following screenshots show the logic signals:
These show the MOSFETs current and source-gate voltage:
These last two screenshots show the peak current and voltage spike when switching from low to high voltage.
The simulation has been run with a huge 47.000µF capacitor and a load of 10Amps.