Preventing current shunt amp saturation, ideas?

[Siwastaja]

Hi,

I'm using an unidirectional current sense amp (CS30BL) to sense a mostly unidirectional current in a synchronous buck. It's never driven near zero current in normal operation, so the current is always normally positive, in CCM.

In startup due to gate driver bootstrap charging off-time pulse, and possibly in other corner cases as well, the current might get a bit negative for a short period of time (a few microseconds).

The amp saturates at 0V, but it takes much longer - around 20 us of fairly high positive current! - to recover from this state, than you'd expect based on the normal bandwidth figure.

Any ideas how to prevent or minimize the internal windup? It's just a few tens of millivolts negative differential input that saturates it "more badly" than zero differential voltage on the input. Input common mode is around 16V, Vcc=5V.

I have software kludges in place, but if I could avoid this without complicating the BOM too much...

(Bidirectional amps with sufficient BW seem to be a bit too expensive. I would really need close to 1MHz, <$0.50 @ 10000pcs.)

Any ideas?

[duak]

Can you bias the opamp input slightly positive with a known offset?  If it's just a few millivolts it shouldn't affect the range much.

Cheers,

[T3sl4co1l]

Put a little voltage divider on one side?  Worsens CMRR by the same amount, of course.

Or a reference and divider, so it's independent of CM. 

Tim

[Siwastaja]

Forgot to mention that CMRR kinda matters, because the buck output (the CM) varies between 16 to 25V, and I do want to regulate current.

Reference and divider... (Grunting sounds.) Maybe a bidirectional amp to begin with would have been the right thing to do. I guess there is no easy, simple way out and I'm stubborn enough to really want to keep the cheap&simple BOM...

The software kludge is doing fine, it's just a bit... scary? To run the DC/DC without any current feedback for the first 15-20us, which basically equals the time from zero current to inductor saturation current in the worst case, although if it really was rising that fast, I guess the amp would come out of the saturation much faster in this case! So the harder I push it, the quicker I am in control, and I have hard time deciding how carefully I should do this.

I do have input and output voltage measurements, which I use to calculate the "theoretical" Vout/Vin duty cycle to PWM it with, adding some offset towards bigger on-time to make sure current's going in the right direction. And then I have a counter to give up if the ADC's showing near-zero current for too long. It's close enough so that the current doesn't get huge during this 20us, and no blown FETs so far with this scheme, but I don't like the software complexity and I'm already wasting 30% of the CPU time in two 330kHz interrupts calculating and limit checking things...

But thanks, I'll come up with something.

[Hydron]

Could you put a low-value resistor between the normally-more-negative leg of the shunt resistor and the Vm input of the CS03? That would allow you to connect a higher-value resistor and MOSFET (e.g. BSS138) to ground from the Vm pin so you can pull the pin a little negative under software control during startup to always bias the CS03 correctly.

[Siwastaja]

Could you put a low-value resistor between the normally-more-negative leg of the shunt resistor and the Vm input of the CS03? That would allow you to connect a higher-value resistor and MOSFET (e.g. BSS138) to ground from the Vm pin so you can pull the pin a little negative under software control during startup to always bias the CS03 correctly.

This isn't actually too bad since I have jellybean discrete MOSFETs in the BOM already. I had something similar pop into my mind but you swapped it around to the negative input and GND side, making it simpler... (For good CMRR, I'd put low-value resistors on both + and - input legs, and use as small value as possible, like 22R).

I was missing the obvious, and recalculated the bootstrap capacitor with less extra margin, dropped it from 220n to 100n which is a tight but decent fit with proper (but not excess) margin, to make it charge in 1us, which would basically solve the issue by limiting the initial negative current to half of what it is now. It turned out, the bootstrap cap not charging enough wasn't the only limiting factor - the gate driver IC requires an (unspecified) long-enough low pulse after the enable has gone up, if it's below about 1.5us, it will completely ignore the first high pulse!! (A non-documented feature.)

[David Hess]

It is too bad they do not provide more internal details.  The output of the error amplifier operates close to ground at low output voltages so windup is limited to about 0.6 volts which is insignificant.  There must be an internal node which recovers from saturation slowly.

My first choice would be to implement the same design with a discrete operational amplifier which does not suffer from the overload recovery problem.

But if I had to keep this part, I would try adding a resistor in series with pin 4 and a constant current sink from pin 4 to ground to create a deliberate fixed offset.  Now the output will have a positive offset from ground when zero current is being drawn so the part can indicate negative currents without saturating.  With some care, this will preserve the original common mode rejection.  This is essentially Hydron's suggestion but the output becomes continuous and no intervention is required.

[Hydron]

This isn't actually too bad since I have jellybean discrete MOSFETs in the BOM already. I had something similar pop into my mind but you swapped it around to the negative input and GND side, making it simpler... (For good CMRR, I'd put low-value resistors on both + and - input legs, and use as small value as possible, like 22R).

I also initially thought to match the resistors in both + and - inputs, but from looking at the internal arrangement in section 5 of the datasheet, it appears that the gain is dependant on the impedance between the sense resistor and the Vp pin (but not the Vm), so best just to add one to the negative input. If you only need a small offset then you can use a fairly low value resistor for Vm anyway.