Your missing parameter is parasitic inductance, and since it comes from your PCB layout, it cannot be in the datasheet.
My suggestion is to try your best in minimizing the loop area, and use proper low-ESL (small ceramic) DC link capacitors very close. You need to think about this loop: input capacitor + -> high side switch -> low side switch -> input capacitor -, and mininize that loop.
Modern SMD parts have made this much easier.
Now, you can add footprints for an RC snubber across both FETs for prototyping, but chances are you won't need them.
Run first at lower voltage and look at the scope trace. If your layout sucks, you may easily have 2x overshoot and ringing in the switch node voltage - this is why you run at lower voltage first so that you won't blow the FETs on excess Vds. OTOH, if the overshoot is below about 1.5x the DC link voltage, your FETs Vds rating is fine with it, and there is no requirement for EMC, then snubbers would only waste some energy.
In modern motor controllers or switch mode designs, most of the time there are no snubbers. Do the layout right.