Revolutionary new memory cell - is this true and usable?

[matseng]

I stumbled onto a video



 about some new "revolutionary" type of memory cell invented by a kid, he claimed that it was patent pending so I searched for the patent and found it. Two transistor ternary random access memory (TTTRAM) - http://www.freepatentsonline.com/20150092485.pdf

The memory cell shown in the patent looks like this:

It looks a lot like a thyristor made out of transistors but with the PNP flipped around.

I'm not particularly good at reading patent claims, so could someone better suited than me have a peek at it and see if it's really something that could work and is revolutionary in terms of speed and energy consumption as he says.  And also describe *how* it works?

[PA0PBZ]

Here is a little bit more info:

https://apps2.societyforscience.org/intelisef2014/project.cfm?PID=EE002

[SeanB]

Using reverse beta will work, but the resistors will be hard to make small on a wafer, unless you use some pinched off FET transistors, which then make it a 4 transistor cell. You will still need a extra FET per cell to either read or write it, and probably 2 in series to get a multiplexed address scheme. DRAM with a single transistor looks good, and SRAM with the main advantage of only needing to make a single MOSFET style, no extra diffusions to make a lateral PNP or a buried well to isolate it either.

[Kleinstein]

Alone the current needed to hold it's state makes this a no go for high density.  Even only 1 nA per bit set in a GBit Ram chip is way to much.

At low density the CMOS SRAM is good enough.

[wraper]

This revolutionary memory cell is 50 years too late.

[Fungus]

Alone the current needed to hold it's state makes this a no go for high density.  Even only 1 nA per bit set in a GBit Ram chip is way to much.

From: https://apps2.societyforscience.org/intelisef2014/project.cfm?PID=EE002

"Modeling showed TTTRAM power consumption in femtoampere range, DRAM in picoampere range while SRAM on average operates in nanoampere range. TTTRAM uses considerably less current than competing technologies."

[jwm_]

Looks somewhat similar to the register configuration of the 8085, two inverters in a cycle, to change the value you fed in a stronger signal. Basically a "bus hold" circuit.

[SeanB]

Alone the current needed to hold it's state makes this a no go for high density.  Even only 1 nA per bit set in a GBit Ram chip is way to much.

From: https://apps2.societyforscience.org/intelisef2014/project.cfm?PID=EE002

"Modeling showed TTTRAM power consumption in femtoampere range, DRAM in picoampere range while SRAM on average operates in nanoampere range. TTTRAM uses considerably less current than competing technologies."

so just how much capacitance is modelled there, if you are in the gigohm range for the resistors then you need both a really low leakage bipolar process ( so something exotic grown on a sapphire base with the great yield of that process) and something that can also have that value resistor as a part. Yes you can have the low current, but the speed will be best described as glacial, and very susceptible to both radiation flipping and thermal flipping of bits, and might even not be readable as the turn on charge of the switch might flip the state. Good thing though is a block erase can be done with a single LED above the array.

[matseng]

...so just how much capacitance is modelled there, if you are in the gigohm range for the resistors then you need both a really low leakage bipolar process ( so something exotic grown on a sapphire base with the great yield of that process) and something that can also have that value resistor as a part.

He mentions using "pseudomorphic heterojunction bipolar transistors" - never heard about it so I had to look it up on wikipedia. It sounds quite exotic and not at all your run-of-the-mill transistors....

"A pseudomorphic heterojunction bipolar transistor developed at the University of Illinois at Urbana-Champaign, built from indium phosphide and indium gallium arsenide and designed with compositionally graded collector, base and emitter, was demonstrated to cut off at a speed of 710 GHz"

[SeanB]

So, just how many dollars per bit then............

[T3sl4co1l]

PHEMTs are standard fare in RF (wireless/microwave+) hardware, so it wouldn't be exceptionally hard to make.  Not sure offhand if they've been used in a monolithic process, possibly along with other devices.  I know I've seen SiGe:C (which is a strained process, not sure if it counts as PHEMTs) op-amps of various spec, from surprisingly general-purpose but very low power for the speed, up to GHz screamers.

Tim

[Marco]

Does anyone even use BJTs in the 10nm range?

[T3sl4co1l]

That's probably the other part, VLSI has been MOS for generations, and isn't showing any signs of quitting.

And as mentioned, sure maybe you could marry it to such a process, but you're likely adding a lot of steps, and that kills yield, and cost even faster.

Tim

[LaserSteve]

I'm pretty sure I've seen that topology before in very old books on semiconductor circuit collections..

Steve   

[0xdeadbeef]

Isn't this a more or less typical latch circuit? I guess if there's something ingenious there (which has to be proven), it's the transistors and not the circuit.

[SeanB]

Probably, using reverse beta does work on a lot of older designs with low breakdown voltages, though long term it does degrade the device in some cases. Was common on making bipolar devices act as an analogue switch. Crappy switch, horrid performance but was the only solid state relay before CMOS analogue switches were available and if you could not use a Jfet.

As for being unique, it is basically a variant on a old design, the SCR. That is long out of patent though, seeing as it was about the third type of transistor developed, and was ther first one to have really high power capability. Must be at least 100 separate dies made per person in the lifetime,

[rfeecs]

HBTs are routinely used in microwave MMICs.  Geometries are in the 1um area.  PNP is virtually never used.
The figure in the patent looks absolutely nuts:

[SeanB]

Good luck making that in bulk with any reasonable yield. you probably will have to make them with a look up table to get the bad blocks out and to make them appear good, at least at manufacture.  1G device with a 256M bad block table......

[Kalvin]

https://upload.wikimedia.org/wikipedia/commons/thumb/2/26/1st-Transistor.jpg/800px-1st-Transistor.jpg

Too big, very unreliable, lousy yield, unpredictable performance, too sensitive to temperature, so no use to develop it any further.

[SeanB]

https://upload.wikimedia.org/wikipedia/commons/thumb/2/26/1st-Transistor.jpg/800px-1st-Transistor.jpg

Too big, very unreliable, lousy yield, unpredictable performance, too sensitive to temperature, so no use to develop it any further.

Yes, but we did learn that some things are very hard, till you learn how to work with material. Now we know how to move atoms around to make a structure, and still this new method will be very expensive to get into mass production.

[matseng]

Isn't this a more or less typical latch circuit? I guess if there's something ingenious there (which has to be proven), it's the transistors and not the circuit.

Maybe, but at 1:05 in the video he mentions that his design can also be done in both CMOS(?) or BiCMOS as well.   I probably heard wrong at the CMOS part, because that would mean that that the circuit would work with mosfets as well - or can you put bjt's on a cmos die?

[T3sl4co1l]

BiCMOS has been around since the 80s. (Or in common use anyway, I don't know when it was introduced.)

That structure doesn't make sense; there's an IO line in the middle of a crystal.  Unless the stuff on top of it is intended to be poly or amorphous, or it's expected to obtain a crystal orientation (perhaps after annealing) from the base material around the IO line.  In any case, it sounds manifestly impossible: if the IO line is copper, it must be surrounded with barrier first (copper diffusing into silicon makes undesirable mid-band doping that increases leakage without providing P or N effect); if aluminum, it will diffuse and make everything nearby P+, ruining the structure anyway.  And if it's all amorphous, does that even work?  I don't know. Not well I'm guessing.  (Well enough for, say, TFTs, at least in MOS format -- but I don't know if BJTs were ever tried.)

Tim