Routing Questions - I thought I knew

[envisionelec]

I started working for a fairly large international company (you would recognize their products) and had a design review recently where I was called out for routing a trace under an 0805 pull-up resistor (circuit voltage 3.3V). Two engineers called it out and one said it was obviously bad design practice. I was pretty shocked considering it didn't violate DRC. They also complained that there were "acute angles" that cause acid traps. Now, I had heard of this one, but thought it was a non-issue these days. It's pretty hard to route a tight layout without incurring an acute angle, but I typically put in teardrops to eliminate this issue.

Some of the arguments included tin whiskers, dendrite growth and just looking bad. Now, correct me if I'm wrong, but wouldn't fine pitch devices also have these problems if those things were true?

Is this really a concern? How can I go about convincing them it isn't a problem?

[Zucca]

It all depends, what are the EMI/working frequency, thermal situation of that board? Project specifications? Pictures?
There are no general rules to be applied with closed eyes and turned off brain IMO.
There is the good and holy theory which has to be implemented in every single situation/board.

The more you know, the more experience you had/have, the more you will be create good/design board.

PS: Never lose, either teach/win or learn 

[tomato]

I started working for a fairly large international company ... How can I go about convincing them it isn't a problem?

You just started working for a large, well-established company and you want to tell them they are doing things wrong?  Good luck with that.

[DaJMasta]

I'd assume that their engineers know the manufacturing process they've used before and should be deferred to, I'd also assume they're being especially scrutinous of your work because you're new.  Tin whiskers are more metallurgy territory, but they could be basically advising best-practice to minimize inevitable failures in production due to changes that can't be made (like getting different lead pitch on certain parts), again they've probably seen issues in products before and want to be careful to not have to spend the big bucks on recalls and replacements.



So some of it is probably being careful  to minimize risk of problems at stages they're hard to correct at, some of it is based on past experience with the process and designs, and some of it is being cautious of the new guy's work.

[james_s]

My advice would be put your pride aside and try to incorporate any suggestions they have, regardless of what you think of them. Go ahead and offer your opinion but don't keep pushing if they push back, and be open to ideas from the more established engineers. Eventually after you've been there a while you'll earn respect and have more leeway to do things your way.

[rx8pilot]

This is why I won't work for a large company.
Many engineers MUST be right all the time - including the ones that are your boss.
Many engineers worry about non-existent problems because they don't truly understand the manufacturing process or how things have changed since 1985
Many engineers actually do know about finicky details that have burned them in the past and do not want to repeat it.

Nearly zero engineers are willing to get a lesson from a new PCB designer - they are responsible for the sign off in the end.
After some period of success and doing it their way - you can judge who is willing to have a conversation and who is not.

[JS]

  0805 is a pretty small package to put a trace between pads, you can fit it within standard DRCs but depends on the 0805 footprint as well, then consider the solder mask retraction, and you are not with a lot of space for insulation, you apply solder to it, there's no space underneath, little insulation, you might see a problem or two while producing hundred of thousands of those and it can be avoided reasonable easily unless you are in a single sided PCB and you shouldn't be using jumpers, so I see no problem with that restriction.

  Acute angles have always been called problems, many reasons why, for HF are really a problem, for LF the problem could be in the process, not so much for the signal, DIY, hobbyists, self etchers learn all this stuff in the hard way early on, when you start with manufactured PCBs you don't realize how or why the process constrains are there. Even if the process for self etch and big manufactures is quite different it shares many of the constrains in different scales. At home 8 mil rules are the limit, when I started I wouldn't be confortable under 16 or 20 mils your manufacturer might be 4 mils, but the process is pretty much the same, some resist material and etching, they have better tooling than I do.

JS

[james_s]

This is why I won't work for a large company.
Many engineers MUST be right all the time - including the ones that are your boss.
Many engineers worry about non-existent problems because they don't truly understand the manufacturing process or how things have changed since 1985
Many engineers actually do know about finicky details that have burned them in the past and do not want to repeat it.

Nearly zero engineers are willing to get a lesson from a new PCB designer - they are responsible for the sign off in the end.
After some period of success and doing it their way - you can judge who is willing to have a conversation and who is not.

There are a lot of large companies out there and not all of them are like that. If one is new there though it's not unreasonable to have to gradually earn the respect of more experienced people. It's not all that unusual for some new guy to march in and think they know everything.

[KL27x]

  0805 is a pretty small package to put a trace between pads, you can fit it within standard DRCs but depends on the 0805 footprint as well, then consider the solder mask retraction, and you are not with a lot of space for insulation

I don't see why that applies specifically to a trace that runs between the pads. If you run the trace between 2 separate 0805's in such a way the spacing is the same, you could claim all the same issues, right? And you would change your DRC settings?

I suppose flux residue stuck under the resistor or heat/thermal issue from the resistor can open up other cans of worms?

[RoGeorge]

How can I go about convincing them it isn't a problem?

That is absolutely what you should not do. The reviewers are not attacking you, they are just guiding your work.

Since there were 2 persons, and they also explained the concerns (whiskers and acid traps), you need to correct the design, and also keep in mind these best practices for the next PCBs.

[ludzinc]

This is why I won't work for a large company.
Many engineers MUST be right all the time - including the ones that are your boss.
Many engineers worry about non-existent problems because they don't truly understand the manufacturing process or how things have changed since 1985
Many engineers actually do know about finicky details that have burned them in the past and do not want to repeat it.

Nearly zero engineers are willing to get a lesson from a new PCB designer - they are responsible for the sign off in the end.
After some period of success and doing it their way - you can judge who is willing to have a conversation and who is not.

Many engineers have lost $10,000's that they were responsible for and have learnt that lesson all too well.

As me about an un-tented via underneath a transistor that saw me replace over 200 units in the field.....

[Mr. Scram]

You don't stand to gain anything from fighting this battle. If you get it your way you only risk being held responsible for any issues down the line that may or may not be caused by your design choices. Just accept this is their version of doing it right and do it how they want it. The only exception would be something where there's actually an issue with how they do it.

Pick your battles.

[krish2487]

Disregarding almost everything what the existing engineers said about acid traps and EMI and anything else.


Is it really so hard to redo the board just to avoid conflicts and make your life easier??


You said it yourself, it should not be a problem. If you can make them happy, you are making your life easier.


Just my 2 cents..

[max_torque]

If there is no (zero cost) way of avoiding the track going under the component, then you need to assess the relative risk that this track creates.

If you can simply move the track out from under the resistor (by using another layer, or re-routing the track, or moving the component) then that's what i would do.

There's no point adding risk for little gain imo, even if that risk is low in absolute!

[exmadscientist]

For what it's worth: my assessment of whether these practices are OK would depend mostly on the intended application, summarized in the IPC Performance Class. For Class 2 stuff (standard reliability), I don't see anything wrong with routing traces under components. I'd even consider vias under components to be fine in Class 2; things like putting vias under caps to create low ESL connections can be very useful. But if this is a Class 3 (high reliability) design, or higher, then the negatives outweigh the positives. The requirements for Class 3 are a lot more strict, and the process much more expensive, because the end application justifies it.

And for Class 1 (low cost), it's fine if it waits until after it leaves the factory before catching on fire 

Acute angle routing traces, on the other hand, are not something I like to see ever. While modern processes have improved to the point where acid traps and tin whiskers are rarely problems now, acute angles are usually just a sign of routing sloppiness and can be trivially fixed. Usually when I find one, I don't worry so much about the angle itself as how much attention the rest of the nearby routing got... and I usually find something else I don't like nearby.

[james_s]

I try to only use 45 degree bends whenever possible, weird angles just looks sloppy and whenever I see a board router that way I immediately think it was done by an amateur. It's the same feeling as looking in an electrical box and seeing that the outer sheath has not been stripped off the NM cable all the way back to near where it enters the box, it still works but it just says sloppy and inattention to details.

[aandrew]

As me about an un-tented via underneath a transistor that saw me replace over 200 units in the field.....

Ok, I'll ask. What's the story of the untented via under a transistor that saw you replace over 200 units in the field? 

[KL27x]

^Bridges? I'm curious, too.

I have done this on accident on a production board, but I noticed it, immediately. I spent several miserable hours with kapton tape and an exacto knife. 

But if this is a Class 3 (high reliability) design, or higher, then the negatives outweigh the positives.

I am curious if the minimum DRC rules change enough to make this (trace under a resistor) impossible, or is it specifically prohibited in Class 3. And what is the failure mode? Also, is it equally prohibited to run a trace under an IC? Where's the cutoff? Surely it is ok under a DIP? An SOIC? A narrow SSOP? SOT-23? 

Obviously OP should say "thank you" to his senior for correcting his mistake. But I don't expect he will ever get a rationale explanation. Just the same smart-sounding non-answers that people post here.

I checked a production board I have, and maybe I made my own footprint/library part. I can't remember. But there's soldermask between the pads. Maybe it's not supposed to be there?

I've never needed to do this on a production board but I have several working boards I use daily for nearly a decade with traces between 0805 sized resistor pads... and no soldermask. The actual component on there is in some cases smaller, even, than 0805; though in this case it is hand soldered with a deliberate air gap.

I was also under the impression that one of the reasons 0R resistors exist is to jump traces. 

[exmadscientist]

^Bridges? I'm curious, too.

I have done this on accident on a production board, but I noticed it, immediately. I spent several miserable hours with kapton tape and an exacto knife. 

But if this is a Class 3 (high reliability) design, or higher, then the negatives outweigh the positives.

I am curious if the minimum DRC rules change enough to make this (trace under a resistor) impossible, or is it specifically prohibited in Class 3. And what is the failure mode? Also, is it equally prohibited to run a trace under an IC? Where's the cutoff? Surely it is ok under a DIP? An SOIC? A narrow SSOP? SOT-23? 

Obviously OP should say "thank you" to his senior for correcting his mistake. But I don't expect he will ever get a rationale explanation. Just the same smart-sounding non-answers that people post here.

I checked a production board I have, and maybe I made my own footprint/library part. I can't remember. But there's soldermask between the pads. Maybe it's not supposed to be there?

I've never needed to do this on a production board but I have several working boards I use daily for nearly a decade with traces between 0805 sized resistor pads... and no soldermask. The actual component on there is in some cases smaller, even, than 0805; though in this case it is hand soldered with a deliberate air gap.

I was also under the impression that one of the reasons 0R resistors exist is to jump traces. 

IPC standards (which define the Performance Classes) don't cover DRC or fab rules; those things are agreed on between designer and fabricator. The standards are more interested in things like defining defects and allowable defect densities, so saying "Class 3" in this context is more shorthand than anything else. Usually Class 3 acceptance rules are specified when a failure would put someone's life at risk (e.g., automotive, aerospace, defense, medical life support, etc) or when truly giant piles of money are involved (e.g., space). Quite obviously that kind of work demands a higher level of performance, hence the very strict acceptance criteria for this class.

As you point out, for normal use there's no reason not to run traces under components. (Though I personally don't do it without solder mask.) My guess is that the failure modes are along the lines of debris getting trapped at the edges of components combining with solder mask degradation to provide a potential shorting path. Solder mask is vulnerable to abrasion, so it's not hard to imagine chip components or low-clearance parts causing mask damage given some thermal cycling. But don't take my word for it, I don't think I've ever done a class 3 design!

[KL27x]

^Well, if you have never done a class 3 board, and class 3 has nothing to do with DRC or fab rules, I'm curious why you suggest running a trace between 0805 pads is not kosher in a class 3 pcb? Is this a rule of some sort? If it is just your opinion, I wonder why you stated it so strongly, as if you agree with the OP's senior colleague. Telling someone this is "obviously bad engineering practice" is so devoid of useful information, it's mindboggling. At least you included some interesting/useful information, albeit, it appears to me to be completely tangential to the original point, lol.

BTW, the OP stated the resistor is a pullup resistor to 3.3V. For say 10K pullup, that is 1.1mW. If anything, the presence of the resistor will protect the soldermask from damage.

I can imagine OP running a trace under an SO-4 IC in the future. Is he going to get beat with a stick for not having learnt what is "obviously bad engineering practice?" What about a 2412 resistor? Does it matter if it were a size D tantalum cap? I mean, it's pretty much open to interpretation what the heck that means. A quick "why" would clarify a lot. Maybe an anecdote of that personal disaster of 1984...

[Rerouter]

I went digging without much success, as high reliability layout is something I try and keep up with.

As Class 3 is "If Things fail, people can die" level of requirements, I take it as removing every possible risk,

So my take would me the additional height of the solder mask over the copper trace would cause a bending force in the SMD component, which especially for ceramic capacitors can reduce reliability, by reducing the flex margin (how much the board can flex before cracks form)

In the same case, it can reduce the margin of your paste re flow, if 1 pad melted first, the part would be see-saw'd away from the other pad, so if you had an untented via that sucked up most of the solder on that pad, it could leave it very marginal.

I have to constantly keep it in mind for QFN packages, if you run traces under one, its better to fill Idle space with a supply rail pour so with solder mask the entire underside area is the same height than to have just the few squiggles causing pivot points. And ironically that solder mask thickness rise of the board can increase reliability as thicker solder fillets can better handle flexing.

Acid Traps are something I rarely worry about these days, less that its still a problem, more so that rounded-rectangle pads, teardrops on Via's and trace neck down removes all but the weirdest issues. and unless your layout package allows spline like traces, 45 degree traces is a good compromise to give you more space efficiency than 90 degrees when you go High density.

[T3sl4co1l]

Funny, I've inherited a design from a Large Company You'd Recognize, and it's full of odd design decisions and ugly routing.  (It's from a much smaller department, however, which is probably part of the reason why we've been called in to help.)

FWIW, I avoid acute angles where possible, not because of acid traps but just because it looks ugly. Take pride in your work, create a masterpiece.  Don't settle for "found art".

Tim

[Mr. Scram]

Funny, I've inherited a design from a Large Company You'd Recognize, and it's full of odd design decisions and ugly routing.  (It's from a much smaller department, however, which is probably part of the reason why we've been called in to help.)

FWIW, I avoid acute angles where possible, not because of acid traps but just because it looks ugly. Take pride in your work, create a masterpiece.  Don't settle for "found art".

Tim

If it saves space functional "ugly" angles take preference over pretty but more space consuming angles. Take pride in coming up with the best solution within your constraints. If it doesn't make a functional difference then sure, go wild and shine things up.

[james_s]

There are certainly exceptions, but in many cases the same rule of thumb that applies to airplanes tends to work pretty well with PCB layouts. If it looks beautiful, it will often work well.

[KL27x]

The other thing with inheriting a design is maybe it wasnt finished? Altium is super snazzy and easy to reroute like an afterthought. In Eagle you are wasting your time about "pretty" until you are sure the components are in the most efficient positioning and exact locations, and the thing works.

... and once it works, there is a saying. If it ain't broke...

I appreciate esthetics in the housing and ergos of the device and the proper functioning and responsiveness of firmware. I don't too much care what the pcb looks like under a microscope. The engineer in me might think I could have done it smaller/cheaper or more reliable (on a level more significant than tin whiskers). Never did care too much about pretty, unless the ugliness increases the cost/area. And sometimes there's extra area on a board due to odd shape or housing requirements, anyway, where you could tighten up some things and reduce some area but it wouldn't decrease the cost... so go crazy in there. I don't care. I guess  Sometimes I mix 45 degree angles and curves on the same board. I often operate on super fine snap-to just by eye, rather than grid. It's not until the very end I would even care if everything is perfectly evenly spaced or symmetrical... and I get to that point sometimes never, before new board revision requiring major changes.

Acute angle routing traces, on the other hand, are not something I like to see ever. While modern processes have improved to the point where acid traps and tin whiskers are rarely problems now, acute angles are usually just a sign of routing sloppiness and can be trivially fixed. Usually when I find one, I don't worry so much about the angle itself as how much attention the rest of the nearby routing got... and I usually find something else I don't like nearby.

Having etched a lot of my own boards, I have a pretty good idea of where acute angles are problematic. And it's pretty much nil on larger pitch boards 7+ mil. That said,  if I see some ugly amateur routing, it might pique my interest. I see the other side of the coin. Examing the board, I might find some unique design decisions and maybe some easily identifiable components rather than inhouse numbers. And seeing how bad something looks and still works you learn more than seeing things made pretty for (possibly) no reason. And you can instantly have some idea of what the trace isn't for. If you find something you don't like, and the board works, anyways, maybe you will learn something.

I do take pride in my work, but for me it comes down to primarily cost and reliability. I don't understand what end user/consumer cares about what the board looks like, and why should you? They care that the thing works. The contractor cares that he makes a profit, which includes ease of assembly, QA/testing, reliability, and cost. The cost to reproduce the board, not just your bill for making it pretty.

I did a collaboration, once, per desire of my contractor. I did the firmware and worked with another hardware designer. Dude was mad skilled in Altium in making pretty traces like lightning. rRight before you eyes, he would paint a picasso of routing. Problem was he didn't bother getting the important bits right. Location of critical things like mounting holes and finger contacts. This company made insanely stupid mistakes, creating new prettier revision 3 times, WITHOUT BEING ASKED, every time making the board look cooler, more complex tab routing for no reason, cool graphic silkscreen, but improving NOTHING. At least once they made the fit to the housing WORSE where a press fit contact was, resulting in 90% fail rate. All the while, they refused to implement some changes I insisted would fix the biggest issues with the PCB; they had more experience and did it their way, which is great but it didn't work. Contractor thankfully didn't quite go bankrupt, and is now using my hardware. It costs less to produce and it brought the rail rate from double digits down to maybe 1%.