SEPIC Converter ringing, efficiency and snubber location

[Pannenkoek_met_een_lampje]

Hello,
Did try to make a SEPIC converter. It seems so work.
please see:
"http://i66.tinypic.com/mikvwy.png"

I use some different values for the Cdc I use 2 x 10 uF ceramics. I use 4 x 47uF allucap at the output side and 4 x 220 uF allu caps on the input side.  2x 4uF7 Ceramic at the input side 2x 10uF ceramic at the output side.


There was some ringing of about 2.5MHz which I did solve. With a snubber across the diode D1. To achieve this I did use this application note:
http://www.ti.com/lit/an/slva255/slva255.pdf
I use a 2n7 and a with a 100R resistor in series. This seems to work.
but then I did take a look at the formula 2 of the slva255 application note and did see a value of about 4uH7. which is in fact the value of the inductor IL1.

When I observe the behavior of the converter:

I find the coil is getting quite hot when output load is 2A even when the input voltage is above 12V. The coil is a  COILTRONICS DRQ127-4R7
I find the input caps getting hot at low input voltages

Questions:
(Q1) I sometimes read you should place the snubber parallel to  the diode D1 sometimes I read you need to put it it parallel across Cdc. So whats the best location for the snubber?
(Q2)What temperature is considered normal for a inductor in a schematic like this?
(Q3)Although the ringing is gone when I take a look with a scope. Can some oscillation still be the cause of the heating of the inductor?
(Q4)Is there another way to stop the ringing? I am under the impression the snubber is making the circuit less efficient.

Thanks for the help

[T3sl4co1l]

What is your layout?

2.7nF sounds like a lot, and 100R too high.  But whatever, if it works...

Q1: This is because there are two independent RLC networks that may need dampening.
Q2: No idea, what power level are you working at?  What does the datasheet recommend for maximum temp rise?
Q3: Sure, why not?  There still has to be some voltage or current, somewhere, that is oscillating, but not all oscillations can be sensed by voltage.  An inductive probe can help here.
Q4: The fundamental problem is: the act of turning currents on and off, and swinging voltages up and down, causes reactive energy to be stored in, and released from, inductances and capacitances in the circuit, respectively.  These include transistor and diode capacitance, leakage inductance, and layout stray inductance.  Burning that energy as waste heat can be done with a resistor, usually an R+C damper or a few kinds of RCD snubber.  It can sometimes be recycled, as in resonant topologies, and quasi-resonant snubbers.

The best solution is to simply make the reactances small, so that they do not store appreciable energy.

This is why the very first question asked, in return, is always: "layout?"

Tim

[Rog520]

How did you decide upon the inductor you chose? You probably need more inductance and/or a different core in order to keep the ripple current at a reasonable level, which will help to keep the temp rise down in both your inductor and capacitors. Are you using low ESR electrolytics?

A quick run of the numbers, based on the voltages shown in your schematic, indicates that you should be at 64uH at 300kHz for 20% ripple current (a reasonable figure). You could try a DRQ127-680 (68uH), although you're probably pushing this particular core beyond its limit.

[Pannenkoek_met_een_lampje]

Hello T3sl4co1l

"Q1: This is because there are two independent RLC networks that may need dampening."
How can I calculate the values needed? For the snubber over the Diode I did use this appnote:
http://www.ti.com/lit/an/slva255/slva255.pdf It basically tells you to use a cap to half the ringing frequency and use this value to calculate the R for the snubber. Problem here is however that there are a caps (Cdc) already. So I can not use this method.

"Q2: No idea, what power level are you working at?  What does the datasheet recommend for maximum temp rise?"
I did change to another Inductor the MSD1514-103ME_  from Coilcraft, I got the Idea a higher inductance might lower the ripple current and even with the higher inductance the DCR is lower compared to the COILTRONICS DRQ127-4R7 I still have got a hot inductor though. Even when I use a 20V input where I measure a 1.54A input current the inductor gets hot. The inductor also makes a lot of noise. This text is from the datasheet of the Coilcraft inductor:
"Maximum part temperature +125°C (ambient + temp rise)." Does this mean these parts are normally used "
Does this mean these inductors are intended to get so hot? Am I spending a lot of time searching for a solution, while there is no problem?
And there is the text:
".    Maximum current when applied to one winding that causes a 40°C
temperature rise from 25°C ambient. This information is for reference
only and does not represent absolute maximum ratings.
"
Still I think there might be something wrong because the inductor heats up that much even when used well below the Irms ( for both windings this is 4A and for one it is 6.8A)

Q3: Sure, why not?  There still has to be some voltage or current, somewhere, that is oscillating, but not all oscillations can be sensed by voltage.  An inductive probe can help here.

Sorry to say but I do not have got that equipment, sounds costly and I am not the richest person to walk the earth :-( Is it is possibility to build a test snubber which might consume a lot of energy just to see if the inductor cools down. If this works I could think with a next PCB version this problem might be fixed? At least then I could know what footprint to use for the inductor.

thank you Tim














 

[Pannenkoek_met_een_lampje]

How did you decide upon the inductor you chose? You probably need more inductance and/or a different core in order to keep the ripple current at a reasonable level, which will help to keep the temp rise down in both your inductor and capacitors. Are you using low ESR electrolytics?

A quick run of the numbers, based on the voltages shown in your schematic, indicates that you should be at 64uH at 300kHz for 20% ripple current (a reasonable figure). You could try a DRQ127-680 (68uH), although you're probably pushing this particular core beyond its limit.

I did use this app note to calculate the inductances:

http://www.ti.com/lit/an/snva168e/snva168e.pdf  please see formula 7. When I use that formula and the following values:
Vout = 12V
Vd (voltage over diode) = 1V
Vin (min) = 7V
I out = 2A

I get a needed inductance of 9.83uH this is about 10 uH


in this appnote however:

http://www.cooperindustries.com/content/dam/public/bussmann/Electronics/Resources/technical-literature/EatonMagnetics/BUS_Elx_App_Notes_4030_SEPIC_Designs.pdf

The use the maximum input voltage and NOT the minimum, I find this strange because the higher currents are when the input voltages are low. Maybe someone can tell whats going on here. Does the latest app-note contain a error?

[Pannenkoek_met_een_lampje]

...

Sorry forgot to ask. I also did measure the voltage across the diode when conducting. The voltages are 1 to 1.5 volts isnt that too much? Isnt this killing the efficiency ? Whats a normal value? I also tried to solder the same type of diode parallel but the voltage drop was the same ( I expected a lower value with 2 parallel) I use a MBRS360T3G diode

[ocset]

here is a sepic design doc

[ocset]

With a sepic, if its coupled inductor, then
…the L(leak)/c(sepic) resonant frequency  must be less than the switching frequency.
For an uncoupled sepic, the 2L/C(sepic) RESOnant frequency  should be lower than f(sw)
The sepic capacitor will have vin across it…….the ripple voltage on the sepic capacitor should be 5% max….so that’s a limit on the smallness of its capacitance.
Put an RC snubber across the sepic capacitor……the c(snub) should be same as the sepic capacitor in capacitance…..the r(snub) should be sqrt(L/c)  approx……..for a coupled sepic, that L is the leakage inductance
Beware your xover freq should be less than the lc ringing frequency of the c(sepic) and the sepic inductors or leakage inductaors depending on whether it’s a  coupled sepic or not,
If it’s a coupled sepic, then design it like a  1:1 flyback kind  of…and the fet and diode current will be the same as that flyback, …if its uncoupled, then design it as a flyback 1:1…….and then  it will behave in terms of fet and diode currents like the inductors are double what they were in the flyback

[Pannenkoek_met_een_lampje]

Hello treez, thank you so much!! I did just read the document and it looks very helpful!
I am using a coupled inductor with and inductance of 10 uH. I did measure the leakage inductance with a LCR meter @ 100kHz (highest setting) and it gives 0.214 uH. The Caps C(sepic) are 2 x a 50V 10uF. Because they value will be less at higher DC voltage I assume them to be somewhere from 5 to 10 uF together.
The frequency I use is 300kHz.

With a sepic, if its coupled inductor, then
…the L(leak)/c(sepic) resonant frequency  must be less than the switching frequency.
...

I did use this formula from the file you did add:
 "F(res) = 1/ {2.pi. sqrt[L(leak).C(sepic)]"

Fres with C 5   uF= 154 kHz
Fres with C 10 uF= 109 kHz

I need to double check the datasheet of the capacitors I will do so when I did finish this writing.
For so far this looks fine right? Can I measure if it is fine? What do I see on the scope when the cap value would be totally wrong?

The sepic capacitor will have vin across it…….the ripple voltage on the sepic capacitor should be 5% max….so that’s a limit on the smallness of its capacitance.

I did use Apnote AN-1484  formula (13) to calculate this ripple Voltage, Delta_VCs=(Iout xDmax)/(Cs x Fsw)

For C = 5 uF I will get a ripple voltage of 0.93V
For C = 10 uF I will get a ripple voltage of 0.46V

The minimal input voltage would be about 8V this means the max ripple current would be 0.4V
this could be problematic I think I need to double check the datasheets of the C(sepic). If the capacitor value would be too low, how could I observe this when the PCB is in use? Could I measure this?

Put an RC snubber across the sepic capacitor……the c(snub) should be same as the sepic capacitor in capacitance…..the r(snub) should be sqrt(L/c)  approx……..for a coupled sepic, that L is the leakage inductance

This part I do not understand as I get a very low value for the R, if I use 5uF for C and 0.2uH for L I get a R of 0.2ohm, am I doing something wrong?

Beware your xover freq should be less than the lc ringing frequency of the c(sepic) and the sepic inductors or leakage inductaors depending on whether it’s a  coupled sepic or not,
If it’s a coupled sepic, then design it like a  1:1 flyback kind  of…and the fet and diode current will be the same as that flyback, …if its uncoupled, then design it as a flyback 1:1…….and then  it will behave in terms of fet and diode currents like the inductors are double what they were in the flyback

I am sorry to say, but I do not understand this part. I do not know the therm: "xover freq " I think it is a "cross over frequency", then I have the right words I think.  But I do not know what it means :-(, and I think it is important to know, could you please explain this? If this value would be wrong how could I measure this or see it on a scope?

Thank you for the help!

[ocset]

Yes the converter's crossover frequency is basically indicative of the bandwidth of the smps...how fast it can respond to a transient.
Th crossover is where the gain vs frequency of the converter crosses over the unity gain line.
I am sure you remember the conditions for instability are that the phase shoudl be a certain value at the unity gain point in order to give oscillating (unstable) output.

Yes you do get a low value for the r(snub)...though if its a step down sepic, then the snubber is less needed. The snubber is most needed for step up sepics with 1:1 and a high step up ratio.
Also DCM sepics have less need of the r(snub).
You can just raise the r(snub) a bit and run a sim on LTspice using say an LT1243 to verify things. The sqrt(L/C) value is just a general "ball park" guide.
You can check your ripple on ltspice.

Remember also that a ceramic capacitor operating near its rated voltage has only 10% of its nominal capacitance.

5% was only a guide for the ripple.....10% may be just about ok.....so anyway, with vin=8v, then with 0.4v ripple you are fine.

Anyway, it sounds like you are aware of the dreaded problem  of the ringing of Llk with C(sepic), and that if the resonant frequency of that is higher than the switching frequency, then your inductor can get hot from it.
Ill look for some notes on xover frequency etc.

To be honest, your 300khz frequency is good as higher switching frequency allows more easier setting of a higher loop bandwidth without going unstable.
Though of course there is the situation of hysteresis losses in the inductor at that frequency.

Attached is an ltspice sim of a sepic, that you can adapt to represent your own case.
ltspice is free download from linear.com

With a sepic you must also be careful if you apply vin as a sudden step input...the sepic Llk and C(sepic) will ring like heck and possibly overvoltage stuff if you are not careful....some people add a fet as a current clamp damper in the ground input line.

[Pannenkoek_met_een_lampje]

Hello Treez, thanx again for the great help!
I do not have much time left this weekend so I'll try to focus on the 'easy' parts.

Yes the converter's crossover frequency is basically indicative of the bandwidth of the smps...how fast it can respond to a transient.
Th crossover is where the gain vs frequency of the converter crosses over the unity gain line.
I am sure you remember the conditions for instability are that the phase shoudl be a certain value at the unity gain point in order to give oscillating (unstable) output.

I think I know the general idea, but I need to do some reading to be able to calculate this. There is a R and C 10k and 6nF8 in the schematic responsible for the respond behavior I think, but I would not know where to start to calculate this.

Yes you do get a low value for the r(snub)...though if its a step down sepic, then the snubber is less needed. The snubber is most needed for step up sepics with 1:1 and a high step up ratio.
Also DCM sepics have less need of the r(snub).
You can just raise the r(snub) a bit and run a sim on LTspice using say an LT1243 to verify things. The sqrt(L/C) value is just a general "ball park" guide.
You can check your ripple on ltspice.

thanks I will do so when I have got the time

Remember also that a ceramic capacitor operating near its rated voltage has only 10% of its nominal capacitance.

I will try to download the right graphs and study them.

5% was only a guide for the ripple.....10% may be just about ok.....so anyway, with vin=8v, then with 0.4v ripple you are fine.

Okay that is one less worry 

Anyway, it sounds like you are aware of the dreaded problem  of the ringing of Llk with C(sepic), and that if the resonant frequency of that is higher than the switching frequency, then your inductor can get hot from it.
Ill look for some notes on xover frequency etc.

To be honest, your 300khz frequency is good as higher switching frequency allows more easier setting of a higher loop bandwidth without going unstable.
Though of course there is the situation of hysteresis losses in the inductor at that frequency.

For the hysteresis losses, if I would put them in a graph are they linear of more X² ? At this time I am getting the feeling the hysteresis losses might be the only reasonable explanation for the high temperature of the inductor. Is it wise to lower the Fsw frequency from 300 kHz to 250kHz to lower the hysteresis heat of the inductor. This way the Fsw is still well above the Fres (150kHz)

Attached is an ltspice sim of a sepic, that you can adapt to represent your own case.
ltspice is free download from linear.com

With a sepic you must also be careful if you apply vin as a sudden step input...the sepic Llk and C(sepic) will ring like heck and possibly overvoltage stuff if you are not careful....some people add a fet as a current clamp damper in the ground input line.

again thank you when I have more time I will do so!

Now I will try to change the diode, there is a voltage drop of 1.5V over it which seems much to much to me.

Thanx Treez! 

[Pannenkoek_met_een_lampje]

I did just change the frequency from 300 kHz to about 240 kHz. At this frequency the inductor is also too hot. I did try to measure the voltage on the feedback loop, I did find out when I touch the input feedback loop trace with a scope probe the sound of the coil changes. When I touch the trace with the scope probe on 1x the coil starts to make a lot of noise and the input current goes up with a 10x setting this is less. Does this mean I need some filtering on the feedback loop pin? Is this the reason my inductor gets too hot? How can I calculate this?

The datasheet of the controller IC  I use can be found here:
http://www.analog.com/media/en/technical-documentation/data-sheets/3844fc.pdf See page 22 for the sepic converter.

Wil the inductor get less hot when I add a small cap from the Fb pin to GND? Or do I need to change the values of the components connected to Vc? I can see some switching noise on the Fb trace of about 100mV.

hope you guys can help

[ocset]

It could just be hysteresis loss in your coil. Sorry i havent checked for your coil.
Many places offer a core loss tool.
Did you scope the Vc pin, ..is it stable and not railed?...indicating stability.

Are all your switchign current loops small.
Did you star ground to the gnd terminal of your source sense resistor....you should lay up so you input cap, output cap ..their gnd terminals meet  are close to the source sense res gnd.
Keep the switching node away from  sensitive traces leading back to the controller.....eg anything with a high z input like opamp, comparator etc.

[rfbroadband]

I have designed few SEPIC converters using the LT3757/58 with a coupled inductor. Linear provides excellent documentation including an Excel sheet that helps you determine component values depending on your specifications (if you don't want to create your own excel sheet based on the equations in the datasheet).

The layout is absolutely critical, I can't emphasis this enough. Obtaining desired EMI performance is one thing but to guarantee stability of the loop you need to understand all loops in your design and optimize the layout accordingly. I had to optimize the layout once to eliminate a stability issue I encountered at lower load currents. I tried to attached Linear's app note AN 139 for you as a reference, but the file is too large...I suggest you download the app note and study it carefully.

I personally measure the loop gain of each regulator and tune the frequency response for all key load conditions so I can tune the loop and get the desired phase margin over all load conditions. Yes this requires certain equipment, but if I don't do that I feel like I am flying blind and I think it is difficult to participate in  discussions about ringing, stability issues without seeing the at least the layout and measured results of the loop gain or output time domain step response.

If you carefully follow Linear's recommendations you will get rock solid performance using this chip. As with most switching regulators, if  you are not careful with your layout you will likely run into loop stability issues.

[ocset]

very true, i attach a doc on smps layout...there is a good  "true story" near the end of this doc