As long as you have a contiguous ground on either layer (preferably both), 2 layer is fine. If you're reserving a fair amount of space for routing buses between chips, this works nicely.
Contiguousness is achieved by stitching ground together. Everywhere a trace cuts through the pour, it's divided into another region; keep ground over/under traces/buses where possible, and add stitching vias around them.
If you need to cram things together a bit more tightly, 4 layer is definitely the way to go. With DIP or SOIC logic, single side placement, I'd think 4 layer would not buy you a 50% board area savings (which since 4 layer typically costs ~double, would be your economic threshold). With two sided placement of SOIC, you'll definitely get there (but you'll also spend a lot more time in layout, which is a far worse deal economically speaking, in proto quantities).
Tim