Transistor high side P-mos driver

[webgiorgio]

Hi,
this is a schematic of a Photovoltaic battery charge controller.
I can't fully understand the circuit driving the mosfet Q1 (P-ch http://www.vishay.com/docs/91078/91078.pdf)

When the output 9 of the microcontroller goes high, Q2 conducts and brings down the potential of the collector.
This causes a current trough the zener diode, the 10 ohm, D3, Q2, and 100ohm.
So, Vgs is -18V and the mosfet conducts.
What is the purpose of Q3? and the 100 ohm resistor? (why not just Q2 Emitter to ground?)

[Yansi]

Nothing that much interesting in there.

If you would drive it with just the NPN down to ground and resistor to Vsource, you would get only fast turn on (gate pulled to GND through that NPN, Q2), but rather slow turn off through the source-gate (collector) resistor 470R 1W.  To fix that, you would either need to make that resistor horribly low value, that would dissipate a metric shit ton of energy (especially in higher voltage applications)

.. or you just use an emitter follower for the turn-off, and the turn-on still works through the antiparallel E-B diode D3.


What I consider strange (probably a design fail also?) is the emitter resistor of Q2. It is typically use to limit the maximum current it can sink, however in this case that means the turn-on current of the PMos is 44mA maximum. I think that is not that much, considering the turn-off is designed to be quite harsh through the only 10ohm gate resistance + the output resistance (re) of Q3, which with the 470ohm base resistor will be quite small also, so the turn-off current will likely be few hundred mA.

But it might have been intentional, to get a rather slow turn-on, to eliminate some EMI from the buck converter at the expense of higher switching (turn-on) loss.  Mind you, the buck conv. will here be likely operating in continuous current mode, so the transistor will turn on with full voltage and current accross it.

There is also a another trick to improve this circuit: You can add a PNP to the follower circuit and make the follower a complementary NPN-PNP pair. Then you do not even need any high currents to operate the gate from the transistor down there, here Q2.  It can then be extended to ever higher operating voltages, up to few hundred volts and make it a full bootstrapped driver.

//EDIT: To be clear, I mean the design fail not being in using the emitter resistor at Q2, that is correct, you need to limit the collector current to (value approx (Vbase-Vbe)/Re, where Vbase is 5V from the MCU), but in that fact the turn on current for the pMOS is also limited by it to a rather small value.

If the limit wasn't there and input voltage would become higher than 18V of ZD2, you would burn the shit out of ZD2 (and then the mosfet) if the current would not be limited in Q2)

[Yansi]

It might make more sense to you  if you redraw the schematic with a NMOS. So considering this, which I expect you understand the functionality well, you just take away the NPN and replace it with a diode (anode to the input, cathode to the gate).

The signal driving circuit then needs to give full turn on current, but turn off is buffered by the PNP.

This trick is often used with switch-mode controller ICs, like TL494, 34063 or such, that do not offer totem-pole output stages, but just a single NPN transistor output, that can deliver high current in only one direction.
 
Your circuit is exactly the same, except the PN polarities are opposite (PMOS + NPN follower).

[webgiorgio]

thanks, I understand it now!
Is any reason why I should follow the schematic I posted instead of using a gate driver IC? (like IRS2007, 0.7 € https://www.mouser.it/datasheet/2/196/Infineon-IRS2007S-DS-v01_00-EN-1223737.pdf)

[Yansi]

There is probably one major reason to leave it there:  Bootstrapped gate drivers can not reach  the full 100% duty cycle. You always need enough off time to recharge the bootstrap capacitor.

In case the control algorithm in the circuit above needs a 100% ON time, or even say >95%, bootstrapped circuit will not cut the mustard.  The discrete solution can leave the mosfet turned on 100% time, which may be beneficial in solar application with a low irradiance, where any switching loss would be significant compared to the power generated in the cells.

[webgiorgio]

I see what you mean,  but how comes that this limitation on the duty-cycle is not mentioned in the datasheet?
If I understood the working principle of the bootstrap circuit, the duty cycle limitation only applies to the high-side mosfet.

I need 100% duty cycle. Does it exist a half bridge gate driver IC that is not bootstrap?
Maybe using a P-ch on the high side (no need of voltage higher than the bus voltage to turn it On) and N-ch on low side.

For the low side I came up with this. I don't like much that is inverted. Do I fix it with software or better put a npn transistor to make it non inverting? Or a complete different circuit that I am not aware of.

[Yansi]

It is not mentioned, because first it is a common knowledge when using these and second the limit is application dependent (bootstrap capacitor size, recharging source impedance, signal waveforms), etc.

Non-bootstrapped halfbridge driver ICs - haven't seen them, but don't say they do not exist. However it is probably way easier and more cost effective to whack there those two or three transistor and voila!

I would invert it in software, usually is easier, and also cheaper than adding another inverting stage, that eats extra current and slows the whole switching process.

The circuit can however be made only from 2 transistors like this. You already know that trick, don't ya?

 

[webgiorgio]

Damn right, this circuit is so cool! Thanks a lot for the explanation!

I think I will add a pull-up resistor to the uC output, so that the low side mosfet is open when the uC is not programmed.

[Yansi]

Yes, the pullup there is kind of a must. Also, it is beneficial, to replace the lower NPN with a NMOS, like a 2N7002.

[Dave]

Also, it is beneficial, to replace the lower NPN with a NMOS, like a 2N7002.

It really isn't.
The lower transistor in combination with the emitter resistor forms a current sink. You want the current to be limited there, because otherwise you're just drawing a ton of current through that Vgs limiting Zener.

Edit: Nevermind, I just skimmed through the thread and missed the last part.

[Yansi]

Read the thread before commenting please!

So no, you're not correct, as the text quoted, refers to the circuit in the post above, which is NOT the circuit driving the PMOS in the OP's original question. It is a simplification of the three transistor circuit with the complementary pair output, driving a GROUND referenced NMOS.

Also, please read carefuly, as I have already explained the emitter resistor in the original OP's circuit in question, so I know well, what's it's purpose and I ahve also commented thoroughly on a suspicious design right there.

//EDIT and btw, it would work even with the NMOS. You can make current sink even with an NMOS.