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Offline axitece

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Biasing of JFET and NPN transistor for bandwidth
« on: November 18, 2017, 06:51:53 AM »
Hello everyone,

I've been trying to understand the biasing of JFET source follower and emitter follower in the impedance converter circuits for oscilloscopes for the past few weeks without any progress. It seems like quite a lot of oscilloscopes take the split AC and DC path approach for implementing the impedance converter as seen in the Rigol DS1052E frontend schematic here. I have a good understanding of how the op-amp is used to get DC precision but I'm having trouble understanding the biasing of the JFET source follower and the NPN emitter follower portion of the circuit which is shown in the attached image.

It seems like the bottom npn transistors are used as current source loads but how are the current values chosen for each stage? I thought that the current source values would be chosen such that the output of the two amplifiers would be ~0V when the input is 0V. However, I'd assume that the bias currents would also have an effect on the bandwidth of each stage? I'd really appreciate any kind of input on how circuits like these are biased for applications where bandwidth is also important. It'd also be great if someone could explain the circuit that's attached or how it should be analyzed. Thanks!
 

Online Cerebus

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Re: Biasing of JFET and NPN transistor for bandwidth
« Reply #1 on: November 18, 2017, 10:47:19 AM »
It seems like the bottom npn transistors are used as current source loads but how are the current values chosen for each stage?

You are correct they are current sink active loads for the respective transistors.

Choice of current is going to be based on having enough current to overcome any capacitance (intrinsic device, stray, next stage input) at the frequencies in question and also by the input impedance of the following stage (probably 50 ohms). For this kind of wide bandwidth circuit you'll generally throw as much as you can at it, but no more than you need to get the output impedance low enough to happily drive about 50 ohms impedance (and here we are definitely dealing with impedance as opposed to resistance and we must take capacitances into account).

Quote
I thought that the current source values would be chosen such that the output of the two amplifiers would be ~0V when the input is 0V.

That's taken care of by the DC control loop set up by the preceding op amp, that you've omitted in your diagram. You can, however, still see the negative feedback limb of that being taken off from the output node. The DC input bias at the JFET gate will probably only be within a 100mV or so of zero, the op amp will take care of setting that at the right level for the output to be ~0V.

Quote
However, I'd assume that the bias currents would also have an effect on the bandwidth of each stage? I'd really appreciate any kind of input on how circuits like these are biased for applications where bandwidth is also important. It'd also be great if someone could explain the circuit that's attached or how it should be analyzed. Thanks!

The 3k01 and 2k resistors from ground to -5 form a voltage divider. This sets the VBE of the two BC349 active load transistors (in combination with the 249 and 75 ohm emitter resistors) and hence sets the emitter currents to ~5mA and 15mA respectively.

From there, the top two transistors are a source follower and an emitter follower (connected very much like a Darlington pair would be) to provide masses of current gain and a voltage gain very close to one. Hence the impedance converter tag, very high input impedance (input DC bias current in the 10 pA region) and low output impedance (typically low enough to comfortably drive 50 ohms or thereabouts).

Most of the bandwidth comes from choosing source/emitter followers, which isolates drain/collector capacitance and avoids the Miller effect and just making sure that there's enough current drive at each stage to overcome intrinsic and stray capacitances.

A quick fiddle with SPICE shows the DC input impedance at the gate of the JFET to be 725Gohm, the DC output impedance to be 3.35 ohms at the emitter of the BTH10, and the overall DC voltage gain to be 0.93, all unloaded.
Anybody got a syringe I can use to squeeze the magic smoke back into this?
 
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Offline axitece

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Re: Biasing of JFET and NPN transistor for bandwidth
« Reply #2 on: November 18, 2017, 01:30:03 PM »
It seems like the bottom npn transistors are used as current source loads but how are the current values chosen for each stage?

You are correct they are current sink active loads for the respective transistors.

Choice of current is going to be based on having enough current to overcome any capacitance (intrinsic device, stray, next stage input) at the frequencies in question and also by the input impedance of the following stage (probably 50 ohms). For this kind of wide bandwidth circuit you'll generally throw as much as you can at it, but no more than you need to get the output impedance low enough to happily drive about 50 ohms impedance (and here we are definitely dealing with impedance as opposed to resistance and we must take capacitances into account).

Quote
I thought that the current source values would be chosen such that the output of the two amplifiers would be ~0V when the input is 0V.

That's taken care of by the DC control loop set up by the preceding op amp, that you've omitted in your diagram. You can, however, still see the negative feedback limb of that being taken off from the output node. The DC input bias at the JFET gate will probably only be within a 100mV or so of zero, the op amp will take care of setting that at the right level for the output to be ~0V.

Quote
However, I'd assume that the bias currents would also have an effect on the bandwidth of each stage? I'd really appreciate any kind of input on how circuits like these are biased for applications where bandwidth is also important. It'd also be great if someone could explain the circuit that's attached or how it should be analyzed. Thanks!

The 3k01 and 2k resistors from ground to -5 form a voltage divider. This sets the VBE of the two BC349 active load transistors (in combination with the 249 and 75 ohm emitter resistors) and hence sets the emitter currents to ~5mA and 15mA respectively.

From there, the top two transistors are a source follower and an emitter follower (connected very much like a Darlington pair would be) to provide masses of current gain and a voltage gain very close to one. Hence the impedance converter tag, very high input impedance (input DC bias current in the 10 pA region) and low output impedance (typically low enough to comfortably drive 50 ohms or thereabouts).

Most of the bandwidth comes from choosing source/emitter followers, which isolates drain/collector capacitance and avoids the Miller effect and just making sure that there's enough current drive at each stage to overcome intrinsic and stray capacitances.

A quick fiddle with SPICE shows the DC input impedance at the gate of the JFET to be 725Gohm, the DC output impedance to be 3.35 ohms at the emitter of the BTH10, and the overall DC voltage gain to be 0.93, all unloaded.

Thanks for the awesome response! I have a few more questions if you don't mind. When you talk about overcoming the intrinsic and stray capacitances, is it in the context of having to charge these capacitances at high frequencies? I'm assuming that if we don't have enough current then we might hit a slew rate limit like problem where we can't charge these capacitances fast enough to follow the signal? So this is why we want to throw as much current at it as we can so that we are covered in that regard for the most part?

Also I understood the calculations for how the BJT active load current is set, but how did you go about finding the effective output impedance of the amplifier? And once again thanks a lot for your response. It was really helpful in terms of getting a few things to click in my mind.

 

Online Cerebus

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Re: Biasing of JFET and NPN transistor for bandwidth
« Reply #3 on: November 18, 2017, 02:28:12 PM »
Thanks for the awesome response! I have a few more questions if you don't mind. When you talk about overcoming the intrinsic and stray capacitances, is it in the context of having to charge these capacitances at high frequencies? I'm assuming that if we don't have enough current then we might hit a slew rate limit like problem where we can't charge these capacitances fast enough to follow the signal? So this is why we want to throw as much current at it as we can so that we are covered in that regard for the most part?

Pretty much. As soon as you get significantly above DC you pretty much have to think in terms of impedance as opposed to resistance, so there's always a reactive component to think about. As you surmise, the reactive part can have a significant effect on slew rates or just appear as a significant load. At 100MHz a stray 5pF to ground (a not unrealistic figure for say an amplifiers input capacitance) looks like 320 ohms to ground, or alternatively 3mA for every volt you try to impress across it.

Quote
Also I understood the calculations for how the BJT active load current is set, but how did you go about finding the effective output impedance of the amplifier? And once again thanks a lot for your response. It was really helpful in terms of getting a few things to click in my mind.

I let SPICE* do the heavy lifting for that but it's not too difficult to work out by hand. An attempt at a tutorial here would get very long winded, very quickly. Hit your textbook of choice for the details; if you don't have a favourite I (and many others) would recommend "The Art of Elecronics" by Horowitz and Hill. 

By the way, a search for "Signal Conditioning in Oscilloscopes" by Steve Roach will turn up a paper on impedance converter design that you'll probably find interesting and helpful - it's an easy read.

*I recognised the circuit and happened to already have a SPICE model of it sitting around from when I took a look at it a couple of years back, so it was pretty quick to hack it down to size to hang some numbers on what I was telling you. I don't know about you, but I always find it easier if people give me some numbers, so that when I go to try analysing it myself I've got something to tell me if I'm in the ball-park.
Anybody got a syringe I can use to squeeze the magic smoke back into this?
 

Offline axitece

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Re: Biasing of JFET and NPN transistor for bandwidth
« Reply #4 on: November 19, 2017, 05:09:00 AM »
Pretty much. As soon as you get significantly above DC you pretty much have to think in terms of impedance as opposed to resistance, so there's always a reactive component to think about. As you surmise, the reactive part can have a significant effect on slew rates or just appear as a significant load. At 100MHz a stray 5pF to ground (a not unrealistic figure for say an amplifiers input capacitance) looks like 320 ohms to ground, or alternatively 3mA for every volt you try to impress across it.
Yep that makes perfect sense. I guess this is why a lot of active probes with FET inputs use techniques like bootstrapping in order to reduce the input capacitance as much as possible.

I let SPICE* do the heavy lifting for that but it's not too difficult to work out by hand. An attempt at a tutorial here would get very long winded, very quickly. Hit your textbook of choice for the details; if you don't have a favourite I (and many others) would recommend "The Art of Elecronics" by Horowitz and Hill. 

By the way, a search for "Signal Conditioning in Oscilloscopes" by Steve Roach will turn up a paper on impedance converter design that you'll probably find interesting and helpful - it's an easy read.
I went back and read the chapter where the JFET source follower is discussed in detail in The Art of Electronics and it was very helpful. I wish we had more info from the authors/publisher on the status of the "x chapters". The book briefly mentions that the source follower design with bandwidth and capacitive loads in mind will be discussed in chapter 3x.

The chapter by Steve Roach was the first place where I learned about the split AC and DC path architecture for the impedance converter. One thing that I found very interesting was that he talks about using depletion mode MOSFET rather than a JFET for the source follower due to its higher speed (higher ft?). Every DSO analog frontend schematic that I've seen seems to use JFET which seems to go against what Steve mentions in his chapter.

I'm also interested in your take on the higher end of bias current for both the source and emitter follower. I'd imagine that the top end limit of the bias current of the JFET would be the Idss since the JFET can't conduct more current than that. Is this the right assumption? As for the BJT emitter follower, I still don't have a good idea on how you would define the upper limit if power consumption of the circuit in general was being disregarded.
 

Online Cerebus

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Re: Biasing of JFET and NPN transistor for bandwidth
« Reply #5 on: November 19, 2017, 07:05:08 AM »
I went back and read the chapter where the JFET source follower is discussed in detail in The Art of Electronics and it was very helpful. I wish we had more info from the authors/publisher on the status of the "x chapters". The book briefly mentions that the source follower design with bandwidth and capacitive loads in mind will be discussed in chapter 3x.

Yeah, c'mon Win, x chapters - please.

Quote

The chapter by Steve Roach was the first place where I learned about the split AC and DC path architecture for the impedance converter. One thing that I found very interesting was that he talks about using depletion mode MOSFET rather than a JFET for the source follower due to its higher speed (higher ft?). Every DSO analog frontend schematic that I've seen seems to use JFET which seems to go against what Steve mentions in his chapter.

Those physically tiny MOSFETs are purpose designed for VHF/UHF and have very low capacitance and low parasitics. Steve is talking about 1GHz designs for 500 MHz nominal bandwidth 'scopes, the sort of front ends you've been looking at are probably in the 100-200 MHz region where suitable general purpose JFETs are plenty good enough (400-500 MHz full power bandwidth into the next stage, perhaps 700-800 MHz -3dB bandwidth).

Quote
I'm also interested in your take on the higher end of bias current for both the source and emitter follower. I'd imagine that the top end limit of the bias current of the JFET would be the Idss since the JFET can't conduct more current than that. Is this the right assumption? As for the BJT emitter follower, I still don't have a good idea on how you would define the upper limit if power consumption of the circuit in general was being disregarded.

10-15 mA is going to be more than adequate at the 2-4V p-p voltages you're looking at here (0.7Vrms - 1.4Vrms). And yes, IDSS is an obvious limiting factor.
Anybody got a syringe I can use to squeeze the magic smoke back into this?
 

Offline axitece

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Re: Biasing of JFET and NPN transistor for bandwidth
« Reply #6 on: Yesterday at 03:01:20 AM »
So I've spent some time to quickly put together a simulation of the impedance converter to play around with things discussed so far. The schematic can be seen in the image below and I've also attached the LTSpice file.



In the end I would like to use this impedance converter to drive the input(s) of LMH6518 which requires <50 ohms input impedance. Therefore I decided to load the output with a 50 ohm load and it reduced the 3 dB bandwidth by a good amount. The output plot of the simulation can be seen below. I would've assumed that the emitter follower would have low enough output impedance at collector current of 15 mA that it wouldn't be affected by change in load impedance it is driving. Am I misunderstanding this?



I've also noticed that most of the schematics I've looked at don't have the 100 ohm resistor (R6) before the input of the JFET. However, when I remove it the output frequency response doesn't really make sense. I'd really appreciate it if anyone has input on this matter. Thanks!
 

Offline A Hellene

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Re: Biasing of JFET and NPN transistor for bandwidth
« Reply #7 on: Yesterday at 09:18:22 AM »
Since I can recognise my handwriting at the first post's partial schematic, originating from the DS1000E schematic sheets I have drawn in the thread Rigol DS1052E nasty surprise! while troubleshooting this DSO, I am afraid that in the simulation above the feedback loop between Q1 output and the OpAmp inverting input that sets the DC gain and offset of the stage being different (see the 806k:203k4 feedback loop resistance ratio at the 'DAC, Demux, Sample & Hold, Buffers' schematic sheet with the TP109 DC bias of nominal 0V00 and ranging from -2V50 .. +2V50) will probably affect the stage overall GBWP.

Other than that, I can confirm that Cerebus' analysis of that stage is correct.


-George

<EDIT> Corrections...
« Last Edit: Yesterday at 10:16:58 AM by A Hellene »
Hi! This is George; and I am three and a half years old!
(This was one of my latest realisations, now in my early fifties!...)
 

Offline StillTrying

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Re: Biasing of JFET and NPN transistor for bandwidth
« Reply #8 on: Today at 09:18:52 AM »
I've also noticed that most of the schematics I've looked at don't have the 100 ohm resistor (R6) before the input of the JFET. However, when I remove it the output frequency response doesn't really make sense.

You'll probably have to give the Vin source some realistic impedance, 25R to 1k maybe. I usually give the V+ and V- supplies 0.2R as well.
If I fix the load at 50R the largest bandwidth loss looks like it's through J1.


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