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Offline ilium007

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Re: Designing shift register circuit for SPI bus
« Reply #100 on: Yesterday at 11:17:03 PM »
Because otherwise the far end  board's Data_In is flapping in the breeze, and floating CMOS inputs are a *BAD* *THING*.  :horse:  The input boards don't use MOSI at all and you may not even connect that pin unless you decide to wire it straight through so you can mix input and output boards in the same daisychain (although if you do that in a long chain, beware of timing skew between MISO or MOSI and SCLK).

The 'far end' board is the last one in the chain ? Furthest from the MCU ? It will be the only one with its 74HC165 pin 10 "SER" disconnected and should have  it tied to GND.

I have drawn a quick and nasty schematic (using my freshly created 74HC165 drawn to Ian.H standards :-DD) showing two boards with an inter-connect - disregard everything else thats missing from it, I have drawn it just for this discussion. Picture each 74HC165 in the diagram as being 2 or more 74HC165's. The far right board is the last one in the chain (inter-connect are the blue lines), is this 'MISO' inter-connect pin the one being tied to GND to ensure the last 74HC165 pin 10 "SER" is tied to ground ?


 

Offline ilium007

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Re: Designing shift register circuit for SPI bus
« Reply #101 on: Yesterday at 11:29:31 PM »
Have you considered what input protection circuit to use for the input board's parallel input pins?

This morning I learnt about Quadruple Positive-NAND Gates With Schmitt-Trigger Input IC's for the first time.... 

I have not thought about input protection circuits :-//

I am not sure what the risks are...
 

Offline ilium007

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Re: Designing shift register circuit for SPI bus
« Reply #102 on: Yesterday at 11:30:38 PM »
One other thing I hadn't really considered was power. I could feed in 5v via the SPI connector and this would power the boards, shift registers, buffers and status LED's, but it would also have to cater for the current sink for all of the outputs.

I am thinking about creating 16 outputs per board:
  - worst case scenario driving 16 relays at 35mA coil current each
    - 16 x 0.035A = 560mA + power consumption of the on-board IC's, status LED's etc - approx 200mA
      - 750mA per board approx.
  - I want to design for 128 outputs per chain
    - 8 x output boards
      - 6.0A total for the chain of boards.

I see a couple of options.

Option 1: I need a 12v feed to each board to drive the relay coils so I could put a cheap linear regulator and a couple of capacitors on each board to give 5v. I'm not sure how much heat will be generated by a linear regulator dropping 12v to 5v and sinking the 750mA per board. I would use Molex 77 254 connectors as the inter-connect current would be well under their rated 4.0A

Option 2: Use the larger Molex KK 356 connectors which allow 7.0A - this would provide all 5v power all the way along the cascaded chain of boards. Each board would then have a seperate 12v feed for the relay coils and I would use a high capacity switch mode power supply on the main MCU board to provide 5v / 3.3v power for everything. But 7.0A through tracks on the output of a 1oz copper PCB.... I'm not sure about that !

I think Option 2 is the better option. Thoughts ?
 

Offline Ian.M

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Re: Designing shift register circuit for SPI bus
« Reply #103 on: Today at 12:02:09 AM »
Way up thread I suggested 1/4" PCB mount spade terminals for the high current power and ground wiring.  Also I suggested crimping up a 'backbone' wire for  each that loops fromone female crimp connector to the next as that will be a quick and easy method of high current power and ground distribution along the chain, that avoids high currents on any individual PCB. 


A TPIC6C595 has a worst case current consumption from its logic supply of 5mA when being clocked at 5MHz.  Below 1MHz it will be sub 1mA, and the logic ICs will be similar or lower, so there are no issues with running logic power over the same cheap small headers as the SPI signals.   If you are concerned about the total current for LED indicators (even using high efficiency LEDs, which can be acceptably bright at under a mA), you can always specify extra power and ground pins.  More ground pins also helps with signal integrity.
« Last Edit: Today at 12:47:28 AM by Ian.M »
 
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Offline ilium007

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Re: Designing shift register circuit for SPI bus
« Reply #104 on: Today at 12:03:56 AM »
Way up thread I suggested 1/4" PCB mount spade terminals for the high current power and ground wiring.  Also I suggested crimping up a 'backbone' wire for  each that loops from one female crimp connector to the next as that will be a quick and easy method of high current power and ground distribution along the chain, that avoids high currents on any individual PCB. 
A TPIC6C595 has a worst case current consumption from its logic supply of 5mA when being clocked at 5MHz.  Below 1MHz it will be sub 1mA, and the logic ICs will be similar or lower, so there are no issues with running logic power over the same cheap small headers as the SPI signals.   If you are concerned about the total current for LED indicators (even using high efficiency LEDs, which can be acceptably bright at under a mA), you can always specify extra power and ground pins.  More ground pins also helps with signal integrity.

Sorry - I've read through this thread so many times today, I don't know how I missed that.

If the TPIC6C595 IC's are getting their Vcc and GND via the small headers / interconnects how do they sink current via the heavier spade connector 'backbone'
« Last Edit: Today at 12:12:33 AM by ilium007 »
 

Offline TomS_

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Re: Designing shift register circuit for SPI bus
« Reply #105 on: Today at 12:19:36 AM »
If the TPIC6C595 IC's are getting their Vcc and GND via the small headers / interconnects how do they sink current via the heavier spade connector 'backbone'

Place one terminal in your positive power plane and the other in the ground plane. You can then feed power to the board by either or both.
 

Offline ilium007

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Re: Designing shift register circuit for SPI bus
« Reply #106 on: Today at 12:20:39 AM »
If the TPIC6C595 IC's are getting their Vcc and GND via the small headers / interconnects how do they sink current via the heavier spade connector 'backbone'

Place one terminal in your positive power plane and the other in the ground plane. You can then feed power to the board by either or both.

Ok - and all grounds are tied together off each supply ? 5v, 3,3v and 12v
 

Offline Ian.M

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Re: Designing shift register circuit for SPI bus
« Reply #107 on: Today at 12:59:35 AM »
Yes, all grounds tied together.   5V logic power isn't on a spade - it doesn't need to be as worst case you have about 5mA for chips and maybe  16mA (8x 2mA) for high efficiency indicator LEDs per board, so for a 12 board chain that's still only about 0.25A. (assuming 8 channels per board - count multi-shift register boards as if they were as many individual boards)

Put the 5V regulator on the MCU board and feed it 12V and Ground using spade connectors.  You'll probably want to use a switching regulator as with multiple chains, the logic 5V current can be quite substantial.  The alternative is a L78S05 2A rated linear regulator and a heatsink big enough to handle 15W dissipation without excessive temperature rise.    Another option that avoids the switching regulator or big heatsink would be to only distribute 12V and put a 5V 100mA 78L05 or similar on each board.  I'd still use the spades for 12V even for input boards as each could need up to 100mA of wetting current (see below). 

You'll have to decide what current polyfuse to put on output boards - do you fuse the channels individually to attempt to protect the TPIC6C595 (as the Abs Max peak output current  is 250mA this is unlikely to work), or do you simply fuse the 12V to the board at 1A so worst case it only takes out the chip (which you may decide to socket) and doesn't melt the wiring?

Have you considered what input protection circuit to use for the input board's parallel input pins?

This morning I learnt about Quadruple Positive-NAND Gates With Schmitt-Trigger Input IC's for the first time.... 

I have not thought about input protection circuits :-//

I am not sure what the risks are...

For the inputs, if you get it wrong you blow the shift register chip, and possibly other chips connected to it.   If you get it less wrong, EMI pickup gives you false input readings.

If its coming from the layout, I suggest you use 12V signalling.  ON is >9V, OFF is <3V.  A potential divider 15K lower arm, 22K upper arm will do that nicely with no issues up to a maximum voltage of 13V.   Above that, unless you clamp it the CMOS input protection diodes will start to pass current (undesirable) so you should also have a 5% 5.1V Zener, anode to ground  across the lower resistor, and a 1K resistor between the divider tap and the actual CMOS input.  With 1/4W resistors, that will survive up to +/- 70V with no issues and if you apply AC mains, as long as the ground connection is low impedance, there is a good chance that only the 22K resistor will blow.  For EMI filtering a 1nF to ground at the CMOS input pin is advisable.

Then you get into stuff like switch wetting current.  Unless a switch or relay has sealed, mercury wetted or gold plated contacts, it will probably be unreliable unless you have enough voltage across it when open and pass enough current through it when closed to break down any oxides or other slight contamination as it closes.  A rough rule of thumb is minimum 10V, 10mA.   

Therefore you will need the option to fit a 1K pullup to +12V or pulldown to ground, to supply the wetting current, at the input so there is a low impedance at the input to reduce the effect of EMI.   Use a through hole resistor and don't mount it dead flat on the board as a 1/4W 1K resistor will burn with as little as 16V across it. Glass or ceramic beads on the legs make good standoffs to get the clearance.  If you want it easily configurable, use a three pin jumper to select between 12V, Gnd (and open) on one end of the resistor, with the other to the input terminal.   If you are going to use screw terminal blocks, its probably easier to simply insert the resistor in the terminal block with the switch wiring. All switch wiring should be twisted pair, with one wire to each side of the switch.   Fit a 500mA polyfuse in the 12V feed (for switch pullups)  on each input board to protect against wiring disasters and decouple the 12V pullup rail with a 10uF 25V cap. 
« Last Edit: Today at 03:26:08 AM by Ian.M »
 

Offline ilium007

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Re: Designing shift register circuit for SPI bus
« Reply #108 on: Today at 02:02:35 AM »
Thanks for this ^^^^^^^

I will look at power tomorrow. I am learning so much through this project, thank you again for all your help.
 

Offline C

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Re: Designing shift register circuit for SPI bus
« Reply #109 on: Today at 06:13:32 AM »

A while back lam.M & I both talked about drawings wasting time.
Little things can make a big difference and it takes time to learn them.
Not trying to pick on you, but just show very small detail as example.

I know what a 165 is an how it works, so knowing this look at this and do you see what you expect?


First quick look and no serial input connection, took a while to find it.
Other things here also delayed the find.

You have a very simple drawing but have a lot of separate detail areas to work with.

Power & Ground    Put next to each other and leave a gap between other details

SPI  here you have 3 or 4 signals, again a detail

You have SPI In & SPI out. Again a detail but here Knowing that Serial in goes to first 165 and daisy chains was lost. It does not stand out so it's easy to see.

Your eye can easily follow group of lines. You need differences to stand out.
Here you have a chip that is drawn for Left to right flow. If the whole drawing was left to right flow then it would be easer to understand, BUT some time you will have a need for a drawing like this. For example a drawing that had 167 & 595 chips.
So what can/could you do?
Simple things, move your 5 horizontal lines down so top line is where your SS line is now. 
Move Power and ground to be next to each other. Keep in mind that you will have a 3rd power wire per chip and need to make it stand out a little from the two shown

Change the gap between power and SPI signals.
make the direction of MISO and MOSI really stand out in the pattern by when they go vertical. MISO going vertical to the right  before the chip is a good hint here. A gap in the MISO bus under the 165 is a hint. so bring pin 9 connection down to left of 165. Here you need a cross like you have of 9 & 10, put it closer to chip and further from bus. make cross stand out.

A little thing like moving pin 8 vertical closer to chip makes a difference.

Your 132 does not follow the left to right. In on left side of box, out on right side of box and then up to pin 1.

--
Now you are working detail on power and connections. More detail that needs to stand out when you take a quick look that that drawing to find something.

-----
Lets see if I can help some with delays.
Some times you get berried in the details  You need to keep looking at big picture 

If you can get in mind the big picture & the small picture you have a better chance.

A while back a news item stated a " minor accident on LA's freeway would have traffic backed up and slowed for 9 hours," & "you could walk faster"
People walking have this problem if there are a lot of people in a line.
What is missing is the Sync signal to get all to start move at same time

One often missed thing.
You are talking via sat to some one. Your baud rate is X but it takes time to get to sat and back down. For easy numbers say 1 sec.
From this example you have X times 2 bits stored in AIR.
Storing bits on a wire was done a long time ago. Search Delay Line if you care.

Now jump to electronics
You have a bunch of inverters connected in series. From data sheet you see time to change. 
Again using simple numbers, change takes 10.  So with 100 inverters in series you change input to ONE and get ONE out of last 1000 later.
You can still change input faster then this total delay, you just have to stay in the limits of a inverter.
Now Your input changes fast, Inverter output might change faster or slower on output.  After 1000 inverters your nice fast square wave could look line a sign wave.

A while back, lan.M talked about Schmitt input on logic.
If the above inverters have Schmitt inputs, each would be doing it's little part in making that logic change faster. The sign wave output happens at a higher frequency.

Now replace the inverters with a non inverting buffer. You still have the delay!

If you draw the clock signal (the inverter input or buffer) on paper and then make a copy on a transparency.
Each inverter/buffer shifts the transparency by some amount. 
You could number the changes see that current input is x newer then output

Now the 165 has a delay!
To hide the delay the clk input shouts out STEP NOW to all the bits in shift register.  As you add more clk inputs to 165's the shout gets smaller.
One way to make shout work better is to do it when peak should happen on data input.

First you have when a bit happens on output. Think of your first output chip replaced with a 165. You would have to shift out bits for all output chips before getting to 165 bits.
You would not do this as to update outputs you would also have to send 8 more bits after the output bits to get output bits in proper position.
If you put 165 as last chip then you send 8 output bits & get 8 input bits.
Until you have matching number of input & output bits you have to send or receive extra bits.

If you have nothing but TPIC6C595's & 165's in chain and NO buffers, you are good.
The design of chips have all shift registers stepping at same time.
But ( always a but ) your input signal times must be good.

If you add buffers in series you have to think about delays as shown in Inverters in series above.
Now what could you do?
With a big loop where you have buffer delays going out and the all the way back, you have a problem. The cure is easy if you use clock out to sample the input bits.
A SPI Master only has a send clock and not a send clock and receive clock.
A SPI Slave only has a receive clock.
If you had to have the big loop with buffers you could send with the SPI Master and receive with the SPI Slave.  The master generates the clock that the slave uses after delay. 

You are splitting the OUT from the IN. A simple step that removes OUT delay from picture. The timing at the SPI Master will be good, but you have to allow for the buffer delays working back.
Think of many transparencies stacked. The nice thing is that a slower clock rate removes the transparencies.
Think of a computer reading memory. Data needs to be at computer to read. A miss of 10ns gives computer garbage. Speeding up memory or slowing computer by 15ns  gives a 5ns safety margin and working computer.

Now to lan.M
In is posts to this thread in answering your questions and making suggestions are a LOT of important details.
I would suggest reading this thread many times and ask your self "why did he say that"

I really like this one
Quote
Then you get into stuff like switch wetting current.  As a rule of thumb, unless a switch or relay has sealed, mercury wetted or gold plated contacts, it will be unreliable unless you have enough voltage across it when open and pass enough current through it to break down any oxides or other slight contamination.  A rough rule of thumb is minimum 10V, 10mA.
Happened to me in the 70's, system used real high dollar low current switches that were suppose to last 100 thousand to 1 million switch cycles. Every thing known at time to make switch last longer.
In an effort to protect the switches, designer lowered the current to far to lower limit. New switches worked but got faulty 10,000 to 20,000 cycles later, One resistor of wrong value. Think it was 10 cent resistor vs $15 switch. If you are repair man, bad switch replace switch.
Try telling management  " if you harm switch more by switching higher current it will last longer".

Quote
If its coming from the layout, I suggest you use 12V signalling.  ON is >9V, OFF is <3V.  A potential divider 15K lower arm, 22K upper arm will do that nicely with no issues up to a maximum voltage of 13V.

A different way to do this is use RS232 chips like
MC1488N SN75188N MC1489N SN75189N
but you then need a negative supply

---------
Now think ahead a bit
so far you have standard SPI interface.
The Teensy 3.2, 3.5 & 3.6 all have a CAN Bus interface.
CAN Bus is a nice way to connect many CPU's together.
You could have many Teensy in system connected via CAN bus.
You could use one to control track and then add two more with each controlling one operator interface.
Now problem with this is high cost of Teensy
SPI & CAN Bus interface can be found on many chips.
Even the ESP32 has SPI & CAN Bus & Arduino

So what I am suggesting is not to get locked into idea that one has to do it all.
Easy to make many copies of a board.
Easy to make many copies of software.
Not hard to have many input or output chains of the boards here.
Not hard to leave off parts mounted to boards
Some times not hard to use different parts on a board to get a little different function.
 
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Offline C

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Re: Designing shift register circuit for SPI bus
« Reply #110 on: Today at 06:47:21 AM »
Quote
I am still considering bi-colour LED's which means my 60 outputs goes to 120 ! 16 TPIC6C595's would surely create fan out problems.

Might want to look at
First Look: APA102 RGB Pixel Addressable LED #1


Think of a color led string connected to SPI
Does not solve problem where you need small leds


 

Offline ilium007

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Re: Designing shift register circuit for SPI bus
« Reply #111 on: Today at 12:20:59 PM »
I am going to work through the reply's one by one and over some time as I am researching all the valuable points made by each contributor.

For the inputs, if you get it wrong you blow the shift register chip, and possibly other chips connected to it.   If you get it less wrong, EMI pickup gives you false input readings.

If its coming from the layout, I suggest you use 12V signalling.  ON is >9V, OFF is <3V.  A potential divider 15K lower arm, 22K upper arm will do that nicely with no issues up to a maximum voltage of 13V.   Above that, unless you clamp it the CMOS input protection diodes will start to pass current (undesirable) so you should also have a 5% 5.1V Zener, anode to ground  across the lower resistor, and a 1K resistor between the divider tap and the actual CMOS input.  With 1/4W resistors, that will survive up to +/- 70V with no issues and if you apply AC mains, as long as the ground connection is low impedance, there is a good chance that only the 22K resistor will blow.  For EMI filtering a 1nF to ground at the CMOS input pin is advisable.

Disclaimer: The schematics below are just showing a single  74HC165 input - I know they are incomplete

The inputs are quite simple, push button switches on a control panel (not sure what was meant by 'coming from the layout') and a few IR detection circuits running 5v logic. I had initially assumed I would just use a 5v logic to provide a LOW (10k pulldown to GND) and HIGH signals to the 74HC165's as below.



What is the benefit of 12v signalling vs 5v ?

What are we designing protection against ? Is it breakdown of a power supply that puts AC on the low voltage DC circuit ?

From the quote above I have drawn this partial schematic:



On to wetting current on relays. I am not sure if my approach to this track switching is going to work (I haven't prototyped it yet as I don't have relays). I am using an off the shelf Pololu MC33926 Motor Driver Carrier, https://www.pololu.com/product/1212, to drive the track PWM.



I will have three of these for three seperate tracks that can be driven at one time. There are a number of sections of track that need to have the PWM signal from one of these H-Bridge PWM motor drivers switched on or off. This is what I was going to use the relays for. I couldn't use an N-Channel / P-Channel MOSFET as the polarity changes on the PWM signal depending on direction selected by the user. I couldn't think of any other way to control the PWM signal to different sections of track.

A basic schematic of the relay switching:



I have thought about the use of pull-up / pulldown resistors for contact wetting but don't know how this will work given the polarity of the PWM signal changes based on motor direction selected.

Will a relay work for the PWM output from the motor driver to the tracks and if so should I just purchase gold plated relays. I only need 8 of them.

I should also mention that at present I am using a 12V 47A / 5v 7.0A HP server power supply in case that information is helpful for the AC protection discussion.
« Last Edit: Today at 01:36:28 PM by ilium007 »
 

Offline Ian.M

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Re: Designing shift register circuit for SPI bus
« Reply #112 on: Today at 01:01:41 PM »
First, for images less than the attachment size limits, its best to host them here as attachments.   Otherwise anyone who wants to download or view the full sized image without the forum resizing it to fit the page has to wrestle with the external image hoisting site. Also image hosting sites frequently change their usage T&Cs or delete old images, so externally hosted images frequently vanish a few months or years later, damaging the content of old topics, and making them far less useful. 

If you need to post an image inline to refer to it, attach it, post the post, then go back and edit the post IN A NEW TAB, so you can easily copy the link URLs of the non-expanded attachment thumbnails from the original tab, for inclusion in the IMG tags in your post.  I normally pre-insert broken image tags:
Code: [Select]
[img]/img]as placeholders so all I have to do is paste the URL between the ] and the / then hit [  and save the changes.  Please don't inline large filesize images as it chews through Dave's hosting bandwidth and the user's download bandwidth every time someone opens that page of the topic.  Them as wants to see them can simply click the attachment.

Partial schematics are fine.   When you draw the final one, for repeated stuff like inputs and relay circuits you can simply draw one channel in a block and indicate its repeated N times. The points each instance connects to should be named with a name that includes the instance number so you can see which connections 'belong' together.

Your first schematic is OK if the switches are on the same board as the CMOS chip and they have gold or carbon loaded elastomer contacts.   If they have silver or other metal contacts, decrease R6 to 1K t get at least a few mA wetting current.  If they are on a front panel, a 10K resistor between the board input (and the top end of R6) and the CMOS input fpr at least minimal protection against transients and over-voltage.  N.B. the extra 10K series resistor is *NOT* compatible with bipolar TTL inputs.

For the second circuit, if it isn't a Gold, mercury wetted or carbon loaded elastomer contact switch, you need that 1K resistor from the left end of R5 to ground to provide the wetting current.  I'd also recommend a 1nF cap from the bottom of R7 to ground for EMI filtering.  That gives you a low pass filter with a 3dB corner frequency of 16KHz which should be enough to keep radio signals out of your inputs.  If you are experiencing severe EMI issues, you could increase the capacitor to 10nF without any issues.   With those mods, its designed to protect against the high impulse voltages that are commonly found around your layout. e.g. if there is a loose  connection somewhere a simple points solenoid or train motor could easily put a short spike or inductive 'kick' of several hundred volts on the 12V supply the switch is connected to, and the normal operation of your layout could easily induce spikes of tens of volts amplitude in your switch wiring.

Now lets consider schematic three.   The relays are switching motor power, not low current control signals.  They do not need and should not have gold plated contacts as the plating wont stand up to high current arcing during opening or closing.  Solid Silver alloy contacts would probably be the most durable, though appropriately rated base metal contacts would come close.   As they are switching significant current and voltage, they don't need any resistors for extra wetting current though RC snubbers (which need to be calculated for the expected load current) or 20V bidirectional TVS diodes across each contact pair would probably be advisable to reduce arcing and prolong the relay contact life.

It's probably worth putting a rightangle header on the Polulu motor driver board and a mating rightangle connector at the edge of your MCU board so they can plug directly together to minimise wiring.  The driver output to the relays and the track wiring should use twisted pair of adequate gauge for the maximum current to minimise EMI so the motor PWM doesn't get into everything else.   I would suggest using socketed  relays mounted off-board - they'll be easier to wire and if one goes bad it will be cheap and easy to replace.   If you turn off the motor drive PWM before switching the relays you can get away with 5A ones.
« Last Edit: Today at 02:27:53 PM by Ian.M »
 

Offline ilium007

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Re: Designing shift register circuit for SPI bus
« Reply #113 on: Today at 01:05:15 PM »
OK thanks - I'll fix up the image links.

Looking at the other points made as well. I put all the relays on the big schematic I'm working on so that they all come across in the netlist in KiCAD PCB editor. I'm not sure what would happen if I were to only draw one of them.

Looking at the 74HC165 datasheet it says (I think) that max "High-level input voltage" VIH is 6.0v. The voltage divider on 12V would supply 7.135V wouldn't this exceed the 6.0V VIH of the 74HC165 ?



The pushbutton switches will connect to a front panel away from the input board. I think I will implement the voltage divider pending confirmation my 7.135V calculation is correct and that it will not damage the 74HC165 inputs:


« Last Edit: Today at 01:28:06 PM by ilium007 »
 

Offline Ian.M

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Re: Designing shift register circuit for SPI bus
« Reply #114 on: Today at 01:33:23 PM »
I'm not a Kicad user, but it looks like you need to use hierarchical sheets to hold the block that you want to repeat.  See http://uhaweb.hartford.edu/kmhill/suppnotes/KiCadDia/KiCadHierarchy01/KiCadHierarchy01.pdf.  If you get stuck with that you should probably start a new topic in the EEVblog EDA subforum.

The abs max input voltage may be 6V, but for CMOS, to avoid malfunctions,you should design to the range Gnd-0.3V to Vcc+0.3V.

However 22K upper, 15K lower divides the input voltage by (22+15)/15 = 2.47, so at 12V in it will only give the CMOS input 4.86V.  Any spikes exceeding +13V or below -0.7V will be handled by the 5.1V Zener keeping the CMOS input within its safe limits. (The -0.7V undershoot, and any rise above 5.7V due to large +ve spikes is permissible as the 1K resistor between the Zener and the input limits the internal input protection diode current to a small fraction of a mA.)

By interpolation, the minimum voltage VIH to guarantee a logic '1' @Vcc=5V is 3.5V.  Multiplying that by 2.47 gives 8.65V so unless you are dropping over 3V in your wiring it will read the input correctly.     
« Last Edit: Today at 01:43:40 PM by Ian.M »
 
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Offline ilium007

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Re: Designing shift register circuit for SPI bus
« Reply #115 on: Today at 01:34:25 PM »
The abs max input voltage may be 6V, but for CMOS, to avoid malfunctions,you should design to the range Gnd-0.3V to Vcc+0.3V.

However 22K upper, 15K lower divides the input voltage by (22+15)/15 = 2.47, so at 12V in it will only give the CMOS input 4.86V.  Any spikes exceeding +13V or below -0.7V will be handled by the 5.1V Zener keeping the CMOS input within its safe limits. (The -0.7V undershoot, and any rise above 5.7V due to large +ve spikes is permissible as the 1K resistor between the Zener and the input limits the internal input protection diode current to a small fraction of a mA.)

By interpolation, the minimum voltage VIH to guarantee a logic '1' @Vcc=5V is 3.5V.  Multiplying that by 2.47 gives 8.65V so unless you are dropping over 3V in your wiring it will read the input correctly.   

Ahh - I did my voltage divider calc incorrectly.
 

Offline ilium007

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Re: Designing shift register circuit for SPI bus
« Reply #116 on: Today at 01:40:12 PM »
The -0.7V undershoot, and any rise above 5.7V due to large +ve spikes is permissible as the 1K resistor between the Zener and the input limits the internal input protection diode current to a small fraction of a mA

I moved the 1k to the left of R5 to provide the wetting current, should I have had another 1k between the zener and the 74HC165 pin 11 input ?

« Last Edit: Today at 01:44:52 PM by ilium007 »
 

Offline Ian.M

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Re: Designing shift register circuit for SPI bus
« Reply #117 on: Today at 01:58:10 PM »
That's looking good apart from C8.  Connecting a cap between ground and ground is   |O *STUPID* - move it to between pin 11 of the IC and ground where its meant to be.

Also, as a matter of style, please move the SER data in pin to the center of the left edge of the 74HC165 symbol.  Then they will daisy-chain more clearly with the MCU board at the right hand end.   That means the SPI control signals are breaking convention and going right to left, but its preferable to having the data flow backwards.  Adding a note '<== SPI clock & control <==' immediately below the grouped control lines would then prevent confusion.

Its a pity the parallel input names don't include the bit number.  I suggest annotating the symbol at the two end inputs with 'b0' and 'b7'   SPI is transmitted MSB first, so get it the right way round!
 

Offline ilium007

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Re: Designing shift register circuit for SPI bus
« Reply #118 on: Today at 02:10:48 PM »
Thanks !! I did question myself when I put that cap there. *facepalm*.

I’ll fix up the component as suggested. All I need to do now is find some appropriate poly fuses and get them on the diagram.
 

Offline ilium007

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Re: Designing shift register circuit for SPI bus
« Reply #119 on: Today at 02:44:26 PM »
It may or may not be of interest but here is Dads train layout and some of the very detailed Queensland Rail locos I am building this for !



 

Offline C

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Re: Designing shift register circuit for SPI bus
« Reply #120 on: Today at 06:50:04 PM »

Motor driver control of track blocks
You have a computer so you could get real fancy if you can create correct code.

You could control inputs of motor controller using logic.
Using relays to control outputs

You can find some relay boards that have single pole double throw relays SPDT
Using these you could stop the train but un switched track side would still be swinging.

Using DPDT you can switch both sides of track.
one relay connected to track gives choice of A or B
Two relays choice of A or B or C
Three relays a choice of A or B or C or D
This last would give off or one of three motor controllers.

Now you could put a motor controller in place of Track in above example.

Think of a checker board
Horizontal rows are track blocks.
Vertical rows (columns) are motor controller
Using the relays you can increase the rows.
The checker on the board is a  full time connection.

Now think about input to motor controller
You can switch inputs using software or logic or both.
You could have a second checker board to select inputs to motor controller.

You could hide from operator that you changed what motor controller is controlling a
train.
Keep in mind that a relay takes time to change, so an A to B change becomes A, off, B with off being a short time.
To swap controllers hidden you would also need to match settings to controller. With logic this could be very fast.

Using solid state relays the off time between A & B gets real small and you can change often.

With a motor controller per block you have best control and probably highest cost when not having motor control in engine.

Now to make the puzzle even more fun or a larger pain you could have one track block connect to another track block with a relay.

Now if one engine by going down the track changes from one motor controller to another, the inputs to the two motor controllers should have outputs the same. A meter would read 0 volts across the gap in a track.

This might help some

 


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