I'm trying to figure out the way the BUS signals work on an old retro computer I am going to clone this project from. The schematic is from a fellow in Japan who designed it, but they don't have any more boards/pcbs so I am going to make my own. It is a 3-in-1 cartridge that plugs into the PC-6001A computer and it provides 16K extended RAM (originally DRAM but this project uses SRAM), 16K of ROM (switchable banks to have different "cartridges" loaded), and finally an 8255 interface to an AVR that emulates floppy drives. One thing he did not have in his design was a way to decide which image files to mount from the SDCARD into which drives. I plan on expanding to an atmega325 with more I/O pins so I can drive a tiny 4 digit 7 segment display and have a few buttons for input. With that I can select which drive to view/change and then use the +/- buttons to change the mounted image (obviously numeric only, but that will be fine for me).
Here are the control signals - am I understanding these correctly:
The parenthesis name is the signal name from computer documentation, not the schematic. Some of them are not listed properly in the documentation (NC!)
1 nRAS2 (RAS) (active low)
10 nEXCAS (MPX) (active low)
both go through an OR gate to the SRAM CS (active low), both must be active low to activate the SRAM
why 2 of these? are they a remnant from some sort of refreshing for DRAM? Does it make sense they should both be low to enable the SRAM IC?
3 nDRD2 (DBIN) (active low)
SRAM OE (active low)
5 nWE (WE) (active low)
Connected to SRAM WE (active low)
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2 nCS3 (ROM2 OE) (active low)
4 nCS2 (ROM1 OE) (active low)
either activate the flash via two nand gates to flash CE
nCS2 also connected to A13, so nCS2 means first 8K IC and nCS3 means the second 8K. This makes sense as cartridges for this computer had a pair of 8K IC's in a rom.
14 nRD (NC!) (active low) (***FLASH or 8255)
it feeds to the 8255 via an OR gate which can't go low unless the other gate input goes low as well
it feeds the flash OE directly (active low)
13 nWR (NC!) (active low)
it feeds to the 8255 via an OR gate which can't go low unless the other gate input goes low as well
11 nIORQ (NC!) (active low)
connects to the decoder nG2A (active low)
The decoder is setup so it will only output active low to the 8255 OR gate when D7-D4 are 0xD for ports 0xD0-0xDF
15 nRESET1 (NC!) (active low)
When it goes low, it pulls the AVR reset to ground which is normally pulled high with 10K.
When it goes low, it goes through an inverter which drives the 8255 reset high which clears it.
His schematic does not have this, but if I wanted to disable the 8255 and the floppy drive emulation can I modify the CS pin circuit. Right now it is grounded (always enabled). Can I pull it high with a 1K resistor and then use a DIP switch to switch it to ground? DIP on=grounded=enabled, DIP off=5V=disabled.
Any thoughts on the wierd signal names?