voltage divider making adc nonlinear

[wraper]

Also, add a hold on the reset: 1k to Vcc and a 0.1uF cap to ground.  Then the reset button sits across the cap and discharges it when pressed.  This gives you a hold on the order of 1ms and deglitch to boot, and a nice reset hold on power-on:

Very "smart suggestion" to put cap in parallel with button, inductive kickback is surely what should be implemented on reset pin.

[Seekonk]

Since this discussion was initially about a UNO, that reset capacitor should be increased to several uF.  A UNO will reset anytime the USB port is plugged in and stored data will be lost.  Reset is externally pulled down by .1uF connected to that pin.

[cc83]

Thanks everyone for the suggestions. I retested and reconfigured and even with my original circuit the result was accurate and linear from input to MCU pin. So I looked at the software. Couldn't find anything there. So I set up a program to log in values on the ADC and the result... It's a ADC linearity issue. So I did some error adjustment in software and it's working well now. I am going to redesign the input a little for v2. This project was for someone that had some strange requirements and they kept changing so the design was not optimal for the end result. I'm hoping that when I design a standalone board without the arduino and shield I won't have as much ADC error.