Author Topic: 8bit CPU made from 74HC logic.  (Read 16678 times)

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Offline PauloConstantino

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8bit CPU made from 74HC logic.
« on: June 09, 2017, 09:14:31 pm »





Instruction set:

MOV A, B       0x01
MOV A, IMM8      0x02
MOV A, [AD8]    0x03
MOV [AD8], A    0x04
MOV , A       0x05
MOV B, A       0x06
MOV B, IMM8    0x07
MOV B, [AD8]    0x08
MOV [AD8], B    0x09
MOV [A], B       0x0A
INC A       0x0B
INC B       0x0C
DEC A       0x0D
DEC B       0x0E
ADD A, B       0x0F
ADD A, IMM8    0x10
ADD B, A       0x11
ADD B, IMM8    0x12
ADC A, B       0x13
ADC A, IMM8    0x14
ADC B, A       0x15
ADC B, IMM8    0x16
SUB A, B       0x17
SUB A, IMM8    0x18
SUB B, A       0x19
SUB B, IMM8    0x1A
SBB A, B       0x1B
SBB A, IMM8    0x1C
SBB B, A       0x1D
SBB B, IMM8    0x1E
AND A, B       0x1F
AND A, IMM8    0x20
AND B, A       0x21
AND B, IMM8    0x22
OR A, B       0x23
OR A, IMM8       0x24
OR B, A       0x25
OR B, IMM8       0x26
XOR A, B       0x27
XOR A, IMM8    0x28
XOR B, A       0x29
XOR B, IMM8    0x2A
NOT A       0x2B
NOT B       0x2C
JMP AD8       0x2D
JMP [AD8]      0x2E
JZ AD8       0x2F
JC AD8       0x30
CMP A, B       0x31
CMP A, IMM8    0x32
CMP B, IMM8      0x33
PUSH A, STK8      0x34
POP A, STK8         0x35
CALL STK8, JMP8   0x36
NOP         0x37







Current Microcode:

*
  Microcode for all ROMS
  Least significant bits on the right
  Types of micro-instruction:         seq    = 00 (next is sequential)
                  branch = 01 (next depends on branch conditions)
                  pre-fetch = 10 (next is fetch)
                 post-fetch = 11 (next given by IR)

CarryInMux:   00 :   0      used for SUB
      01 :   1      used for ADD
      10 :  CF      used for SBB
      11 : ~CF      used for ADC


CONTROL BITS
   HIGH-------------------------------------------------------------------------------LOW

ROM1: ALU_Op2, ALU_Op1, ALU_Op0, WR, RD, branch_code, type1, type0
ROM2: PC_Wrt, CarryIn_Mux1, CarryIn_Mux0, CarryOut_Invert, ZF_Wrt, CF_Wrt, ALU_Mode, ALU_Op3
ROM3: MAR_Wrt, MDRIn_Mux, MDR_DB_Out, MDR_Y_Out, MDR_X_Out, MDR_Wrt, IR_Wrt, PC_Out
ROM4:   B_Out, B_Wrt, A_Out, A_Wrt, IMM_Out, IMM_Val, TDR_Out, TDR_Wrt

*

* FETCH *
*   ROM 1     ROM 2     ROM 3     ROM 4     *
0x00: 00000000, 00000000, 00000000, 00000000, * During this cycle, nothing is output onto the bus, in order no to create shorts.
                        Because the previous u-instructions might have been outputting data onto the buses and if PC outputs right after they might collide. *
   00100000, 00100001, 10000001, 00001000, * PC_Out, IMMVal=0, IMMOut, ALU=1001, ALUMode=0, CarryInMux=01, MAR_Wrt, type=seq(00) *
   00001000, 00000000, 00000010, 00000000, * RD, IR_Wrt, type=seq (00)*
   00100000, 10100001, 00000001, 00001100, * PC_Out, PC_Wrt, ALU=1001, ALUMode=0, CarryInMux=01, IMM_Out, IMMVal=1, type= +1(00)*
   00000011, 00000000, 00000000, 00000000; * Delay to avoid bus collision between PC and next instruction on X bus. post-fetch(11)*       

* MOV A, B *
0x01: 00100010, 00100001, 00000000, 10011000; * BOut, AWrt, IMMOut, IMM(0), ALUMode=0, ALUOp=1001, CarryInMux=01, type=pre-fetch(10) *

* MOV A, IMM8 *                                                                                                                 
0x02: 00100000, 00100001, 10000001, 00001000, * PC_Out, MAR_Wrt, IMM_Out, IMM(0), CarryInMux=01, ALUOp=1001, ALUMode=0, Next=00 *
   00001000, 00000000, 01000100, 00000000, * RD, MDRIn_Mux=1, MDR_Wrt, next=00 *
   00100000, 10100001, 00000001, 00001100, * PC+1: PC_Out, PC_Wrt, ALU=ADD,ALUMode=L, CarryInMux1=0, CarryInMux0=1, IMM_Out, IMMVal=1, next=00 *
   00000000, 00000000, 00000000, 00000000, * Delay to avoid bus collision between PC and MDR on X bus. *
   00100010, 00100001, 00001000, 00011000; * A_Wrt, MDR_X_Out, IMM_Out=1, IMM_Val=0, ALUOp=1001, ALUMode=0, CarryInMux=01, type=pre-fetch(10)*

* MOV A, [AD8] *
0x03: 00100000, 00100001, 10000001, 00001000, * PC_Out, MAR_Wrt, IMM_Out, IMM_Val=0, CarryInMux=01, ALUOp=1001, ALUMode=0, Next=00 *
   00001000, 00000000, 01000100, 00000000, * RD, MDRIn_Mux=1, MDR_Wrt, next=00 *
   00100000, 10100001, 00000001, 00001100, * PC+1: PC_Out, PC_Wrt, ALU=ADD,ALUMode=L, CarryInMux1=0, CarryInMux0=1, IMM_Out, IMMVal=1, next=00 *
   00000000, 00000000, 00000000, 00000000, * Delay to avoid bus collision between PC and MDR on X bus. *
   00100000, 00100001, 10001000, 00001000, * MAR_Wrt, MDR_X_Out, IMM_Out, IMM(0), ALUOp=1001, ALUMode=0, CarryInMux=01, next=00*
   00001000, 00000000, 01000100, 00000000, * RD, MDRIn_Mux=1, MDR_Wrt, next=00 *
   00100010, 00100001, 00001000, 00011000; * A_Wrt, MDR_X_Out, IMM_Out, IMM(0), ALUOp=1001, ALUMode=0, CarryInMux=01, type=pre-fetch(10) *

* MOV [AD8], A *
0x04: 00100000, 00100001, 10000001, 00001000, * PC_Out, MAR_Wrt, IMM_Out, IMM(0), CarryInMux1=0, CarryInMux0=1, ALUOp=1001, ALUMode=0, Next=00 *
   00001000, 00000000, 01000100, 00000000, * RD, MDRIn_Mux=1, MDR_Wrt, next=00 *
   00100000, 10100001, 00000001, 00001100, * PC+1: PC_Out, PC_Wrt, ALU=ADD, ALUMode=L, CarryInMux1=0, CarryInMux0=1, IMM_Out, IMMVal=1, next=00 *
   00000000, 00000000, 00000000, 00000000,
   00100000, 00100001, 10001000, 00001000, * MAR_Wrt, MDR_X_Out, IMM_Out, IMM_Val=0, ALUOp=1001, ALUMode=0, CarryInMux=01, type=00 *
   00000000, 00000000, 00000000, 00000000, * Delay to avoid bus collision between A and MDR on X bus. *
   00100000, 00100001, 00000100, 00101000, * A_Out, MDRIn_Mux=0, MDR_Wrt, IMM_Out, IMM_Val=0, ALUOp=1001, ALUMode=0, CarryInMux=01, type=00 *
   00000000, 00000000, 00100000, 00000000, * MDR_DB_Out, type=00(+1) * * open MDR to DB one cycle before WR goes low *
   00010000, 00000000, 00100000, 00000000, * WR, MDR_DB_Out, type=00(+1) * * WR goes low; MDR_DB still open *
   00000010, 00000000, 00100000, 00000000; * MDR_DB_Out, type=10(pre-fetch) * * WR goes inactive, but MDR_DB still needs to be open for data to stay stable. *   

* MOV A, [B + SIGNED8] - 2 BYTE INSTRUCTION *
0x05: 00100000, 00100001, 10000001, 00001000, * PC_Out, MAR_Wrt, IMM_Out, IMM(0), CarryInMux1=0, CarryInMux0=1, ALUOp=1001, ALUMode=0, Next=00 *
   00001000, 00000000, 01000100, 00000000, * RD, MDRIn_Mux=1, MDR_Wrt, next=00 *
   00100000, 10100001, 00000001, 00001100, * PC+1: PC_Out, PC_Wrt, ALU=ADD, ALUMode=L, CarryInMux1=0, CarryInMux0=1, IMM_Out, IMMVal=1, next=00 *
   00000000, 00000000, 00000000, 00000000,
   00100000, 00100001, 10010000, 10001000, * B_Out, MDR_Y_Out, MAR_Wrt, IMM_Out, IMM_Val=0, ALUOp=1001, ALUMode=0, CarryInMux=01, type=00 *
   00001000, 00000000, 01000100, 00000000, * RD, MDRIn_Mux=1, MDR_Wrt, next=00 *
   00100010, 00100001, 00001000, 00011000; * A_Wrt, MDR_X_Out, IMM_Out, IMM(0), ALUOp=1001, ALUMode=0, CarryInMux=01, type=pre-fetch(10) *   
   
   
* MOV [B + SIGNED8], A - 2 BYTE INSTRUCTION *
0x06: 00100000, 00100001, 10000001, 00001000, * PC_Out, MAR_Wrt, IMM_Out, IMM(0), CarryInMux1=0, CarryInMux0=1, ALUOp=1001, ALUMode=0, Next=00 *
   00001000, 00000000, 01000100, 00000000, * RD, MDRIn_Mux=1, MDR_Wrt, next=00 *
   00100000, 10100001, 00000001, 00001100, * PC+1: PC_Out, PC_Wrt, ALU=ADD, ALUMode=L, CarryInMux1=0, CarryInMux0=1, IMM_Out, IMMVal=1, next=00 *
   00000000, 00000000, 00000000, 00000000,
   00100000, 00100001, 10010000, 10001000, * B_Out, MDR_Y_Out, MAR_Wrt, IMM_Out, IMM_Val=0, ALUOp=1001, ALUMode=0, CarryInMux=01, type=00 *
   00000000, 00000000, 00000000, 00000000,
   00100000, 00100001, 00000100, 00101000, * A_Out, MDRIn_Mux=0, MDR_Wrt, IMM_Out, IMM_Val=0, ALUOp=1001, ALUMode=0, CarryInMux=01, type=00 *
   00000000, 00000000, 00100000, 00000000, * MDR_DB_Out, type=00(+1) * * open MDR to DB one cycle before WR goes low *
   00010000, 00000000, 00100000, 00000000, * WR, MDR_DB_Out, type=00(+1) * * WR goes low; MDR_DB still open *
   00000010, 00000000, 00100000, 00000000; * MDR_DB_Out, type=10(pre-fetch) * * WR goes inactive, but MDR_DB still needs to be open for data to stay stable. *



*

1    ALU_Op2, ALU_Op1, ALU_Op0, WR, RD, branch_code, type1, type0
2    PC_Wrt, CarryIn_Mux1, CarryIn_Mux0, CarryOut_Invert, ZF_Wrt, CF_Wrt, ALU_Mode, ALU_Op3
3    MAR_Wrt, MDRIn_Mux, MDR_DB_Out, MDR_Y_Out, MDR_X_Out, MDR_Wrt, IR_Wrt, PC_Out
4   B_Out, B_Wrt, A_Out, A_Wrt, IMM_Out, IMM_Val, TDR_Out, TDR_Wrt

*

* MOV B, A *
0x06: 00100010, 00100001, 00000000, 01101000; * AOut, BWrt, IMMOut, IMM(0), ALUMode=0, ALUOp=1001, CarryInMux1=0, CarryInMux0=1, type=pre-fetch(10) *

* MOV B, IMM8 *
0x07: 00100000, 00100001, 10000001, 00001000, * PC_Out, MAR_Wrt, IMM_Out, IMM(0), CarryInMux1=0, CarryInMux0=1, ALUOp=1001, ALUMode=0, Next=00 ** Send PC to MAR *         
   00001000, 00000000, 01000100, 00000000, * RD, MDRIn_Mux=1, MDR_Wrt, next=00 ** read byte from mem and write to mdr *            
   00100000, 10100001, 00000001, 00001100, * PC_Out, PC_Wrt, ALUOp=1001, ALUMode=0, CarryInMux=01, IMM_Out, IMMVal=1, next=00 ** increase PC by 1. *
   00000000, 00000000, 00000000, 00000000, * Delay to avoid bus collision between PC and MDR on X bus. *
   00100010, 00100001, 00001000, 01001000; * B_Wrt, MDR_X_Out, IMM_Out, IMM(0), ALUOp=1001, ALUMode=0, CarryInMux=01, type=pre-fetch(10)** save result to B: *
                        
* MOV B, [AD8] *
0x08: 00100000, 00100001, 10000001, 00001000, * PC_Out, MAR_Wrt, IMM_Out, IMM(0), CarryInMux1=0, CarryInMux0=1, ALUOp=1001, ALUMode=0, Next=00 *
   00001000, 00000000, 01000100, 00000000, * RD, MDRIn_Mux=1, MDR_Wrt, next=00 *
   00100000, 10100001, 00000001, 00001100, * PC+1: PC_Out, PC_Wrt, ALU=ADD,ALUMode=L, CarryInMux1=0, CarryInMux0=1, IMM_Out, IMMVal=1, next=00 *
   00000000, 00000000, 00000000, 00000000, * Delay to avoid bus collision between PC and MDR on X bus. *
   00100000, 00100001, 10001000, 00001000, * MAR_Wrt, MDR_X_Out, IMM_Out, IMM(0), ALUOp=1001, ALUMode=0, CarryInMux=01, next=00*
   00001000, 00000000, 01000100, 00000000, * RD, MDRIn_Mux=1, MDR_Wrt, next=00 *
   00100010, 00100001, 00001000, 01001000; * B_Wrt, MDR_X_Out, IMM_Out, IMM(0), ALUOp=1001, ALUMode=0, CarryInMux=01, type=pre-fetch(10) *

* MOV [AD8], B *
0x09: 00100000, 00100001, 10000001, 00001000, * PC_Out, MAR_Wrt, IMM_Out, IMM(0), CarryInMux1=0, CarryInMux0=1, ALUOp=1001, ALUMode=0, Next=00 *
   00001000, 00000000, 01000100, 00000000, * RD, MDRIn_Mux=1, MDR_Wrt, next=00 *
   00100000, 10100001, 00000001, 00001100, * PC+1: PC_Out, PC_Wrt, ALU=ADD,ALUMode=L, CarryInMux1=0, CarryInMux0=1, IMM_Out, IMMVal=1, next=00 *
   00000000, 00000000, 00000000, 00000000, * Delay to avoid bus collision between PC and MDR on X bus. *
   00100000, 00100001, 10001000, 00001000, * MAR_Wrt, MDR_X_Out, IMM_Out, IMM_Val=0, ALUOp=1001, ALUMode=0, CarryInMux=01, type=00 *
   00000000, 00000000, 00000000, 00000000, * Delay to avoid bus collision between B and MDR on X bus. *
   00100000, 00100001, 00000100, 10001000, * B_Out, MDRIn_Mux=0, MDR_Wrt, IMM_Out, IMM_Val=0, ALUOp=1001, ALUMode=0, CarryInMux=01, type=00 *
   00000000, 00000000, 00100000, 00000000, * MDR_DB_Out, type=00(+1) * * open MDR to DB one cycle before WR goes low *
   00010000, 00000000, 00100000, 00000000, * WR, MDR_DB_Out, type=00(+1) * * WR goes low; MDR_DB still open *
   00000010, 00000000, 00100000, 00000000; * MDR_DB_Out, type=10(pre-fetch) * * WR goes inactive, but MDR_DB still needs to be open for data to stay stable. *

*

1    ALU_Op2, ALU_Op1, ALU_Op0, WR, RD, branch_code, type1, type0
2    PC_Wrt, CarryIn_Mux1, CarryIn_Mux0, CarryOut_Invert, ZF_Wrt, CF_Wrt, ALU_Mode, ALU_Op3
3    MAR_Wrt, MDRIn_Mux, MDR_DB_Out, MDR_Y_Out, MDR_X_Out, MDR_Wrt, IR_Wrt, PC_Out
4   B_Out, B_Wrt, A_Out, A_Wrt, IMM_Out, IMM_Val, TDR_Out, TDR_Wrt

*

* INC A *
0x0B:   00100010, 00111101, 00000000, 00111100; * AOut, AWrt, IMM_Out, IMM_Val=1, ALUMode=0, ALUOp=1001, CarryInMux=01, CarryOutInvert=1, ZFWrt, CFWrt, type=pre-fetch(10) *

* INC B *
0x0C:   00100010, 00111101, 00000000, 11001100; * BOut, BWrt, IMM_Out, IMM_Val=1, ALUMode=0, ALUOp=1001, CarryInMux=01, CarryOutInvert=1, ZFWrt, CFWrt, type=pre-fetch(10) *

* DEC A *
0x0D:   11000010, 00001100, 00000000, 00111100; * AOut, AWrt, IMM_Out, IMM_Val=1, ALUMode=0, ALUOp=0110, CarryInMux=00, CarryOutInvert=0, ZFWrt, CFWrt, type=pre-fetch(10) *

* DEC B *
0x0E:   11000010, 00001100, 00000000, 11001100; * BOut, BWrt, IMM_Out, IMM_Val=1, ALUMode=0, ALUOp=0110, CarryInMux=00, CarryOutInvert=0, ZFWrt, CFWrt, type=pre-fetch(10) *


* ADD A, B *
0x0F: 00100000, 00100001, 00000000, 10001001, * BOut, IMMOut, IMM(0), ALUMode=0, ALUOp=1001, CarryInMux1=0, CarryInMux0=1, TDRWrt, next=00 *
   00000000, 00000000, 00000000, 00000000, * Delay to avoid bus collision between A and B on X bus. *
   00100010, 00111101, 00000000, 00110010; * AOut, AWrt, TDROut, ALUMode=0, ALUOp=1001, CarryInMux1=0, CarryInMux0=1, CarryOutInvert=1, ZFWrt, CFWrt, type=pre-fetch(10) *

* ADD A, IMM8 *
0x10: 00100000, 00100001, 10000001, 00001000, * PC_Out, MAR_Wrt, IMM_Out, IMM(0), CarryInMux1=0, CarryInMux0=1, ALUOp=1001, ALUMode=0, Next=00 *
   00001000, 00000000, 01000100, 00000000, * RD, MDRIn_Mux=1, MDR_Wrt, next=00 *
   00100000, 10100001, 00000001, 00001100, * PC+1: PC_Out, PC_Wrt, ALU=ADD,ALUMode=L, CarryInMux1=0, CarryInMux0=1, IMM_Out, IMMVal=1, next=00 *
   00000000, 00000000, 00000000, 00000000, * Delay to avoid bus collision between PC and A on X bus. *
   00100010, 00111101, 00010000, 00110000; * A_Out, A_Wrt, MDR_Y_Out, ALUOp=1001, ALUMode=0, CarryInMux=01, CarryOutInvert=1, ZF_Wrt, CF_Wrt, type=pre-fetch(10)*

* ADD B, A *
0x11: 00100000, 00100001, 00000000, 00101001, * AOut, TDRWrt, IMMOut, IMM(0), ALUMode=0, ALUOp=1001, CarryInMux1=0, CarryInMux0=1, next=00 *
   00000000, 00000000, 00000000, 00000000, * Delay to avoid bus collision between A and B on X bus. *
   00100010, 00111101, 00000000, 11000010; * BOut, BWrt, TDROut, ALUMode=0, ALUOp=1001, CarryInMux1=0, CarryInMux0=1, CarryOutInvert=1, ZFWrt, CFWrt, type=pre-fetch(10) *

* ADD B, IMM8 *
0x12: 00100000, 00100001, 10000001, 00001000, * PC_Out, MAR_Wrt, IMM_Out, IMM(0), CarryInMux1=0, CarryInMux0=1, ALUOp=1001, ALUMode=0, Next=00 *
   00001000, 00000000, 01000100, 00000000, * RD, MDRIn_Mux=1, MDR_Wrt, next=00 *
   00100000, 10100001, 00000001, 00001100, * PC+1: PC_Out, PC_Wrt, ALU=ADD,ALUMode=L, CarryInMux1=0, CarryInMux0=1, IMM_Out, IMMVal=1, next=00 *
   00000000, 00000000, 00000000, 00000000, * Delay to avoid bus collision between PC and B on X bus. *
   00100010, 00111101, 00010000, 11000000; * B_Out, B_Wrt, MDR_Y_Out, ALUOp=1001, ALUMode=0, CarryInMux=01, CarryOutInvert=1, ZF_Wrt, CF_Wrt, type=pre-fetch(10)*



* ADC A, B *
0x13: 00100000, 00100001, 00000000, 10001001, * BOut, IMMOut, IMM(0), ALUMode=0, ALUOp=1001, CarryInMux1=0, CarryInMux0=1, TDRWrt, next=00 *
   00000000, 00000000, 00000000, 00000000, * Delay to avoid bus collision between A and B on X bus. *
   00100010, 01111101, 00000000, 00110010; * AOut, AWrt, TDROut, ALUMode=0, ALUOp=1001, CarryInMux=11, CarryOutInvert=1, ZFWrt, CFWrt, type=pre-fetch(10) *

* ADC A, IMM8 *
0x14: 00100000, 00100001, 10000001, 00001000, * PC_Out, MAR_Wrt, IMM_Out, IMM(0), CarryInMux1=0, CarryInMux0=1, ALUOp=1001, ALUMode=0, Next=00 *
   00001000, 00000000, 01000100, 00000000, * RD, MDRIn_Mux=1, MDR_Wrt, next=00 *
   00100000, 10100001, 00000001, 00001100, * PC+1: PC_Out, PC_Wrt, ALU=ADD,ALUMode=L, CarryInMux1=0, CarryInMux0=1, IMM_Out, IMMVal=1, next=00 *
   00000000, 00000000, 00000000, 00000000, * Delay to avoid bus collision between PC and A on X bus. *
   00100010, 01111101, 00010000, 00110000; * A_Out, A_Wrt, MDR_Y_Out, ALUOp=1001, ALUMode=0, CarryInMux=11, CarryOutInvert=1, ZF_Wrt, CF_Wrt, type=pre-fetch(10)*

* ADC B, A *
0x15: 00100000, 00100001, 00000000, 00101001, * AOut, TDRWrt, IMMOut, IMM(0), ALUMode=0, ALUOp=1001, CarryInMux1=0, CarryInMux0=1, next=00 *
   00000000, 00000000, 00000000, 00000000, * Delay to avoid bus collision between A and B on X bus. *
   00100010, 01111101, 00000000, 11000010; * BOut, BWrt, TDROut, ALUMode=0, ALUOp=1001, CarryInMux=11, CarryOutInvert=1, ZFWrt, CFWrt, type=pre-fetch(10) *

* ADC B, IMM8 *
0x16: 00100000, 00100001, 10000001, 00001000, * PC_Out, MAR_Wrt, IMM_Out, IMM(0), CarryInMux1=0, CarryInMux0=1, ALUOp=1001, ALUMode=0, Next=00 *
   00001000, 00000000, 01000100, 00000000, * RD, MDRIn_Mux=1, MDR_Wrt, next=00 *
   00100000, 10100001, 00000001, 00001100, * PC+1: PC_Out, PC_Wrt, ALU=ADD,ALUMode=L, CarryInMux1=0, CarryInMux0=1, IMM_Out, IMMVal=1, next=00 *
   00000000, 00000000, 00000000, 00000000, * Delay to avoid bus collision between PC and B on X bus. *
   00100010, 01111101, 00010000, 11000000; * B_Out, B_Wrt, MDR_Y_Out, ALUOp=1001, ALUMode=0, CarryInMux=11, CarryOutInvert=1, ZF_Wrt, CF_Wrt, type=pre-fetch(10)*



* SUB A, B *
0x17: 00100000, 00100001, 00000000, 10001001, * BOut, IMMOut, IMM(0), ALUMode=0, ALUOp=1001, CarryInMux1=0, CarryInMux0=1, TDRWrt, next=00 *
   00000000, 00000000, 00000000, 00000000, * Delay to avoid bus collision between A and B on X bus. *
   11000010, 00001100, 00000000, 00110010; * AOut, AWrt, TDROut, ALUMode=0, ALUOp=0110, CarryInMux1=0, CarryInMux0=0, CarryOutInvert=0, ZFWrt, CFWrt, type=pre-fetch(10) *

* SUB A, IMM8 *
0x18: 00100000, 00100001, 10000001, 00001000, * PC_Out, MAR_Wrt, IMM_Out, IMM(0), CarryInMux1=0, CarryInMux0=1, ALUOp=1001, ALUMode=0, Next=00 *
   00001000, 00000000, 01000100, 00000000, * RD, MDRIn_Mux=1, MDR_Wrt, next=00 *
   00100000, 10100001, 00000001, 00001100, * PC+1: PC_Out, PC_Wrt, ALU=ADD,ALUMode=L, CarryInMux1=0, CarryInMux0=1, IMM_Out, IMMVal=1, next=00 *
   00000000, 00000000, 00000000, 00000000, * Delay to avoid bus collision between PC and A on X bus. *
   11000010, 00001100, 00010000, 00110000; * A_Out, A_Wrt, MDR_Y_Out, ALUOp=0110, ALUMode=0, CarryInMux=00, CarryOutInvert=0, ZF_Wrt, CF_Wrt, type=pre-fetch(10)*

* SUB B, A *
0x19: 00100000, 00100001, 00000000, 00001001, * AOut, IMMOut, IMM(0), ALUMode=0, ALUOp=1001, CarryInMux1=0, CarryInMux0=1, TDRWrt, next=00 *
   00000000, 00000000, 00000000, 00000000, * Delay to avoid bus collision between A and B on X bus. *
   11000010, 00001100, 00000000, 11000010; * BOut, BWrt, TDROut, ALUMode=0, ALUOp=0110, CarryInMux1=0, CarryInMux0=0, CarryOutInvert=0, ZFWrt, CFWrt, type=pre-fetch(10) *

* SUB B, IMM8 *
0x1A: 00100000, 00100001, 10000001, 00001000, * PC_Out, MAR_Wrt, IMM_Out, IMM(0), CarryInMux1=0, CarryInMux0=1, ALUOp=1001, ALUMode=0, Next=00 *
   00001000, 00000000, 01000100, 00000000, * RD, MDRIn_Mux=1, MDR_Wrt, next=00 *
   00100000, 10100001, 00000001, 00001100, * PC+1: PC_Out, PC_Wrt, ALUOp=1001, ALUMode=0, CarryInMux1=0, CarryInMux0=1, IMM_Out, IMMVal=1, next=00 *
   00000000, 00000000, 00000000, 00000000, * Delay to avoid bus collision between PC and B on X bus. *
   11000010, 00001100, 00010000, 11000000; * B_Out, B_Wrt, MDR_Y_Out, ALUOp=0110, ALUMode=0, CarryInMux=00, CarryOutInvert=0, ZF_Wrt, CF_Wrt, type=pre-fetch(10)*



* SBB A, B *
0x1B: 00100000, 00100001, 00000000, 10001001, * BOut, IMMOut, IMM(0), ALUMode=0, ALUOp=1001, CarryInMux1=0, CarryInMux0=1, TDRWrt, next=00 *
   00000000, 00000000, 00000000, 00000000, * Delay to avoid bus collision between A and B on X bus. *
   11000010, 01001100, 00000000, 00110010; * AOut, AWrt, TDROut, ALUMode=0, ALUOp=0110, CarryInMux=10, CarryOutInvert=0, ZFWrt, CFWrt, type=pre-fetch(10) *

* SBB A, IMM8 *
0x1C: 00100000, 00100001, 10000001, 00001000, * PC_Out, MAR_Wrt, IMM_Out, IMM(0), CarryInMux1=0, CarryInMux0=1, ALUOp=1001, ALUMode=0, Next=00 *
   00001000, 00000000, 01000100, 00000000, * RD, MDRIn_Mux=1, MDR_Wrt, next=00 *
   00100000, 10100001, 00000001, 00001100, * PC+1: PC_Out, PC_Wrt, ALU=ADD,ALUMode=L, CarryInMux1=0, CarryInMux0=1, IMM_Out, IMMVal=1, next=00 *
   00000000, 00000000, 00000000, 00000000, * Delay to avoid bus collision between PC and A on X bus. *
   11000010, 01001100, 00010000, 00110000; * A_Out, A_Wrt, MDR_Y_Out, ALUOp=0110, ALUMode=0, CarryInMux=10, CarryOutInvert=0, ZF_Wrt, CF_Wrt, type=pre-fetch(10)*

* SBB B, A *
0x1D: 00100000, 00100001, 00000000, 00001001, * AOut, IMMOut, IMM(0), ALUMode=0, ALUOp=1001, CarryInMux1=0, CarryInMux0=1, TDRWrt, next=00 *
   00000000, 00000000, 00000000, 00000000, * Delay to avoid bus collision between A and B on X bus. *
   11000010, 01001100, 00000000, 11000010; * BOut, BWrt, TDROut, ALUMode=0, ALUOp=0110, CarryInMux=10, CarryOutInvert=0, ZFWrt, CFWrt, type=pre-fetch(10) *

* SBB B, IMM8 *
0x1E: 00100000, 00100001, 10000001, 00001000, * PC_Out, MAR_Wrt, IMM_Out, IMM(0), CarryInMux1=0, CarryInMux0=1, ALUOp=1001, ALUMode=0, Next=00 *
   00001000, 00000000, 01000100, 00000000, * RD, MDRIn_Mux=1, MDR_Wrt, next=00 *
   00100000, 10100001, 00000001, 00001100, * PC+1: PC_Out, PC_Wrt, ALUOp=1001, ALUMode=0, CarryInMux1=0, CarryInMux0=1, IMM_Out, IMMVal=1, next=00 *
   00000000, 00000000, 00000000, 00000000, * Delay to avoid bus collision between PC and B on X bus. *
   11000010, 01001100, 00010000, 11000000; * B_Out, B_Wrt, MDR_Y_Out, ALUOp=0110, ALUMode=0, CarryInMux=10, CarryOutInvert=0, ZF_Wrt, CF_Wrt, type=pre-fetch(10)*

*
1    ALU_Op2, ALU_Op1, ALU_Op0, WR, RD, branch_code, type1, type0
2    PC_Wrt, CarryIn_Mux1, CarryIn_Mux0, CarryOut_Invert, ZF_Wrt, CF_Wrt, ALU_Mode, ALU_Op3
3    MAR_Wrt, MDRIn_Mux, MDR_DB_Out, MDR_Y_Out, MDR_X_Out, MDR_Wrt, IR_Wrt, PC_Out
4   B_Out, B_Wrt, A_Out, A_Wrt, IMM_Out, IMM_Val, TDR_Out, TDR_Wrt
*

* AND A, B *
0x1F: 00100000, 00100001, 00000000, 10001001, * BOut, IMMOut, IMM(0), ALUMode=0, ALUOp=1001, CarryInMux1=0, CarryInMux0=1, TDRWrt, next=00 *
   00000000, 00000000, 00000000, 00000000, * Delay to avoid bus collision between A and B on X bus. *
   01100010, 00001011, 00000000, 00110010; * AOut, AWrt, TDROut, ALUMode=1, ALUOp=1011, ZFWrt, type=pre-fetch(10) *

* AND A, IMM8 *
0x20: 00100000, 00100001, 10000001, 00001000, * PC_Out, MAR_Wrt, IMM_Out, IMM(0), CarryInMux1=0, CarryInMux0=1, ALUOp=1001, ALUMode=0, Next=00 *
   00001000, 00000000, 01000100, 00000000, * RD, MDRIn_Mux=1, MDR_Wrt, next=00 *
   00100000, 10100001, 00000001, 00001100, * PC+1: PC_Out, PC_Wrt, ALU=ADD,ALUMode=L, CarryInMux1=0, CarryInMux0=1, IMM_Out, IMMVal=1, next=00 *
   00000000, 00000000, 00000000, 00000000, * Delay to avoid bus collision between PC and A on X bus. *
   01100010, 00001011, 00010000, 00110000; * A_Out, A_Wrt, MDR_Y_Out, ALUOp=1011, ALUMode=1, ZF_Wrt, type=pre-fetch(10)*

* AND B, A *
0x21: 00100000, 00100001, 00000000, 10001001, * A_Out, IMMOut, IMM(0), ALUMode=0, ALUOp=1001, CarryInMux1=0, CarryInMux0=1, TDRWrt, next=00 *
   00000000, 00000000, 00000000, 00000000, * Delay to avoid bus collision between A and B on X bus. *
   01100010, 00001011, 00000000, 11000010; * B_Out, BWrt, TDROut, ALUMode=1, ALUOp=1011, ZFWrt, type=pre-fetch(10) *

* AND B, IMM8 *
0x22: 00100000, 00100001, 10000001, 00001000, * PC_Out, MAR_Wrt, IMM_Out, IMM(0), CarryInMux1=0, CarryInMux0=1, ALUOp=1001, ALUMode=0, Next=00 *
   00001000, 00000000, 01000100, 00000000, * RD, MDRIn_Mux=1, MDR_Wrt, next=00 *
   00100000, 10100001, 00000001, 00001100, * PC+1: PC_Out, PC_Wrt, ALUOp=1001, ALUMode=0, CarryInMux=01, IMM_Out, IMMVal=1, next=00 *
   00000000, 00000000, 00000000, 00000000, * Delay to avoid bus collision between PC and B on X bus. *
   01100010, 00001011, 00010000, 11000000; * B_Out, B_Wrt, MDR_Y_Out, ALUOp=1011, ALUMode=1, ZF_Wrt, type=pre-fetch(10)*

* OR A, B *
0x23: 00100000, 00100001, 00000000, 10001001, * BOut, IMMOut, IMM(0), ALUMode=0, ALUOp=1001, CarryInMux1=0, CarryInMux0=1, TDRWrt, next=00 *
   00000000, 00000000, 00000000, 00000000, * Delay to avoid bus collision between A and B on X bus. *
   11000010, 00001011, 00000000, 00110010; * AOut, AWrt, TDROut, ALUMode=1, ALUOp=1110, ZFWrt, type=pre-fetch(10) *

* OR A, IMM8 *
0x24: 00100000, 00100001, 10000001, 00001000, * PC_Out, MAR_Wrt, IMM_Out, IMM(0), CarryInMux1=0, CarryInMux0=1, ALUOp=1001, ALUMode=0, Next=00 *
   00001000, 00000000, 01000100, 00000000, * RD, MDRIn_Mux=1, MDR_Wrt, next=00 *
   00100000, 10100001, 00000001, 00001100, * PC+1: PC_Out, PC_Wrt, ALU=ADD,ALUMode=L, CarryInMux1=0, CarryInMux0=1, IMM_Out, IMMVal=1, next=00 *
   00000000, 00000000, 00000000, 00000000, * Delay to avoid bus collision between PC and A on X bus. *
   11000010, 00001011, 00010000, 00110000; * A_Out, A_Wrt, MDR_Y_Out, ALUOp=1110, ALUMode=1, ZF_Wrt, type=pre-fetch(10)*

* OR B, A *
0x25: 00100000, 00100001, 00000000, 10001001, * AOut, IMMOut, IMM(0), ALUMode=0, ALUOp=1001, CarryInMux1=0, CarryInMux0=1, TDRWrt, next=00 *
   00000000, 00000000, 00000000, 00000000, * Delay to avoid bus collision between A and B on X bus. *
   11000010, 00001011, 00000000, 11000010; * BOut, BWrt, TDROut, ALUMode=1, ALUOp=1110, ZFWrt, type=pre-fetch(10) *

* OR B, IMM8 *
0x26: 00100000, 00100001, 10000001, 00001000, * PC_Out, MAR_Wrt, IMM_Out, IMM(0), CarryInMux1=0, CarryInMux0=1, ALUOp=1001, ALUMode=0, Next=00 *
   00001000, 00000000, 01000100, 00000000, * RD, MDRIn_Mux=1, MDR_Wrt, next=00 *
   00100000, 10100001, 00000001, 00001100, * PC+1: PC_Out, PC_Wrt, ALUOp=1001, ALUMode=0, CarryInMux=01, IMM_Out, IMMVal=1, next=00 *
   00000000, 00000000, 00000000, 00000000, * Delay to avoid bus collision between PC and B on X bus. *
   11000010, 00001011, 00010000, 11000000; * B_Out, B_Wrt, MDR_Y_Out, ALUOp=1110, ALUMode=1, ZF_Wrt, type=pre-fetch(10)*


* XOR A, B *
0x27: 00100000, 00100001, 00000000, 10001001, * BOut, IMMOut, IMM(0), ALUMode=0, ALUOp=1001, CarryInMux1=0, CarryInMux0=1, TDRWrt, next=00 *
   00000000, 00000000, 00000000, 00000000, * Delay to avoid bus collision between A and B on X bus. *
   11000010, 00001010, 00000000, 00110010; * AOut, AWrt, TDROut, ALUMode=1, ALUOp=0110, ZFWrt, type=pre-fetch(10) *

* XOR A, IMM8 *
0x28: 00100000, 00100001, 10000001, 00001000, * PC_Out, MAR_Wrt, IMM_Out, IMM(0), CarryInMux1=0, CarryInMux0=1, ALUOp=1001, ALUMode=0, Next=00 *
   00001000, 00000000, 01000100, 00000000, * RD, MDRIn_Mux=1, MDR_Wrt, next=00 *
   00100000, 10100001, 00000001, 00001100, * PC+1: PC_Out, PC_Wrt, ALU=ADD,ALUMode=L, CarryInMux1=0, CarryInMux0=1, IMM_Out, IMMVal=1, next=00 *
   00000000, 00000000, 00000000, 00000000, * Delay to avoid bus collision between PC and A on X bus. *
   11000010, 00001010, 00010000, 00110000; * A_Out, A_Wrt, MDR_Y_Out, ALUOp=0110, ALUMode=1, ZF_Wrt, type=pre-fetch(10)*

* XOR B, A *
0x29: 00100000, 00100001, 00000000, 10001001, * AOut, IMMOut, IMM(0), ALUMode=0, ALUOp=1001, CarryInMux1=0, CarryInMux0=1, TDRWrt, next=00 *
   00000000, 00000000, 00000000, 00000000, * Delay to avoid bus collision between A and B on X bus. *
   11000010, 00001010, 00000000, 11000010; * BOut, BWrt, TDROut, ALUMode=1, ALUOp=0110, ZFWrt, type=pre-fetch(10) *

* XOR B, IMM8 *
0x2A: 00100000, 00100001, 10000001, 00001000, * PC_Out, MAR_Wrt, IMM_Out, IMM(0), CarryInMux1=0, CarryInMux0=1, ALUOp=1001, ALUMode=0, Next=00 *
   00001000, 00000000, 01000100, 00000000, * RD, MDRIn_Mux=1, MDR_Wrt, next=00 *
   00100000, 10100001, 00000001, 00001100, * PC+1: PC_Out, PC_Wrt, ALUOp=1001, ALUMode=0, CarryInMux=01, IMM_Out, IMMVal=1, next=00 *
   00000000, 00000000, 00000000, 00000000, * Delay to avoid bus collision between PC and B on X bus. *
   11000010, 00001010, 00010000, 11000000; * B_Out, B_Wrt, MDR_Y_Out, ALUOp=0110, ALUMode=1, ZF_Wrt, type=pre-fetch(10)*



*
1    ALU_Op2, ALU_Op1, ALU_Op0, WR, RD, branch_code, type1, type0
2    PC_Wrt, CarryIn_Mux1, CarryIn_Mux0, CarryOut_Invert, ZF_Wrt, CF_Wrt, ALU_Mode, ALU_Op3
3    MAR_Wrt, MDRIn_Mux, MDR_DB_Out, MDR_Y_Out, MDR_X_Out, MDR_Wrt, IR_Wrt, PC_Out
4   B_Out, B_Wrt, A_Out, A_Wrt, IMM_Out, IMM_Val, TDR_Out, TDR_Wrt
*

* NOT A *
0x2B: 00000010, 00001010, 00000000, 00111000; * AOut, AWrt, IMMOut, IMM(0), ALUMode=1, ALUOp=0000, ZFWrt, type=pre-fetch(10) *
   

* NOT B *
0x2C: 00000010, 00001010, 00000000, 11001000; * BOut, BWrt, IMMOut, IMM(0), ALUMode=1, ALUOp=0000, ZFWrt, type=pre-fetch(10) *
   

* JMP AD8 *
0x2D: 00100000, 00100001, 10000001, 00001000, * PC_Out, MAR_Wrt, IMM_Out, IMM(0), CarryInMux1=0, CarryInMux0=1, ALUOp=1001, ALUMode=0, Next=00 *
   00001000, 00000000, 01000100, 00000000, * RD, MDRIn_Mux=1, MDR_Wrt, next=00 *
   00100010, 10100001, 00001000, 00001000; * MDR_X_Out, PC_Wrt, IMM_Out, IMM(0), ALUOp=1001, ALUMode=0, CarryInMux1=0, CarryInMux0=1, type=10(pre_fetch) *

* JZ AD8 *
0x2E: 00100000, 00100001, 10000001, 00001000, * PC_Out, MAR_Wrt, IMM_Out, IMM(0), CarryInMux1=0, CarryInMux0=1, ALUOp=1001, ALUMode=0, Next=00 *
   00001000, 00000000, 01000100, 00000000, * RD, MDRIn_Mux=1, MDR_Wrt, next=00 *
   00100000, 10100001, 00000001, 00001100, * PC+1: PC_Out, PC_Wrt, ALU=ADD,ALUMode=L, CarryInMux1=0, CarryInMux0=1, IMM_Out, IMMVal=1, next=00 *
   00000001, 00000000, 00000000, 00000000, * branch point. if ZF = 1 then execute next u. else jump to fetch. branch_code=0(ZF), type=branch(01)*
   00100010, 10100001, 00001000, 00001000; * MDR_X_Out, PC_Wrt, IMM_Out, IMM(0), ALUOp=1001, ALUMode=0, CarryInMux1=0, CarryInMux0=1, type=10(pre_fetch) *

* JC AD8 *
0x2F: 00100000, 00100001, 10000001, 00001000, * PC_Out, MAR_Wrt, IMM_Out, IMM(0), CarryInMux1=0, CarryInMux0=1, ALUOp=1001, ALUMode=0, Next=00 *
   00001000, 00000000, 01000100, 00000000, * RD, MDRIn_Mux=1, MDR_Wrt, next=00 *
   00100000, 10100001, 00000001, 00001100, * PC+1: PC_Out, PC_Wrt, ALU=ADD,ALUMode=L, CarryInMux1=0, CarryInMux0=1, IMM_Out, IMMVal=1, next=00 *
   00000101, 00000000, 00000000, 00000000, * branch point. if CF = 1 then execute next u. else jump to fetch. branch_code=1(CF), type=branch(01) *
   00100010, 10100001, 00001000, 00001000; * MDR_X_Out, PC_Wrt, IMM_Out, IMM(0), ALUOp=1001, ALUMode=0, CarryInMux1=0, CarryInMux0=1, type=10(pre_fetch)*

* CMP A, B *
0x30: 00100000, 00100001, 00000000, 10001001, * BOut, TDRWrt, IMMOut, IMM(0), ALUMode=0, ALUOp=1001, CarryInMux1=0, CarryInMux0=1, next=00 *
   00000000, 00000000, 00000000, 00000000, * Delay to avoid bus collision between A and B on X bus. *
   11000010, 00001100, 00000000, 00100010; * AOut, TDROut, ALUMode=0, ALUOp=0110, CarryInMux=00, CarryOutInvert=0, ZFWrt, CFWrt, type=pre-fetch(10) *

* CMP A, IMM8 *
0x31: 00100000, 00100001, 10000001, 00001000, * PC_Out, MAR_Wrt, IMM_Out, IMM(0), CarryInMux1=0, CarryInMux0=1, ALUOp=1001, ALUMode=0, Next=00 *
   00001000, 00000000, 01000100, 00000000, * RD, MDRIn_Mux=1, MDR_Wrt, next=00 *
   00100000, 10100001, 00000001, 00001100, * PC+1: PC_Out, PC_Wrt, ALU=ADD,ALUMode=L, CarryInMux1=0, CarryInMux0=1, IMM_Out, IMMVal=1, next=00 *
   00000000, 00000000, 00000000, 00000000, * Delay to avoid bus collision between PC and A on X bus. *
   11000010, 00001100, 00010000, 00100000; * A_Out, MDR_Y_Out, ALUOp=0110, ALUMode=0, CarryInMux=00, CarryOutInvert=0, ZF_Wrt, CF_Wrt, type=pre-fetch(10)*

* CMP B, IMM8*
0x32: 00100000, 00100001, 10000001, 00001000, * PC_Out, MAR_Wrt, IMM_Out, IMM(0), CarryInMux1=0, CarryInMux0=1, ALUOp=1001, ALUMode=0, Next=00 *
   00001000, 00000000, 01000100, 00000000, * RD, MDRIn_Mux=1, MDR_Wrt, next=00 *
   00100000, 10100001, 00000001, 00001100, * PC+1: PC_Out, PC_Wrt, ALU=ADD,ALUMode=L, CarryInMux1=0, CarryInMux0=1, IMM_Out, IMMVal=1, next=00 *
   00000000, 00000000, 00000000, 00000000, * Delay to avoid bus collision between PC and B on X bus. *
   11000010, 00001100, 00010000, 10000000; * B_Out, MDR_Y_Out, ALUOp=0110, ALUMode=0, CarryInMux=00, CarryOutInvert=0, ZF_Wrt, CF_Wrt, type=pre-fetch(10)*

*
1    ALU_Op2, ALU_Op1, ALU_Op0, WR, RD, branch_code, type1, type0
2    PC_Wrt, CarryIn_Mux1, CarryIn_Mux0, CarryOut_Invert, ZF_Wrt, CF_Wrt, ALU_Mode, ALU_Op3
3    MAR_Wrt, MDRIn_Mux, MDR_DB_Out, MDR_Y_Out, MDR_X_Out, MDR_Wrt, IR_Wrt, PC_Out
4   B_Out, B_Wrt, A_Out, A_Wrt, IMM_Out, IMM_Val, TDR_Out, TDR_Wrt
*

* CALL &SP8, JMP8  saves PC to [SP] and jumps to JMP8 *
0x33: 00100000, 00100001, 10000001, 00001000, * PC_Out, MAR_Wrt, IMM_Out, IMM_Val=0, ALUOp=1001, ALUMode=0, CarryInMux=01, Next=00 *
   00001000, 00000000, 01000100, 00000000, * MDR_Wrt, RD, MDRIn_Mux=1(DB), next=00 *
   00100000, 10100001, 00000001, 00001100, * PC+1: PC_Out, PC_Wrt, ALU_Op=1001, ALUMode=0, CarryInMux=01, IMM_Out, IMMVal=1, next=00 *
   00100000, 10100001, 00000001, 00001100, * PC+1: PC_Out, PC_Wrt, ALU_Op=1001, ALUMode=0, CarryInMux=01, IMM_Out, IMMVal=1, next=00 *
   00000000, 00000000, 00000000, 00000000,
* push *
   00100000, 00100001, 10001000, 00001001, * MDR_X_Out, MAR_Wrt, TDR_Wrt, IMM_Out, IMM_Val=0, ALU_Op=1001, ALU_Mode=0, Carry_In_Mux=01, Next=seq(00) *
   00001000, 00000000, 01000100, 00000000, * RD, MDRIn_Mux=1(DB), MDR_Wrt, next=00 *
   00100000, 00100001, 10001000, 00001000, * MDR_X_Out, MAR_Wrt, IMM_Out, IMM_Val=0, ALU_Op=1001, ALU_Mode=0, Carry_In_Mux=01, Next=seq(00) *
   00000000, 00000000, 00000000, 00000000,
   00100000, 00100001, 00000101, 00001000, * MDR_Wrt, PC_Out, MDR_In_Mux=0(Z), IMM_Out, IMM_Val=0, ALU_Op=1001, ALU_Mode=0, CarryInMux=01, next=seq(00) *
   00000000, 00000000, 00100000, 00000000, * MDR_DB_Out, type=00(+1) * * open MDR to DB one cycle before WR goes low *
   00010000, 00000000, 00100000, 00000000, * WR, MDR_DB_Out, type=00(+1) * * WR goes low; MDR_DB still open *
   00000000, 00000000, 00100000, 00000000, * MDR_DB_Out, type=00(00) * * WR goes inactive, but MDR_DB still needs to be open for data to stay stable. *
   01000000, 00000011, 10000000, 00100010, * MAR_Wrt, TDR_Out, (A_Out), ALU_Op=1010, ALU_Mode=1, next=seq(00)*
   00001000, 00000000, 01000100, 00000000, * RD, MDR_Wrt, MDRIn_Mux=1(DB), next=00 *
   11000000, 00000000, 00001100, 00001100, * MDR_X_Out, MDR_Wrt, IMM_Out, IMM_Val=1, ALU_Op=0110, ALU_Mode=0, Carry_In_Mux=00, Next=seq(00) *
   00000000, 00000000, 00100000, 00000000, * MDR_DB_Out, type=00(+1) * * open MDR to DB one cycle before WR goes low *
   00010000, 00000000, 00100000, 00000000, * WR, MDR_DB_Out, type=00(+1) * * WR goes low; MDR_DB still open *
   00000000, 00000000, 00100000, 00000000, * MDR_DB_Out, type=00(00) * * WR goes inactive, but MDR_DB still needs to be open for data to stay stable. *
   11000000, 10000000, 00000001, 00001100, * PC-1: PC_Out, PC_Wrt, ALU_Op=0110, ALUMode=0, CarryInMux=00, IMM_Out, IMMVal=1, next=00 *
* jump *
   00100000, 00100001, 10000001, 00001000, * PC_Out, MAR_Wrt, IMM_Out, IMM(0), CarryInMux1=0, CarryInMux0=1, ALUOp=1001, ALUMode=0, Next=00 *
   00001000, 00000000, 01000100, 00000000, * RD, MDRIn_Mux=1, MDR_Wrt, next=00 *
   00100010, 10100001, 00001000, 00001000; * MDR_X_Out, PC_Wrt, IMM_Out, IMM(0), ALUOp=1001, ALUMode=0, CarryInMux1=0, CarryInMux0=1, type=10(pre_fetch) *
   

* RET STK8 - STK8 holds the address of the stack, used to retrieve PC *
0x34:

* JMP [AD8] - Jumps to address located at AD8 *
0x34: 00100000, 00100001, 10000001, 00001000, * PC_Out, MAR_Wrt, IMM_Out, IMM_Val=0, ALUOp=1001, ALUMode=0, CarryInMux=01, Next=00 *
   00001000, 00000000, 01000100, 00000000, * RD, MDRIn_Mux=1(DB), MDR_Wrt, next=00 *
   00100000, 10100001, 00000001, 00001100, * PC+1: PC_Out, PC_Wrt, ALU_Op=1001, ALUMode=0, CarryInMux=01, IMM_Out, IMMVal=1, next=00 *
   00000000, 00000000, 00000000, 00000000,
   00100000, 00100001, 10001000, 00001000, * MDR_X_Out, MAR_Wrt, IMM_Out, IMM_Val=0, ALU_Op=1001, ALU_Mode=0, Carry_In_Mux=01, Next=seq(00) *
   00001000, 00000000, 01000100, 00000000, * RD, MDRIn_Mux=1(DB), MDR_Wrt, next=00 *
   00100010, 10100001, 00001000, 00001000; * MDR_X_Out, PC_Wrt, IMM_Out, IMM_Val=0, ALU_Op = 1001, ALU_Mode = 0, Carry_In_Mux=01, Next=pre-fetch(10)*

* PUSH A - SP is located at 0x00 *
0x35:
    01000000, 00000011, 10000000, 00101000, * MAR_Wrt, IMM_Out, (A_Out) IMM_Val=0, ALU_Op=1010, ALU_Mode=1, next=seq(00) *
   00001000, 00000000, 01000100, 00000000, * MDR_Wrt, RD, MDRIn_Mux=1(DB), next=00 *
   00100000, 00100001, 10001000, 00001000, * MDR_X_Out, MAR_Wrt, IMM_Out, IMM_Val=0, ALU_Op=1001, ALU_Mode=0, Carry_In_Mux=01, Next=seq(00) *
   00000000, 00000000, 00000000, 00000000,
   00100000, 00100001, 00000100, 00101000, * MDR_Wrt, A_Out, MDR_In_Mux=0(Z), IMM_Out, IMM_Val=0, ALU_Op=1001, ALU_Mode=0, CarryInMux=01, next=seq(00) *
   00000000, 00000000, 00100000, 00000000, * MDR_DB_Out, type=00(+1) * * open MDR to DB one cycle before WR goes low *
   00010000, 00000000, 00100000, 00000000, * WR, MDR_DB_Out, type=00(+1) * * WR goes low; MDR_DB still open *
   00000000, 00000000, 00100000, 00000000, * MDR_DB_Out, type=00(00) * * WR goes inactive, but MDR_DB still needs to be open for data to stay stable. *
    01000000, 00000011, 10000000, 00101000, * MAR_Wrt, IMM_Out, (A_Out), IMM_Val=0, ALU_Op=1010, ALU_Mode=1, next=seq(00) *
   00001000, 00000000, 01000100, 00000000, * MDR_Wrt, RD, MDRIn_Mux=1(DB), next=00 *
   00100000, 00100001, 00001100, 00001100, * MDR_X_Out, MDR_Wrt, MDR_In_Mux=0, IMM_Out, IMM_Val=1, ALU_Op=1001, ALU_Mode=0, Carry_In_Mux=01, Next=seq(00) *
   00000000, 00000000, 00100000, 00000000, * MDR_DB_Out, type=00(+1) * * open MDR to DB one cycle before WR goes low *
   00010000, 00000000, 00100000, 00000000, * WR, MDR_DB_Out, type=00(+1) * * WR goes low; MDR_DB still open *
   00000010, 00000000, 00100000, 00000000; * MDR_DB_Out, type=00(00) * * WR goes inactive, but MDR_DB still needs to be open for data to stay stable. *

* PUSH B - SP is located at 0x00 *
0x35:
    01000000, 00000011, 10000000, 00101000, * MAR_Wrt, IMM_Out, (A_Out) IMM_Val=0, ALU_Op=1010, ALU_Mode=1, next=seq(00) *
   00001000, 00000000, 01000100, 00000000, * MDR_Wrt, RD, MDRIn_Mux=1(DB), next=00 *
   00100000, 00100001, 10001000, 00001000, * MDR_X_Out, MAR_Wrt, IMM_Out, IMM_Val=0, ALU_Op=1001, ALU_Mode=0, Carry_In_Mux=01, Next=seq(00) *
   00000000, 00000000, 00000000, 00000000,
   00100000, 00100001, 00000100, 10001000, * MDR_Wrt, B_Out, MDR_In_Mux=0(Z), IMM_Out, IMM_Val=0, ALU_Op=1001, ALU_Mode=0, CarryInMux=01, next=seq(00) *
   00000000, 00000000, 00100000, 00000000, * MDR_DB_Out, type=00(+1) * * open MDR to DB one cycle before WR goes low *
   00010000, 00000000, 00100000, 00000000, * WR, MDR_DB_Out, type=00(+1) * * WR goes low; MDR_DB still open *
   00000000, 00000000, 00100000, 00000000, * MDR_DB_Out, type=00(00) * * WR goes inactive, but MDR_DB still needs to be open for data to stay stable. *
    01000000, 00000011, 10000000, 00101000, * MAR_Wrt, IMM_Out, (A_Out), IMM_Val=0, ALU_Op=1010, ALU_Mode=1, next=seq(00) *
   00001000, 00000000, 01000100, 00000000, * MDR_Wrt, RD, MDRIn_Mux=1(DB), next=00 *
   00100000, 00100001, 00001100, 00001100, * MDR_X_Out, MDR_Wrt, MDR_In_Mux=0, IMM_Out, IMM_Val=1, ALU_Op=1001, ALU_Mode=0, Carry_In_Mux=01, Next=seq(00) *
   00000000, 00000000, 00100000, 00000000, * MDR_DB_Out, type=00(+1) * * open MDR to DB one cycle before WR goes low *
   00010000, 00000000, 00100000, 00000000, * WR, MDR_DB_Out, type=00(+1) * * WR goes low; MDR_DB still open *
   00000010, 00000000, 00100000, 00000000; * MDR_DB_Out, type=00(00) * * WR goes inactive, but MDR_DB still needs to be open for data to stay stable. *

* POP A - SP is located at 0x00 *
0x36: 01000000, 00000011, 10000000, 00101000, * MAR_Wrt, IMM_Out, (A_Out) IMM_Val=0, ALU_Op=1010, ALU_Mode=1, next=seq(00) *
   00001000, 00000000, 01000100, 00000000, * MDR_Wrt, RD, MDRIn_Mux=1(DB), next=00 *
   11000000, 00000000, 00001100, 00001100, * MDR_X_Out, MDR_Wrt, MDR_In_Mux=0, IMM_Out, IMM_Val=1, ALU_Op=0110, ALU_Mode=0, Carry_In_Mux=00, Next=seq(00) *
   00000000, 00000000, 00100000, 00000000, * MDR_DB_Out, type=00(+1) * open MDR to DB one cycle before WR goes low *
   00010000, 00000000, 00100000, 00000000, * WR, MDR_DB_Out, type=00(+1) * * WR goes low; MDR_DB still open *
   00000000, 00000000, 00100000, 00000000, * MDR_DB_Out, type=seq(00) * * WR goes inactive, but MDR_DB still needs to be open for data to stay stable. *
   00100000, 00100001, 10001000, 00001000, * MDR_X_Out, MAR_Wrt, IMM_Out, IMM_Val=0, ALU_Op=1001, ALU_Mode=0, Carry_In_Mux=01, Next=seq(00) *
   00001000, 00000000, 01000100, 00000000, * RD, MDRIn_Mux=1(DB), MDR_Wrt, next=00 *
   00100010, 00100001, 00001000, 00011000; * MDR_X_Out, A_Wrt, IMM_Out, IMM_Val=0, ALU_Op=1001, ALU_Mode=0, Carry_In_Mux=01, Next=pre-fetch(10) *

* POP B - SP is located at 0x00 *
0x36: 01000000, 00000011, 10000000, 00101000, * MAR_Wrt, IMM_Out, (A_Out) IMM_Val=0, ALU_Op=1010, ALU_Mode=1, next=seq(00) *
   00001000, 00000000, 01000100, 00000000, * MDR_Wrt, RD, MDRIn_Mux=1(DB), next=00 *
   11000000, 00000000, 00001100, 00001100, * MDR_X_Out, MDR_Wrt, MDR_In_Mux=0, IMM_Out, IMM_Val=1, ALU_Op=0110, ALU_Mode=0, Carry_In_Mux=00, Next=seq(00) *
   00000000, 00000000, 00100000, 00000000, * MDR_DB_Out, type=00(+1) * open MDR to DB one cycle before WR goes low *
   00010000, 00000000, 00100000, 00000000, * WR, MDR_DB_Out, type=00(+1) * * WR goes low; MDR_DB still open *
   00000000, 00000000, 00100000, 00000000, * MDR_DB_Out, type=seq(00) * * WR goes inactive, but MDR_DB still needs to be open for data to stay stable. *
   00100000, 00100001, 10001000, 00001000, * MDR_X_Out, MAR_Wrt, IMM_Out, IMM_Val=0, ALU_Op=1001, ALU_Mode=0, Carry_In_Mux=01, Next=seq(00) *
   00001000, 00000000, 01000100, 00000000, * RD, MDRIn_Mux=1(DB), MDR_Wrt, next=00 *
   00100010, 00100001, 00001000, 01001000; * MDR_X_Out, B_Wrt, IMM_Out, IMM_Val=0, ALU_Op=1001, ALU_Mode=0, Carry_In_Mux=01, Next=pre-fetch(10) *   
   

*
1    ALU_Op2, ALU_Op1, ALU_Op0, WR, RD, branch_code, type1, type0
2    PC_Wrt, CarryIn_Mux1, CarryIn_Mux0, CarryOut_Invert, ZF_Wrt, CF_Wrt, ALU_Mode, ALU_Op3
3    MAR_Wrt, MDRIn_Mux, MDR_DB_Out, MDR_Y_Out, MDR_X_Out, MDR_Wrt, IR_Wrt, PC_Out
4   B_Out, B_Wrt, A_Out, A_Wrt, IMM_Out, IMM_Val, TDR_Out, TDR_Wrt
*

* NOP *
0x37: 00000010, 00000000, 00000000, 00000000; * NOP: Total of 5 clock cycles including the previous Fetch. *


« Last Edit: June 13, 2017, 06:18:37 am by PauloConstantino »
 
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Offline Nusa

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Re: Weird things about bypass caps and 74HC logic
« Reply #1 on: June 09, 2017, 09:32:54 pm »
Just because you're still operational doesn't mean you aren't much closer to a malfunction. You need a scope to monitor the power rail at the chip to actually know how close to that line you are.

If you don't have a scope, this page should give you the idea: http://www.vagrearg.org/content/decoupling
 
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Offline Fungus

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Re: Weird things about bypass caps and 74HC logic
« Reply #2 on: June 09, 2017, 10:09:59 pm »
You need to find out the max frequency it will run at with/without.

 

Offline Audioguru

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Re: Weird things about bypass caps and 74HC logic
« Reply #3 on: June 09, 2017, 10:32:47 pm »
That is the biggest mess of wires all over the place that I have ever seen! I made many complicated high speed circuits using 74LSxx TTL ICs with the parts soldered on stripboard with its strips cut short as possible and only a few very short jumper wires (a compact layout) and they all worked perfectly. They looked good enough to be sold as the final product (only 1 or 2 were made).
 

Offline MagicSmoker

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Re: Weird things about bypass caps and 74HC logic
« Reply #4 on: June 09, 2017, 10:38:25 pm »
Also, the 74HC family is fairly slow (only 4000 series CMOS is slower, IIRC), which helps avoid signal integrity issues from a lack of ground plane, supply bypassing, etc.

Try that crap with 'LVC and see how far you get... Note that it is the edge speed that really gets you into trouble, not so much the clock frequency.

 

Offline magetoo

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Re: Weird things about bypass caps and 74HC logic
« Reply #5 on: June 10, 2017, 12:13:19 am »
74HC is pretty tolerant and 5 MHz is not very fast.  Oneironaut/Brad over at the 6502.org forums built a monstrous VGA graphics project in 74HC logic, running at 25 MHz over one square meter of breadboards with no decoupling caps on the chips and that also worked just fine.

The common wisdom about decoupling seems to come mostly from greybeards who are used to TTL families and people in the industry who are going much faster with much more sensitive parts like FPGAs.  For a hobbyist today who is building things out of slower logic families it's a good idea but not that critical.
 

Offline German_EE

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Re: Weird things about bypass caps and 74HC logic
« Reply #6 on: June 10, 2017, 02:47:44 am »
The rule I normally follow is a 100nF capacitor per device and a 10uF capacitor for every five chips. Yes, I do have a gray beard.

However.........

The first thing that comes to mind is the capacitance between the strips on your breadboards, this cannot be ignored and to some extent it will replace the bypass capacitors. Running without them though is like driving without a seatbelt, you can get away with it but it's not advisable.
Should you find yourself in a chronically leaking boat, energy devoted to changing vessels is likely to be more productive than energy devoted to patching leaks.

Warren Buffett
 
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Offline DBecker

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Re: Weird things about bypass caps and 74HC logic
« Reply #7 on: June 10, 2017, 07:07:56 am »
Errrm, I do have a gray beard, and have built complex boards with TTL where careful wirewrapping was barely clean enough.

HC parts are very different than the 7400 and 74LS parts that absolutely needed decoupling beside each chip.  TTL is asymmetrical and voltage level sensitive, rather than ratiometric.  A voltage sag with CMOS results in slower transitions, which doesn't matter at all with conservative timing.  A voltage sag with TTL results in changing state, and voltage glitches might show up as extra clocks.

 
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Offline james_s

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Re: Weird things about bypass caps and 74HC logic
« Reply #8 on: June 10, 2017, 07:14:04 am »
Holy crap! That makes my head spin just looking at that rat's nest, I'm amazed you got it to work at all, I would have been tearing my hair out trying to keep track of them all.
 

Offline DimitriP

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Re: Weird things about bypass caps and 74HC logic
« Reply #9 on: June 10, 2017, 07:33:31 am »
Quote
Can anyone explain what's going on?
With this many  jumpers , on breadboards , there is enough capacitance and inductance spread around that  standard rules are so far out the window, you can't even see the window.

   If three 100  Ohm resistors are connected in parallel, and in series with a 200 Ohm resistor, how many resistors do you have? 
 
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Offline bson

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Re: Weird things about bypass caps and 74HC logic
« Reply #10 on: June 10, 2017, 07:41:32 am »
5MHz is pretty far from the operational limits of HC logic...
 

Offline KE5FX

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Re: Weird things about bypass caps and 74HC logic
« Reply #11 on: June 10, 2017, 08:26:12 am »
The other reason for those bypass caps in commercial designs is that you don't want to be the subject of an email entitled FW: FW: FW: FW: Get a load of this, guys! ROFL that gets passed around for years at the FCC.
 

Online T3sl4co1l

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Re: Weird things about bypass caps and 74HC logic
« Reply #12 on: June 10, 2017, 10:22:12 am »
You probably aren't testing with sufficiently random noise to see problems.  You certainly aren't testing to find the noise margin, making this observation nearly meaningless.
 :P

Paranoia about bypass caps is largely overrated, anyway.  The advice is repeated out of ignorance, and usually winds up doing more good than harm, so in the absence of proper analysis, it's the best minimum.

But there are absolutely situations where applying the advice actively harms the circuit.  Nothing can replace properly understanding and analyzing the power supply network!

Back when I built this thingy,



It would run ~forever with a repetitive program, but crash randomly (within days) when I added a LFSR routine.

Additional supply bypass didn't have any effect on stability, but that is obvious from PSN analysis -- the +/- wires are always nearby, so the impedance between them is small, and the effect between regions is small (the PSN has a low impedance, so there is little ripple propagating through it).  No, the problem is the PSN shape relative to the routed signals, and the routed signals themselves which are through air, high impedance (>100 ohms), and not routed in parallel with the PSN, but across rungs of it.

Most likely failure mode would be: a bunch of (data or address) lines all change at once, causing a large enough displacement current along the bus, in turn causing signal bounce between the local supply (which is "cantilevered" out on a rung, here) and the bus signals.  It doesn't take much bounce to violate the TTL V_IL (0.8V).

In effect, you get a series resonant circuit, between the supply inductance (of the +/- leads in parallel), input pin capacitances (all acting in parallel), bus wires (all acting in parallel), and all pin drivers (acting in parallel and driving the circuit).

74HC is somewhat faster than TTL, lower current consumption, and symmetrical logic threshold (= more noise immunity).  It's fast enough to cause signal quality issues on modest length runs (~1m+), and questionable behavior on a breadboard.  You're lucky to escape problems with a board that size -- but, you may also be just that: lucky.  Without checking actual signal quality, who knows?

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 
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Offline Ian.M

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Re: Weird things about bypass caps and 74HC logic
« Reply #13 on: June 10, 2017, 02:17:03 pm »
As I mentioned earlier in the O.P's other topic, most of us don't even have the test equipment to adequately assess signal quality in a large breadboard or protoboard project:

Assuming 74HC logic at 5V, signals and glitches up to around 100MHz* are possible (not that they will work as intended), and as it requires 5x greater bandwidth than the fundamental frequency to view a squarewave without excessive distortion, that means you need a 500MHz scope., and due to the absence of an effective ground plane, to avoid the extra ground paths via the scope probes changing the circuit's operation, you'll need differential probes for all input channels, and, again to avoid excessive disturbance of the signals, they'll  need to be low input capacitance ones.  Then there's the issues with detecting and determining the cause of the malfunction. - in complex clocked LSI logic, the original glitch may be tens or even hundreds of cycles earlier than its first visible result. Assuming you have some way of post-triggering on the malfunction, if you are sampling fast enough to catch the glitch, there are going to be a *LOT* of samples between the glitch and the trigger point.

e.g. Lets suppose the glitch is a 10ns 'runt' pulse clocking or latching something at the wrong time, and the system clock frequency is 1MHz, if it takes 10 clock cycles for the glitch to corrupt an accessible output, there will be a thousand times more data after the glitch than during the period of interest around the glitch.

That's a fairly conservative set of assumptions - the clock could easily be slower and the number of clock cycles for the glitch's effects to show, significantly greater.   Therefore, a scope with only kilosamples of memory depth will be pretty much useless for this sort of work, you need megasamples of depth.

At this point it should be fairly obvious that cheap scopes aren't going to be up to the job - $1000 of scope sitting on your bench is as likely to mislead you as not.  Get up to $10K of appropriately specified scope and probes and you'll have a reasonable chance of an experienced tech being able to trace the malfunction back to the original glitch, without too many diversions chasing ghosts.

Then there's the matter of how rare the glitch is.  Again, assuming a 1MHz system clock, and this time assuming its a CPU of some sort, a one in a billion (10e9) glitch only gives you an up-time of 16.66 seconds before it crashes.  Unless you can make the glitch easily reproducible (without 'forcing' a new glitch), it is likely to take many man hours to track down.

The extra time and cost of doing grounding and decoupling 'by the book' are negligible - 100nF disc ceramics can easily be had for $0.02 each in very moderate quantities, and it only takes seconds to plug them in.   Leave them out and sooner or later you will waste hours or days attempting the de-glitch your project.

The time to look at decoupling more seriously to see how far it can be minimised without excessively compromising performance and/or reliability is when you are preparing a desgn for high volume production. Even Mad Man Muntz didn't stop his designers adding decoupling caps in the first place - he only snipped them out from WORKING circuits - and those were simpler analog days when loss of signal quality was readily and immediately apparent. 

* 74HC74 - max CP frequency 76MHz @5V Vdd.
 
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Offline EEVblog

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Re: Weird things about bypass caps and 74HC logic
« Reply #14 on: June 10, 2017, 03:03:38 pm »
I just wanted to  :clap: the breadboard art
 

Offline jcerqueira

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Re: Weird things about bypass caps and 74HC logic
« Reply #15 on: June 10, 2017, 03:32:09 pm »
I got curious. Did you measure the total power consumption for the entire circuit?
 

Offline uwezi

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Re: Weird things about bypass caps and 74HC logic
« Reply #16 on: June 10, 2017, 07:57:28 pm »
Kudos to that design!

As others have already pointed out here, the fact that your tests didn't show any problems does not mean that you are not on the edge of malfunction.

Why do we use these bypass caps? They are there to provide some extra charge carriers through a low-inductance connection to the switching transistors on the chips. When a CMOS gate switches from one state to the other the chip draws a significantly higher current than in steady state (where CMOS consumption is almost zero). This current, i.e. these charge carriers have to be delivered to the chip quickly, otherwise the supply voltage will locally drop, Gnd will go up and Vcc will go down. If the charge is not delivered "in time" this may go so far that the logic levels for 0 and 1 shift and you get false signals into your circuit.

The more transistors which switch at the same time, the more critical is the situation. In standard 74HC gates there are only a couple of dozen transistors in each package and in your circuit only a fraction of these will normally switch at the same time. There might be the worst case scenario only happening once a day or once a week when too many transistors switch at the same time and then your circuit will fail. You might not even notice it in general.

For standard 74HC 100nF capacitors are definitely larger than you need, but on the other hand too large capacitance does not harm. And buying a large stock of same-size capacitors is simpler and cheaper than trying to find the exact capacitance which you might need for each individual part. Also in your case the parasitic capacitance in the breadboard and wiring and the probably low impedance of your wires as compared to narrow traces on a pcb work in your favor here.

I just recently read an old text book "EMI control in the design of printed circuit boards and backplanes" by Donald White (1982). There is a very detailed analysis of the circuits and as a rule of thumb he recommends 500pF/gate for CMOS, 3000pF/gate for old-style TTL, 2500pF/gate for LS. On many old-school TTL boards you would find 10nF capacitors per chip. I personally always use 100nF for TTL and microcontrollers alike.... just because...
 
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Offline NANDBlog

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Re: Weird things about bypass caps and 74HC logic
« Reply #17 on: June 11, 2017, 02:20:40 am »
You place a 100nF capacitor because 5.000 of them costs 3 EUR. And for sure, it will make things better, unless you have a really bad habits of designing PCBs. And I have to repeat myself again and again:

Something which is working does not mean it is properly done. Properly done is the difference between engineering, and mucking around with electrons. A "just working" LED light will burn down your house after it electrocutes you, a properly designed will blow the fuse inside and double insulate all the metal parts that you can touch.
 
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Offline janoc

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Re: Weird things about bypass caps and 74HC logic
« Reply #18 on: June 11, 2017, 04:50:31 am »
I just wanted to  :clap: the breadboard art

Thanks Dave :) Since this became a curiosity, the computer runs all its instructions perfectly and it has been given a sound circuit and is now playing 8bit music.

Here's an earlier video of it working:

 :o

Whooa, debugging that had to be a nightmare.

Well, you certainly have the knack if you have got that contraption working.   :clap: :-+
 

Offline PauloConstantino

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Re: Weird things about bypass caps and 74HC logic
« Reply #19 on: June 11, 2017, 07:00:20 am »
I just wanted to  :clap: the breadboard art

Thanks Dave :) Since this became a curiosity, the computer runs all its instructions perfectly and it has been given a sound circuit and is now playing 8bit music.

Here's an earlier video of it working:


 :-+

 :o

Whooa, debugging that had to be a nightmare.

Well, you certainly have the knack if you have got that contraption working.   :clap: :-+
 

Online jbb

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Re: Weird things about bypass caps and 74HC logic
« Reply #20 on: June 11, 2017, 09:06:24 am »
It's a bloody impressive arrangement.  There are a lot of wires to get right!

On the decoupling caps front, you should remember that the traditionalist approach isn't 100% necessary, and is traditionally aimed at making products.  There are many things which can change when you make 10000 pieces:
  • Some units will operate at very different temperatures
  • Some units will have different power supply voltage levels (variation in regulator chips)
  • A different batch of chips might have different response times
  • Someone might substitute a part (maybe during a repair)
  • You might have EMC problems (either spewing out noise or failing when external RF fields are applied)

If you just want to operate your prototype at a fairly constant temperature and nothing terrible will happen if the processor does something weird, don't stress about all the caps.
 
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Offline Bendba

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Re: 8bit CPU made from 74HC logic.
« Reply #21 on: June 12, 2017, 12:28:59 am »
My rule is that if the first prototype works well without caps, the final project can't crash once you add them.
Stop dreaming your life, start leaving your dreams.
 
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Offline ChristofferB

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Re: 8bit CPU made from 74HC logic.
« Reply #22 on: June 12, 2017, 07:53:15 am »
My rule is that if the first prototype works well without caps, the final project can't crash once you add them.

Wise words!
-And amazing project, by the way! If only I had your patience.
--Christoffer
Check out my scientific instruments diy (GC-FID, NMR, etc) tumblr:
https://chrisbnstuff.tumblr.com/
 
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Offline PauloConstantino

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Re: 8bit CPU made from 74HC logic.
« Reply #23 on: June 12, 2017, 08:35:03 am »
Hi I want to thank everyone for the kind responses.


The CPU has been running fine at 5MHz for days now. It hasn't crashed once! It runs a validation "test suite" that gives sets a few flags in case of errors.

At any rate, I have changed the original topic of this post given that Dave published this in his blog and people are finding it amusing.
« Last Edit: June 12, 2017, 10:02:11 pm by PauloConstantino »
 

Offline technix

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Re: 8bit CPU made from 74HC logic.
« Reply #24 on: June 12, 2017, 10:51:00 am »
Maybe you can try rearrange the ISA into something more orthogonal. This way you can significantly reduce the amount of microcode needed.

I am trying to cook up an ISA too. Things are a bit different as I prefer RISC over CISC. I have chosen to use the format of a few instructions as the basis of all other instructions.
 


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