Could do it with a RasPi compute module or other processor board and seperate FPGA, however I can imagine there is a potential advantage to keeping the high speed FPGA to Processor communication inside the SoC.
Given ADC throughput is SPI at upwards of 24MHz for desired sample rate, it could be possible that I just continue to use the development board I have chosen paying care and attention to the wires to the ADC.
I appreciate there is a trade-off between time to market and the performance of the end product. I can imagine using a faster/better processor could reduce the need for an FPGA, however to my mind, the correct design approach is to take advantage of the parallel nature of an FPGA and break the matrix computations down into a parallel hardware implementation, taking advantage of DSP blocks/slices. Worst case, I can always take my verilog implementation and the relevant C code and move it into a more capable FPGA/CPU/SoC, if I was unable to achieve the desired resolution/speed trade-off.
Thanks for the numbers, I had already decided to rule out having someone else design the board, given it could cost as much as £20,000.
I could see it taking a few months for each stage.
Yes Mike, you're probably right. £10K might get me a few iterations of prototypes.
I will have a better look at ready made solutions, even if I have to compromise sample rate initially it would get my feet off the ground more quickly and at lower cost.