when should i be concerned about length matching and impedance matching?

[alireza7]

hi,
i'm working on a project that has a 2 channel 65mhz adc (ad9238-65) and i want to read two channels with one data bus so the frequency that i work with is 65*2=130mhz.

i heard about length matching and impedance matching and its importance but i don't know when they are necessary and my question is:

1-generally in which case i should do length matching and impedance matching?

2-should i do length matching and impedance matching in my project ?

[Rerouter]

For impedance matching, that comes down to the edge transition speed, I'm overkill, so anything approaching 1/20th of wavelength i impedance match, use a tool like saturn pcb, to calaculate it for you, and yes you can impedance match vias,

As for length matching, as its double data rate, make sure its within 10% of a clock cycle to give yourself some margin (your sampling window is at best half a clock cycle)

[ali_asadzadeh]

Exactly

[kosine]

Slight correction: Speed of light is indeed about 1 foot per ns, but " means inches, whereas ' means feet. (Lovely mixing of imperial and metric!)

And technically the speed of electricity is about 3/4 of the speed of light, but it varies depending on the conductor, so I wouldn't worry about it.

[Benta]

I'm a metric/decimal guy, so my rule-of-thumb is 5 ns/m.
This is true for RG-58, but a matched line on FR-4 is in the same ballpark.

[CatalinaWOW]

So far everyone has told him how well to do the job, not why to do it, which is the question I think he asked.  The two questions are not independent.

I am sure others here can answer that better than I, but here is the general one that make sense for me.

You are doing an A/D to measure a signal.  The need for matching of the lines will depend on how well you intend to represent that signal.  If you are aiming for 2 bit (25%) accuracy you need to get the sampling times close enough to the theoretical time to give much less than 25% error with worst case slope on your 65 MHz signal (remember Nyquist says the best you can do is half the sampling rate).  How much less?  That varies from case to case.  This isn't the only source of error and you want all of the errors to add up to less than your 25% goal. 

As you up the number of bits the timing accuracy needs to increase correspondingly.  Most applications want significantly more than 2 bit accuracy.

As another addendum - if you can measure and know the difference in timing of the two channels, and want to jump through some fancy math hoops you can compensate to some degree.  This isn't perfect which you can see by thinking of the case where the two path lengths differ by exactly one half sample interval.

[CatalinaWOW]

You are doing an A/D to measure a signal.  The need for matching of the lines will depend on how well you intend to represent that signal.  If you are aiming for 2 bit (25%) accuracy you need to get the sampling times close enough to the theoretical time to give much less than 25% error with worst case slope on your 65 MHz signal (remember Nyquist says the best you can do is half the sampling rate).  How much less?  That varies from case to case.  This isn't the only source of error and you want all of the errors to add up to less than your 25% goal. 

Usually sample and hold and DAC are built into the same chip, so clock skew will only affect inter-chip delay mismatch. For a single ADC design, it doesn't matter. Data line skew, as long as they are much less than 1/2 Tclk, they won't hurt.
Your slope theory applies to random clock skew, aka. jitter. For a well determined delay, such as PCB routing delay, this doesn't reduce SFDR.

OK, I don't disagree with what you have said.  Does that boil down to an answer of NO to the OP?

[Vtile]

I'm far from 'radio' (now called electronics) engineer as many other gents here. You did ask when should lenght and impedance matching to be considered. You have had different technical answers so far. Unfortunately they do not answer your question. The right simple answer is obviously when it makes difference. Impedance matching obviously is important for amplitude and frequency responce and lenght matching for delta time errors. When it should be done? ...always when you are after precision and accuracy, which are both highly subjective. Lenght and impedance matching are crucial even on many DC and extra low frequency aplications.

[NorthGuy]

For digital connections, you need to do timing analysis.

Your receiving device (whatever receives digital data from ADC) will sample the data at the clock edge. You need to ensure that when the edge comes, the correct data is on the line. For that, the receiving device will have two characteristics (typically in the datasheet):

- setup time - how much before the clock edge the data must be on the line. For example if setup is 3 ns, you must make sure that the data is on the line at least 3 ns before the clock edge.

- hold time - how long the data must be kept on the line after the clock edge. For example if hold is 2 ns, you must make sure that the data is still on the line for at least 2 ns after the clock edge.

The circuit/PCB design must make sure that the setup/hold requirements are met. So, you calculate two entities:

First, you calculate the longest delay, which would consist of

- clock jitter (the edge may be a little late)
- the maximum delay which is necessary for the clock to get out of your device
- the clock PCB trace delay
- the maximum ADC delay (see the datasheet)
- the longest data PCB trace delay on the way back
- clock jitter (the receiving edge may be a little earlier)

Then you calculate the difference between the receiver and ADC clock edges. Say, if ADC posts data on the rising edge and you want to receive on the falling edge, it is half of the clock cycle - about 7ns at 60 MHz. Then you subtract the setup requirement from that number. The result tells you how much of a delay can be tolerated. You compare it to your longest delay. If your longest delay is bigger, your interface won't work.

Similarly, you calculate what happens if things happen fast. The shortest delay will consist of:

- clock jitter (the edge may be a little early)
- the minimum delay which is necessary for the clock to get out of your device
- the clock PCB trace delay
- the minimum ADC delay (see the datasheet)
- the shortest data PCB trace delay on the way back
- clock jitter (the receiving edge may be a little late)

Also, you calculate what is the shortest delay you can tolerate. The short delay might be bad because ADC may post the next data too soon - before your receiver is done with the previous data point. So, you calculate the difference between the clock edge where your receiver samples the data and the clock edge where the ADC produces the next data point. This may be negative (which is a good thing). You add your device's hold requirement to this, which may turn it into positive. You compare the result to the shortest delay you have just calculated. If the delay is too short, your interface won't work.

Once you do such timing analysis, you will see if your data connection works or not. If it is on the edge of working, you will have to change something. One of the things you can do is to make PCB traces shorter (to decrease delays), longer (to increase delays), or more even (to decrease the difference between minimum and maximum delays). If your timing analysis shows that there's a need to make data lines more even, you need to worry about the length matching.