Author Topic: Z80 memory banking for 128K - MMU design  (Read 3653 times)

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Offline nockieboy

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Z80 memory banking for 128K - MMU design
« on: November 09, 2017, 03:19:53 AM »
Hi everyone,

Okay, I've been busy learning more assembly and writing CP/M software for my Z80 SBC these past few weeks and now I'm taking a break to finish off a couple of hardware tasks I'd like to complete on it.

I'm having more than just a little trouble getting my head around designing an MMU for my Z80 that will allow it to use a 17-bit (128KB) address space. 

For those that are unaware of my lengthy previous post in these forums regarding Z80 fault finding, I'll just state that my software capability far outstrips my hardware and soldering skills.  My Z80 currently resides on a breadboard, but is otherwise a fully-functioning computer with 64K SRAM, CTC, SIO/2, PIO and an Atmega328 micro-controller providing multiple speeds of system clock (2, 4 and 8 MHz selectable from CP/M 2.2 which runs just fine from the CompactFlash card.)

It has a 128KB SRAM chip, though and I would really like to be able to give the Z80 access to the full 128KB of SRAM goodness.  However, after much digging online and finding precious little regarding MMU designs for the Z80, I am resorting to asking here for a bit of a leg-up on the circuit design.

Here's the design specs (or intended memory map, if you will):



So as you can see, I want to divide the memory space into 4 blocks of 16KB:

Area 0, the base 16KB of memory, will be fixed as this forms the ROM space when the computer first boots up and, when CP/M is running, this area is RAM and houses a lot of important CP/M vectors and the start of the TPA.

Area 1 is the second 16KB of RAM space and, if CP/M isn't running, houses a lot of important information for the ROM like the stack, command buffer etc.

Area 2 is the top 16KB of the TPA in CP/M and free memory - so this is the 16KB bank of RAM I'd like to be able to switch with one of the four 16KB banks in the upper 64KB of the SRAM.

Area 3 is the top 16KB of the 64KB addressable by the Z80 (the bottom half of the 128KB SRAM) and is where CP/M, CBIOS etc reside.

So I'd like to be able to swap in any of four 16KB banks in the upper half of the 128KB SRAM into Areas 0, 1 or 2.

So what have I tried so far?  :-//

Well, aside from hunting out some not very helpful schematics online, like this one https://sites.google.com/site/oldcpusrus/home/simple-mmu-for-the-z80, which confuses rather than helps me (remember I'm not so hot on the electronics side), I came up with the beginnings of an MMU design on the back of a fag packet (or would have been if I smoked):



So this allows me to swap Area 2 for Bank 1 or Bank 2 in the upper 64KB of SRAM.  I think.  BUT I can't work out how to finish the schematic so that ANY other 16KB bank in the upper 64KB can be mapped to Area 2 - at least not without the addition of lots of convoluted circuits and logic chips to force the values of A15 and A14 depending on the output from the 273... but then I don't want to mess with the addressing of normal, non-banked memory space.  |O

So, would anyone be kind enough to give me some explicit guidance on how I need to design the circuit (as simply and with as few chips as possible) so as to expand the address bus to 17 bits and allow me to map any of the 4 banks in the top half of the 128KB SRAM to Area 2 in the lower half of the memory space?

UPDATE: (Edited to update requirements for CP/M 3 compatibility.)

I've been reading through the CP/M 3 system guide (seems I should have done that before I decided the specifications for the MMU  :palm:) and it appears that CP/M 3 wants the bottom three areas (0, 1 and 2) to be switchable, rather than just the one...

So now I'm looking to have three switchable 16KB banks, Areas 0, 1 and 2, that I can switch the banks in the upper 64KB into and out of at will.  I like the idea of being able to map any bank to any area in the memory space, so that's a key requirement for the MMU design now.
« Last Edit: November 09, 2017, 07:47:07 AM by nockieboy »
 

Offline Mjolinor

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Re: Z80 memory banking for 128K - MMU design
« Reply #1 on: November 09, 2017, 03:33:52 AM »
It has been a long time since I did any messing with Z80s, around 40 years if I had to guess.

At that time I would probably have solved this problem with a UVEPROM that contained a look up table and used the data lines to drive the relevant address lines on the thing I wanted the data from.

I hope that is enough to start your brain because specific would really tax me nowadays.
 

Online jm_araujo

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Re: Z80 memory banking for 128K - MMU design
« Reply #2 on: November 09, 2017, 04:04:03 AM »
I think you can solve it with a single  74HCT157 - Quad 2-input multiplexer. See attached schematic.

I didn't redesign the parts already in your schematic. "Dn_Latch" are the outputs from the 74hct273 (with an extra D2), "1Y" is the same as yours (area 2 selected).
If other area is selected A16=0, SRAM_A14/A15=CPU_A14/A15

If area 2 is selected, A16=D0, A14=D1, A15=D2 (change as it best suits you, it was made in a rush).

This way you can map any memory area to area 2, so be careful :)

 

Offline bsudbrink

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Re: Z80 memory banking for 128K - MMU design
« Reply #3 on: November 09, 2017, 04:05:27 AM »
Use something simple like a 7475 latch at a particular I/O address to drive some of the EPROM pins and give you software control over the banking.
 

Online glarsson

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Re: Z80 memory banking for 128K - MMU design
« Reply #4 on: November 09, 2017, 05:12:17 AM »
The CP/M system I designed, built and used in the early eighties had a MMU designed using 74170 register file (SRAM). The 7417 is (was?) an odd thing with separate data and address lines for writing and reading. It has two address lines and four data lines (not a large RAM).

The way to build a MMU from it to connect A14 and A15 (on the Z80 side) to the two address lines used for reading and the four data outputs to A14, A15, A16 and A17 (bus side). RE (read enable) is grounded. More 74170 can be used to address even more memory and/or address smaller segments. Note that the 74170 has open collectors on the data outputs and will need pull up resistors. The four data inputs connect to D0, D1, D2 and D3 on the Z80. The two address inputs connect to A0 and A1 on the Z80. The write enable (WE) connect to some decoding logic that decodes the port space and write signals from the Z80.

The 74170 will now appear as four byte sized I/O ports (write only).

After reset the content is unknown so you can not use anything on the bus side until the 74170 has been initialized. I did this by having the boot EPROM on the inside of the MMU. It had incomplete address decoding so it was replicated all over the 64k address space. When the Z80 started running at 0000 it jumped up to the same EPROM at 64k-4k. After initializing the 74170 it then copied itself over to RAM (the write signal went to the bus, the read signal to the EPROM). Then a flip/flop was set and the EPROM was removed from the address space.

I ran CP/M 3.0 (also known as CP/M Plus) on this machine. This version of CP/M supported memory banks. The way I used my MMU was to have 16k at the bottom for CP/M variables and first part of the TPA and 16k at the top for the last part of the TPA. At the top was a very small bios used to switch bank and vector all CP/M calls to a different memory bank. The middle two 16k banks had three alternatives, 32k TPA, 32k disk buffers or 32k CP/M bios and bdos.
The memory was 64 times 6116 CMOS RAM (2k-byte) for a total of 128k. All wire wrapped. The MMU used more than one 74170 to make expansion to 1MB possible, but that never happened. To expensive (both cost of RAM and wire wrapping time).
 

Offline David Hess

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Re: Z80 memory banking for 128K - MMU design
« Reply #5 on: November 09, 2017, 07:35:27 AM »
One trick I remember is to have separate banking control for reads and writes.  Now banks may be configured to act like ROMs if necessary, ROMs may be copied into overlayed RAM which is then swapped, and copying from the current visible bank to a hidden bank at the same addresses becomes trivial.
 

Offline nockieboy

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Re: Z80 memory banking for 128K - MMU design
« Reply #6 on: November 09, 2017, 07:42:59 AM »
Okay, thanks guys - there's some good starters for 10 there.  I've been reading through the CP/M 3 system guide (seems I should have done that before I decided the specifications for the MMU  :palm:) and it appears that CP/M 3 wants the bottom three areas (0, 1 and 2) to be switchable, rather than just the one...

So now I'm looking to have three switchable 16KB banks, Areas 0, 1 and 2, that I can switch the banks in the upper 64KB into and out of at will.  I like the idea of being able to map any bank to any area in the memory space, so that's a key requirement for the MMU design now.

If at all possible, I'd like to do it with discrete logic rather than more RAM or EEPROM chips (seems like overkill?)

I think you can solve it with a single  74HCT157 - Quad 2-input multiplexer. See attached schematic.

I didn't redesign the parts already in your schematic. "Dn_Latch" are the outputs from the 74hct273 (with an extra D2), "1Y" is the same as yours (area 2 selected).
If other area is selected A16=0, SRAM_A14/A15=CPU_A14/A15

If area 2 is selected, A16=D0, A14=D1, A15=D2 (change as it best suits you, it was made in a rush).

This way you can map any memory area to area 2, so be careful :)

That sounds like the ideal solution so far - would it require much alteration to allow mapping to ANY area, not just Area 2?
 

Offline C

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Re: Z80 memory banking for 128K - MMU design
« Reply #7 on: November 09, 2017, 07:44:31 AM »
Need to get your head around memory management. It can be simple, your computer is doing it now.

Area 0
You now have a bit that is controlled by an z80 out instruction. This bit and Area 0 select enables one of two chips.You have a switch with output enabled by Area 0 select. The switch controls which chip select is enabled.
If you add one more bit then you would have four different states. when combined with Area 0 could select one of four chips by using chip select. Area 0 would enable output of a 139
With three bits, you could select one of eight chips. This would use a 138.
So this is many chips swapped into one area.

Now lets look at many areas of a chip swapped into one area.
If the bit is connected to an address line of a chip, you could switch between two areas of the chip. So the Z80 would access Area 0 and the bit would select one of two blocks of memory on the chip.
If you added one more bit(2), you would get 4 blocks from chip. With three bits you get 8 blocks.

Now if you put both of above together you have a X-Y matrix of block. Some bits select what chip ( row ) and some bits select the block (column).

Now this is all using Area 0 select, but you also have four areas to deal with. You want to use the blocks from one chip in the different areas. You get four layers in the Z direction when you add the area selects.

To have the blocks work with four areas you need four sets of bits to select what block is used in each area. You also need a switch to select what set of bits is used.
A 273 has 8 bits, so you could have two bits for each area. You would need a dual one of four data selector to do this. The output of data selector connects to chip address lines and selects one of four sets of bits on the input.
Now if you add an additional 273 and dual 1 of 4 selector you could have four sets(area) of 4 bits(block). Do some numbers, Four Areas of 16k for Z80 & 16 blocks of 16k for memory(256k).   So you have two 273 and two 153 to do this.
Now ram/rom switch is included, Using this larger address space, Rom is addressed 0-128k and ram is addressed 128k-256k.
With power up resetting the two 273's you have the the first block of Rom in each Area. With two Z80 output instructions you can have any block in any Area.

Now that you have got this far, look at the 74LS670 again. Data sheet states it is a 4 x 4 register file. Four sets of bits with each set four bits wide.
To work with this chip you would use 4 I/O addresses and write just 4 bits. The above using two 273's lets you use just two addresses and write two sets of four bits.
Note that the special thing about the 74LS670 is that it has one set of pins to write to the chip and a second set that is used for read. The write set would be connected to Z80 I/O. The Read set address lines are connected to Z80 A14-A15 giving you four areas. The read data outputs are the expanded address A14-A17 address lines. You should note that on power up the data in the 74LS670 is unknown which will need more chips to correct so that Rom is in place on power up..
 
------
Think of a separate memory card. Rom responds to addresses of 0-128k and Ram responds to addresses 128k-256k.
The A14-A17 address lines are connected to the outputs of the 153's.
The A0-A13 address lines are connected to the Z80.
The other lines are connected to Z80 like normal memory.

The Inputs to 153's are connected to outputs of the 273.
The two select lines(a0-a1) of 153 are connected to Z80 A14-A15
The Strobe lines are tied low.
With two 153's each being dual you have a 4 of 4 data selector.

The two 273's are connected as Z80 output ports and the outputs are the four sets of four bits for input to 153's
The 273's are reset on power on so that you get Rom on power up.

Now the cement.
You want four areas of 16k. This uses two bits to select area. If you only had two bits of data in the four sets, you would have four blocks that you could put in any of the four areas. This is four areas with four blocks. You need more bits in each set to expand. Each extra bit per sett doubles the number of blocks.
If you understand how this works  then you can expand even more. Each 153 adds two more expanded address lines and would need input data.
Note that the data sits at inputs of the 153's so that the upper expanded address lines are delayed by 153's input select time.

This is greater then what you asked for, but in the process uses few general chips and works with power on.

 
 
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Offline nockieboy

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Re: Z80 memory banking for 128K - MMU design
« Reply #8 on: November 09, 2017, 10:15:29 PM »
I think you can solve it with a single  74HCT157 - Quad 2-input multiplexer. See attached schematic.

I didn't redesign the parts already in your schematic. "Dn_Latch" are the outputs from the 74hct273 (with an extra D2), "1Y" is the same as yours (area 2 selected).
If other area is selected A16=0, SRAM_A14/A15=CPU_A14/A15

If area 2 is selected, A16=D0, A14=D1, A15=D2 (change as it best suits you, it was made in a rush).

This way you can map any memory area to area 2, so be careful :)

Would an SN74HCT257N be a suitable replacement for the 74HCT157?  I'm trying to avoid SMD if at all possible as my soldering skills are probably not up to it!
 

Offline nockieboy

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Re: Z80 memory banking for 128K - MMU design
« Reply #9 on: November 09, 2017, 10:20:23 PM »
Need to get your head around memory management. It can be simple, your computer is doing it now....
[SNIP]
This is greater then what you asked for, but in the process uses few general chips and works with power on.

I'm going to have to go away and think about what you've written, C - for quite a while. Maybe even draw some diagrams before I can understand the premise.. there's a lot there!  :o
 

Online jm_araujo

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Re: Z80 memory banking for 128K - MMU design
« Reply #10 on: November 09, 2017, 10:45:39 PM »
Would an SN74HCT257N be a suitable replacement for the 74HCT157?  I'm trying to avoid SMD if at all possible as my soldering skills are probably not up to it!

In this case it will work the same.
 

Offline C

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Re: Z80 memory banking for 128K - MMU design
« Reply #11 on: November 10, 2017, 07:13:40 AM »
nockieboy

  sorry looks like my cement was not good.
Try making a picture.

Large sheet of paper.
1. On right side make a box an label it memory. Draw a line across this block as half is rom and other half is ram.

2. On left side make a box an label it Z80.

First question
   How many areas will Z80 memory be?
When you have number of Z80 memory areas then you know what kind of switch you need. 
You stated 4 Z80 areas, so you need a 4 throw switch.
3. Draw a 4 throw switch to right of center of drawing.

With 4 Z80 areas you have
 Z90
      A15 - A14                          these are area select lines.
                       A13-A0             these are address in the area & block

Expanded memory
  Ea17-Ea14                             These are the block in expanded memory
                       Ea13-Ea0          These are the address in the block.

Back to your drawing

4.  Now to the left of center need to draw something for block address data.
     From switch side you have four boxes.
    From Z80 you have two boxes that are split
So Two boxes wide & two boxes high with some white space separating the boxes

5. now add some logic lines.
  a.  each box of #4 will be connected to a switch input.
  b. the two horizontal boxes will be written by a Z80 out instruction.
  c. The switch position will be controlled by Z80 A14 & A15
  d. The remaining Z80 addresses are connected to memory box.

On Power up you reset the 273's, so all bits are 0 in #4 boxes.
So
6. In memory box, Rom must be low address range of memory to match the 273 on reset.

So you have the 4 boxes of #4 that the contents of a box is Ea17-Ea14   The extended memory block address for that Z80 area.
The switch is selecting which box of data to use as extended address, the block address based on Z80 area.

After two Z80 out instructions you could have this.

Area   Z80                   extended memory
          A15    A14        Ea17    Ea16   Ea15  Ea14
0           0       0             0         0          0        0 
1           0       1             0         0          0        1
2           1        0            1         0          0        0
3           1        1            1         0          0        1

Note that you are using two 273 to store the above data, one out instruction sets data for two areas.

The data in above table states
Z80 area 0  0-16k     = expanded memory block 0 = 0-16k          = rom 0-16k
Z80 area 1  16k-32k  = expanded memory block 1  = 16k-32k     = rom 16k-32k
Z80 area 2  32k-48k = expanded memory block 8  = 128k- 144k = ram 0-16k
Z80 area 3  28k-64k = expanded memory block 9  = 144k--160k = ram 16k-32k

From the Z80 you have 32k of rom starting ar address 0 & followed by 32k of ram
This is the same as if you just had two 32k memory chips connected to Z80.
To get to this state the Z80 did two Z80 Out instructions with the instructions in 0-16k if rom

Org   0 H
; do some initial boot stuff

; then set up memory
  out 273-0, 10h    ; set area 1 bits to block 1   set area 0 bits to block 0
  out 273-1, 98h    ; set area 3 bits to block  9  set area 2 bits to block 8
: now you can set the SP  and continue booting

===============

The switch in the drawing is letting you use two bits of Z80 to get 4 bits to be used as the high bits of the extended address.

======
Things to look at
The switch is doing the decoding of the Z80 area.

  Say you wanted
    0-16k to be rom always at same rom address
   48k-64k to be ram always at the same ram address.
  And want to switch the center two 16k blocks.
You would need memory chips for the two fixed areas & more memory chips for the switched memory. You could use a two way switch in this case.

If you want the fixed rom or ram to come from the memory chips in the switched memory chip area, you need to add at least one more switch position to get this to happen.
Computers work in binary so a 3 position switch is hard to find, you would end up using a 4 throw switch. You could then strap the inputs of the 4 throw switch so that it gives the fixed address to get the above two fixed areas. And data at the other two switch inputs to select wanted block for that area.
By adding just one 273 chip you have data for  four switched areas. This is what you have in drawing.

If you look at the boxes that hold the expanded address, you should see that a few bits can make a huge difference. Two more bits would let you have a 1M expanded address range.

==========
 74LS670
  As stated in last post, you would have a power up problem using this chip. There is a pin on this chip that will make outputs go tri-state. You could control this pin by using one bit of a 273 that was cleared on power up.
To get this to work you would need pull-up resistors on the outputs of the 74LS670 & need to put power up boot code in the highest block of memory.
Ram would be address in 0-128k, Rom 128k -256k.
The highest block of 16k would then be rom and you put boot code in this block.
At power up Z80 would be running block F code with Z80 using addresses in  0-16k.
With Z80 now running the first steps would be to write good data in the extended address blocks stored in the 74LS670 and then enable output of the 74LS670 by writing to 273

Look at drawing again
When you use 74LS670
Rom and Ram areas are wwapped.
The boxes that store extended address are now four tall and use four Z80 output instructions.
The 74LS670 contains the switch and the data boxes.

Using two 74LS670 would let you have a 4M expanded address range by using 4 output ports. You are probably thinking what would I use it for.
One use would be to use memory that is shared or used by a different CPU.

So memory management is simple

You have something between the CPU and Memory that changes addresses that the CPU can control.

If something does not make sense it could be an error in above.

 
 
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Offline nockieboy

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Re: Z80 memory banking for 128K - MMU design
« Reply #12 on: November 10, 2017, 09:19:38 AM »
Yeah, I'm going to have to go away and think long and hard about what you've written, C - I'm finding it a little hard to follow.  ???

Here's what I've drawn up so far - it's more of a serious sketch of the original hand-drawn plans in my first post, but this one includes a slight improvement in terms of using a 74HCT257, thanks to jm_araujo's suggestion.



The problem with this design is that it just answers my original question - i.e. making area 2 switchable with any bank in the upper 64KB of RAM.  What I need to be able to do, having looked at the CP/M 3 System Guide, is to make areas 0, 1 and 2 switchable.  This adds a layer of complexity that is far beyond my simple electronics knowledge and understanding, unfortunately.
 

Online glarsson

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Re: Z80 memory banking for 128K - MMU design
« Reply #13 on: November 10, 2017, 09:29:10 AM »
What I need to be able to do, having looked at the CP/M 3 System Guide, is to make areas 0, 1 and 2 switchable.  This adds a layer of complexity that is far beyond my simple electronics knowledge and understanding, unfortunately.
Using a 74140 or 74LS670 allows you to map any memory segment (e.g. 16k) to any e.g. 16k as seen by the Z80.
 

Offline C

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Re: Z80 memory banking for 128K - MMU design
« Reply #14 on: November 10, 2017, 02:16:31 PM »
Look at your last design.

You have more bits in the 273 & one more 1 of 2 switches.
This one bit lets you have A17.
When A17 = 0 rom is selected.
When A17 = 1 ram is selected.
You can get this to happen just by proper connection to rom & ram chips.
You now have 8 banks you can swap in to area 2, 4 ram & 4 rom.
This change is a step to removing all the other chips used to swap rom for ram.

Your switch is a 2 throw switch & is selecting normal Z80 or Banked, but banked is only used for area 2 which needs extra logic to select.

You can remove the logic that selects area 2 by using a 4 throw switch!
Two 153 would let you do this. A 153 is a dual 1 of four switch.
By connecting Z80 A14 & A15 to the 153's A & B inputs, the switch it's self will decode the area removing need for area2 select. For now just strap other inputs to proper levels for the fixed addresses like you have with the 257.

Now if you look at 273 you have 4 bits not used. If you used these 4 bits to select the bank for area 0 you could remove all the other logic that selects rom/ram for system.
Area 0 would point to 0-16k on power up and by writing the 4 bits can point to any block of ram or rom.

This leaves 8 inputs to the 153 strapped to a level. By adding one 273 you have bits needed to change these pins and all areas can be banked as needed.

So two 273's and two 153's give you four areas that are bank selectable & you get to remove current logic that selects rom or ram swap. 

You should note that CS for the rom & ram chips selects chip active or disabled/sleep.
If A17 & Z80 MREQ is used for Chip select then Z80 RD & WR can be directly connected to these chips.

Need to look at big picture when thinking about a change.
You locked into changing only area 2 and not looking at total system and a change that would get a better result.




 

Offline nockieboy

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Re: Z80 memory banking for 128K - MMU design
« Reply #15 on: November 10, 2017, 10:18:49 PM »
Look at your last design.

You have more bits in the 273 & one more 1 of 2 switches.
This one bit lets you have A17.
When A17 = 0 rom is selected.
When A17 = 1 ram is selected.
You can get this to happen just by proper connection to rom & ram chips.
You now have 8 banks you can swap in to area 2, 4 ram & 4 rom.
This change is a step to removing all the other chips used to swap rom for ram.

Oh yes, I like your thinking, C. :-+   It would be great to improve on Grant Searle's original ROM/RAM switching design with a reversible system.  By default, his system allows you to switch the ROM 'off' when loading CP/M, but there's no way to switch it back in without doing a cold reset of the entire system.  Being able to switch in any bank of the 128KB ROM would be nice too...

Your switch is a 2 throw switch & is selecting normal Z80 or Banked, but banked is only used for area 2 which needs extra logic to select.

Yes, well the whole Area 2 thing was just my initial thoughts on MMU design, partly because it seemed simple and a good idea at the time, and partly because I was unaware how CP/M 3 likes to have the whole bottom three areas switchable!  I've updated the original post and memory map accordingly.

You can remove the logic that selects area 2 by using a 4 throw switch!
Two 153 would let you do this. A 153 is a dual 1 of four switch.
By connecting Z80 A14 & A15 to the 153's A & B inputs, the switch it's self will decode the area removing need for area2 select. For now just strap other inputs to proper levels for the fixed addresses like you have with the 257.

I like the sound of this. :-+  Will have to look at the 153 and spend some time thinking about what you've said here to make sure I understand how it fits together.

Now if you look at 273 you have 4 bits not used. If you used these 4 bits to select the bank for area 0 you could remove all the other logic that selects rom/ram for system.
Area 0 would point to 0-16k on power up and by writing the 4 bits can point to any block of ram or rom.

This is going to require some :-/O on the breadboard (or at least de-wiring of logic chips for the existing RAM/ROM select circuit), but it sounds like a much more flexible and powerful system. ;D

This leaves 8 inputs to the 153 strapped to a level. By adding one 273 you have bits needed to change these pins and all areas can be banked as needed.

So two 273's and two 153's give you four areas that are bank selectable & you get to remove current logic that selects rom or ram swap. 

You should note that CS for the rom & ram chips selects chip active or disabled/sleep.
If A17 & Z80 MREQ is used for Chip select then Z80 RD & WR can be directly connected to these chips.

Okay, I think I already have a couple of 273's knocking about.  Could I use 74HCT253's in place of the 153's?  I'm dippy about DIPs and want to stay away from SMD for as long as possible - plus the adapters are an added expense when prototyping on breadboard and I'm as likely to solder an SMD to my fingers as I am to the board.  ::)

Need to look at big picture when thinking about a change.
You locked into changing only area 2 and not looking at total system and a change that would get a better result.

Consider myself told off! ;)  Seriously though, thanks for that C - I feel I actually have the outlines of a plan now.  I'm going to spend some time this weekend (hopefully) converting what you've written into a schematic that I'll post ASAP for feedback.  :-+
 

Offline nockieboy

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Re: Z80 memory banking for 128K - MMU design
« Reply #16 on: November 11, 2017, 01:26:34 AM »
Is this going along the right lines, C?  I'm not sure this is even right, but going by your previous comments this as close as I can get.  Not sure what to do with the Y1/Y2 outputs of the 253's, though - do they go to A15/A16 on the RAM/ROM?  How do I select between RAM/ROM with this configuration?

 

Offline C

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Re: Z80 memory banking for 128K - MMU design
« Reply #17 on: November 11, 2017, 01:43:22 AM »
Just think of what you have

A 4 throw switch

so the switch is area decode and you use two chips the get the expanded address buss width.

the two latches are
the memory for the MMU, The storage of what bank in extended address to use for an area

so put bank decoder under area decoder in your drawing as both are area

label four outputs of these as expanded address or extended address

Your data bus  Area & bank
these inputs are Z80 I/O write to selected address
you are writing two areas extended address data (bank) with one output.

ADDED

The output of Switch is A14, A15,A16,A17
As they are not the same as direct Z80 it is a good idea to change the label

EA14-EA17

Yes yes switch outputs go direct to memory are address lines.

The big difference is that you have the ability to change the address mapping
&
The switch takes time to switch so these higher address lines change slower, need to check timing as this can effect memory read/write times
« Last Edit: November 11, 2017, 01:51:39 AM by C »
 

Offline C

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Re: Z80 memory banking for 128K - MMU design
« Reply #18 on: November 11, 2017, 05:24:31 AM »
You should note that all my posts here are same result.
Two 273's and two dual 1 of 4 switches or mux.
I just modified your drawing step by step.

Speed of the switches is important. Faster gives you more time for memory.

Normal Z80 Memory connection.

Most memory chips do nothing when CS is inactive.
Most expect address inputs to be stable when CS goes active.
With CS inactive changes on RD and WR are not used or looked at.
Your memory works like this.

I say most as there are many ways to connect memory and types of memory

So Normal Z80 has RD & WR directly connected to memory. The selected chip will respond to memory cycle.

Memory CS is a combination of Address Valid, which memory chip is to respond & Z80 MREQ

The 138 is build just for this as you can connect one of the enables to Z80 MREQ and if you look at inside logic of chip, some of the enables just turn on the outputs of the chip. This hides all the random states as the address line inputs are changing.
MREQ then will enable output at correct time, removes chip output glitches.

So my good design practice it to use proper chips in correct place and really check the timing & time delays to try to prevent glitches that are very hard to find.

So You have two 128k chips and need a decoder to select which chip based on EA17 & Z80 MREQ

Pick a decoder chip and use it. You have many choices 138, 139 and many others.

Now look at your memory timing.
The data in the 273 is static, not changing on a memory cycle.
The address buss from Z80 starts changing.
The Switch takes time to switch inputs and get proper static output so this adds a delay.
Then Z80 MREQ happens and gets sent to decoder chips.
The decoder chip takes time so you have a delay here also.
The output of decoder chips start the time clock on the memory CS time.

So is address stable when CS of memory chip goes active?
Now keep in mind that for Z80 address starts changing on one clock edge and MREQ is a different clock edge.
It is not hard to add some delay to MREQ.



Look at removing Grant's logic.


Having a Cold reset & Warm reset is a great thing.

U8 is not common in most designs I have seen
  With most designs I have seen MREQ and IORQ are  output enables of address decoder chips.

Looking at the SIO the CE pin would go low(active) when proper address is valid and stable and IORQ is active. U5 is missing a IORQ input to enable pins to make this case.

You could do some tests to verify that the following changes work step by step with the result of removing grant's logic.

1. On U5 connect pin 5 (E0) to IORQ instead of A7
     Test computer all should work fine. You should be able to send/receive via SIO and you should be able to read and write to CF Card with out errors.

2. With change 1 in place, you should be able to move connections to J1 piins 4 & 5 to connect to the Z80 RD & WR in place of U8c & U8D.
    Run tests of #1 again and you should see no problems.

Starting change to add new Memory mapper.

3 You will add a decoder chip and connect it to an un-used output of U5. You will use this I/o address range to control the MMU. When MMU is working properly you can then remove grant's ram/rom logic.
  Add a 138 or 139 chip. The U5 un-used output can be connected to an enable pin or an address input of decoder. One of the enables will be Z80 WR. Connect A0 & if possible A1,A2 to this chip.
You now have outputs that are IO write that can be connected to 273 chips.

4. A quick test  of what you have to this point.
connect one 273 to #3 and use a output of 273 to change input of U8D pin 12.
  heck/verify  that a 0 output of 273 selects ROM chip.
Add software in Z80 to change the bit in 273. leave old software for grant's in place.
    Run #1 tests.  Should work for grant's logic or 273 output.


Keep in mind that a MMU goes between CPU and Memory.
This MMU uses a few I/O writes to control it's operation.
You might want to put this circuit on a separate breadboard.

A step by step change for memory is harder to do. You need all four chips connected properly with some changes to memory chip selects & software.
 
5. with U6D connected to grant's logic, build MMU circuit.
   Do NOT connect switch outputs yet.
   You will need to write software for MMU. Do this by adding software leaving grant's software.
   On power up you will have all ROM so use software to make MMU select
   0-16k rom for area 0 and ram for other areas.
   Where software changes to all ram, add code to change MMU (the 273 data) for all ram. Leave grant's software in place.
   Check proper data is written to the two 273's
   Will need to use scope to verify that Switch outputs is working.


6. Now that you have this much working and tested as much as you can, change memory selects so that MREQ is used to control CS of memory chips and EA17 is also used.  Rom = 0-128l Ram = 129k-256k when looking at the expanded address.
If you need logic to do this I would use a decoder chip.
Connect MMU outputs to memory.

7. Test it.
    with proper software for MMU you should see no change from what you have now.

8. Here you can remove Grant's logic that is not used.

You should note that for CP/M3 & TurboDos you can start the computer running CP/M2 and run a command to change to new system.
This makes testing the software changes needed for new OS easer.
   


You can use the 74ls670 if you want to.
The cmos versions of this chip are very slow, you need LS or faster.
If you order this chip 74LS670, I would get 2 or more.
You will also need pull-up resistors for outputs of chip.

The basics are the same as using 4 chip MMU
The 74ls670 will use 4 Z80 out addresses instead of 2.
Rom/Ram is swapped in extended memory
One step that you might have trouble with is loading boot code into the highest 16k block of Ram.

Something you might want to think about. The Z80 can program the ROM you are using.
 

Offline jaycee

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Re: Z80 memory banking for 128K - MMU design
« Reply #19 on: November 11, 2017, 07:19:07 AM »
Worth looking at the design of the ZX Spectrum 128, which banks memory in the top page of the Z80's address range. It's quite a simple mechanism.
 

Offline nockieboy

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Re: Z80 memory banking for 128K - MMU design
« Reply #20 on: November 11, 2017, 08:49:34 AM »
Worth looking at the design of the ZX Spectrum 128, which banks memory in the top page of the Z80's address range. It's quite a simple mechanism.

Yeah, that's no good for me as I want to make my computer compatible with CP/M 3, which requires the bottom two thirds of RAM to be switchable.  I noticed some interesting stuff going off with the AY sound chip in the 128's schematic though - looks like they control the keyboard and RS232 through the AY's IO ports..

Looking at the SIO the CE pin would go low(active) when proper address is valid and stable and IORQ is active. U5 is missing a IORQ input to enable pins to make this case.

Yes, Grant's design is missing the IORQ input to U5, but I've added it to mine so the 138 only responds to proper IO requests.
 

Offline Jr460

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Re: Z80 memory banking for 128K - MMU design
« Reply #21 on: November 11, 2017, 09:33:54 AM »
I didn't read all the post in this thread in detail, so maybe I'm stating something already discussed, sorry.

Many years ago, before CP/M 3.0, when 2.2 was king, I worked on a MP/M system.  It was multi-user CP/M and if you wanted it work well you needed bank switched memory.  Like 3.0 the top part of memory was not switched.

(If think about it this is way most modern virtual memory OSes work.  System space for the OS and devices is the top half of the virtual address space and process private is the lower half.)

The system I worked on was S100 buss based and the memory cards were 48K each and had a dip switch that set the IO port number that the card would listen to to turn it on or off.  It was up to MP/M to keep track and only have one card enabled at a time.  One card in the system had a full 64K, and the lower 48 could be disabled again with an OUT command.

Maybe look for old schematics of those S100 boards and see what they did.  At least you know CP/M 3.0 will work with with that method of memory management.
 

Offline nockieboy

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Re: Z80 memory banking for 128K - MMU design
« Reply #22 on: November 12, 2017, 03:01:03 AM »
Okay, this is where I'm at with the schematic based on C's discussion above (ignore the labelling for ~AREA and ~BANK - they're just IO select lines from the '138.)



I'm flying blind a little bit as I don't fully understand how this will work - or even if it WILL work - I've just thrown it all together based on C's posts.  You don't want to hear excuses, but I've had a busy day with the family and now have a splitting headache, so I'm struggling to work out how and if this circuit works at switch-on.

At power-on, the default state should be:  ROM - 0000h-3FFFh, RAM - 4000h-FFFFh.  The ROM should be able to be switched-out with an IO call so that the entire 64KB memory space is RAM, for CP/M to run.  This is handled by EA17 in the schematic.

Now bearing in mind I don't really know how this is supposed to work - aren't I going to have to set a default value in the latches to ensure the above default ROM/RAM memory state is enforced?

If no banking is enabled, how does A14 and A15 get passed through to the RAM/ROM?  Do I need to connect A14/A15 to 1C0/2C0 on the 253 that outputs EA14 and EA15?  This circuit just feels incomplete...  :-//

I didn't read all the post in this thread in detail, so maybe I'm stating something already discussed, sorry.

No need to apologise! Welcome to the discussion, Jr460!  :D

The system I worked on was S100 buss based and the memory cards were 48K each and had a dip switch that set the IO port number that the card would listen to to turn it on or off.  It was up to MP/M to keep track and only have one card enabled at a time.  One card in the system had a full 64K, and the lower 48 could be disabled again with an OUT command.

Maybe look for old schematics of those S100 boards and see what they did.  At least you know CP/M 3.0 will work with with that method of memory management.

I'll have a hunt for S100-related schematics then - there seems to be a couple of sites relating to S100 computers that I've come across previously.  I feel I'm getting somewhere with my current design, though and if I can complete it, it'll be extremely versatile as it will allow me to map ANY 16KB bank of memory space to ANY 16KB bank in physical RAM or ROM.
 

Offline Ian.M

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Re: Z80 memory banking for 128K - MMU design
« Reply #23 on: November 12, 2017, 04:08:50 AM »
At powerup, after /RESET is released, both latches will have '0' on all outputs.  A14 and A15 will therefore be ignored and the low 16K of the ROM will be mapped to the whole address space, repeating four times.  By writing to the latches you can map any bank of RAM or ROM at any 16K page in the address space.  However you would do well to rearrange the input lines to the multiplexors so EA14-EA17 for a single page are controlled by four bits on the same latch, otherwise it will be difficult to switch mappings without smashing the mapping for the page that is currently executing.

However this seems over-complex.  Personally, I'd use a 74HC670 4x4 addressable register file to expand the addressing.  It does *NEARLY* everything the above circuit does in one chip.   That would give you a separate port write to control each page, with two bits in the data selecting the page and four bits selecting the bank, but would need the addition of a flipflop driving its /RE pin (that controls its output tristate capability) set by /Reset and cleared by an unused data bit decoded at the port address+ 10K pullup or pulldown resistors to set the default powerup mapping.
 

Offline nockieboy

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Re: Z80 memory banking for 128K - MMU design
« Reply #24 on: November 12, 2017, 07:06:55 AM »
By writing to the latches you can map any bank of RAM or ROM at any 16K page in the address space.  However you would do well to rearrange the input lines to the multiplexors so EA14-EA17 for a single page are controlled by four bits on the same latch, otherwise it will be difficult to switch mappings without smashing the mapping for the page that is currently executing.

Ah, right - how should I rearrange the multiplexer input lines to achieve that?

However this seems over-complex.  Personally, I'd use a 74HC670 4x4 addressable register file to expand the addressing.  It does *NEARLY* everything the above circuit does in one chip.   That would give you a separate port write to control each page, with two bits in the data selecting the page and four bits selecting the bank, but would need the addition of a flipflop driving its /RE pin (that controls its output tristate capability) set by /Reset and cleared by an unused data bit decoded at the port address+ 10K pullup or pulldown resistors to set the default powerup mapping.

Okay, I'm nearly persuaded - I'll see if I can get a basic understanding of how it works from the datasheet and throw a schematic together to see if I can pull this off. 
 


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