I have previously looked for the mysterious PC program but I think that it was never released outside Philips, looking at the firmware I can see that as well as the documented commands there appear to be "CF", "DW", "EM", "EO", "EX", "PF", "QC" and "QF" but what they do or what parameters they might take is anybody's guess.
I know a guy who has the software but is very tight about it and will not make a copy, although these instruments are now 20+ years old. He was the chosen one that continued the official service for "PM" instruments, when Philips stepped out of it. May be one of these days I will convince him to make a copy and hand me the manual.
Given that I've been looking at the CPU card & firmware on these 'scopes again and also have been playing with a cheap USB LA (one of the 8ch 24MHz saleae clones) I find my myself motivated to look at reverse engineering the firmware once more.
The 8ch LA is not really enough but it piqued my interest enough to get a better USB LA - this time a 16Ch 400Mhz DSLogic Pro (probably a clone given the price) which is plenty to start by mapping the address decode PAL.
The PAL is arranged with 10 inputs A
14 and A
15 from the CPU, 4 lines from CPU port 1 labelled SELA
15 - SELA
18, two further bits from port 1 labelled PROGENLT and TEXTENLT, the CPU INST output and EA
It generates chip selects for the RAM and two ROMs, address bits 15-17 for the ROMs (A
0 through A
14 for both the ROM & RAM come from the CPU), and some further select signals (IOCS and TXTCS).
This the basic scheme would seem to be to split the 64k CPU address map into 4 16k chunks and to expand the ROM address space to 20 bits. However as the ROM & RAM chips see A
0 - A
14 direct from the CPU they are probably mapped in 32k chunks. However as "INST" is an input so RAM could be mapped at the same address as ROM, or they could use that to map I/O space over ROM.
1024 input combinations was always going to be too much to map by hand but a 16ch LA would be fine to cover most of the inputs (only really need the clock and the final carry out so I know when the count rolls over to all bits 0) and 8 outputs - all I need then is a clock signal and a few 74xx191's (which I know I have in the parts bin) to generate the inputs.
I'll see if I can do that this weekend (if the new LA turns up).
The "A" and "B" boards are completely different - a PLS 173 is used, the address inputs go from A
12 to A
15 so potentially there is much finer grained control over the memory map (though the ROM & RAM still have to be 32k contiguous) and the outputs do not include the expanded address lines for the ROM, just various chip selects.