if in the future you'll be playing more with 3245A internals, would you mind probing XMSP/XMSN and XSLP/XLSN signals? I'm curious what is the scheme employed there, PWM or pulse density, what PWM frequencies (as we have 200 Hz and 194 Hz low pass filters), center aligned and complementary PWMs or what.
I'm analyzing their PWM DAC circuit and it is a bit cryptic due to the sheer number of analog switches involved in all the modes (and probably selftests). In HiRes scenario LSB PWM is connected with the MSB via RP100A resistors ?, then through low pass filter, but the LSB has its own path and LPF as well and both of them can be switched to the common DAC output. In these scenario the HS DAC seems to provide DC offset. In high speed scenario the LSB+MSB DAC seems to provide DC offset (called vernier)?
Very interesting device indeed. Maybe with HV option and LTZ1000 it could as well replace these bulky EDC voltage/current standards.
What INL can one expect from such PWM DAC? Linearity is not specified in the 3245A datasheet AFAIR, but if they say it is 6.5 digit I would assume 1 ppm.