$r + 4C + 1 FPGA == Radio Challenge

[antti]

As subject, the challeng is to use 8 passive components, 4 x R, 4 x C and one FPGA (any Xilinx 7 series is ok) to create a Radio receiver with frequency coverage over 500mhz.

Challenge announcement at Xilinx blog https://forums.xilinx.com/t5/Xcell-Daily-Blog/Antti-s-Trenz-Challenge-Build-a-500MHz-radio-receiver-with-4/ba-p/757338

[daveshah]

What a funny coincidence, given my project only a couple of days ago

[antti]

Yes, I read your GTx but honestly, I found your post LATER, and its totally different approuch!

[daveshah]

I wasn't implying anything - just thought it was interesting. This certainly looks like a better approach for lower frequencies and will be much more sensitive I'm sure. I'm definitely going to have  a play with it as I'm interested in SDR type stuff.

[antti]

yes its pretty cool, the technical details will get explained and published as soon as the challenge is completed..