2-meter class E with a cheap GaN FET?

[mark03]

This is a question for blueskull or someone else with GaN design experience.

Mostly out of idle curiosity, but also with a potential application in the back of my mind, I was curious if these new GaN transistors could be used in a class E amplifier at VHF.  The cheap ones at Digikey are from EPC, aimed at high-frequency SMPS.  See e.g. the EPC2038:

http://epc-co.com/epc/Portals/0/epc/documents/datasheets/EPC2038_datasheet.pdf

(EPC actually sells a class-E amplifier demo board, optimized for much lower frequencies around 10 MHz.)

I tried some simple calculations for the EPC2038, with an eye toward a QRP (low power, 1/2 to 1 watt) transmitter at 146 MHz:

With 3.3 volt gate drive, total gate charge is 30 pC, making the effective C_gate 30e-12/3.3 = 9 pF.

For efficient class E operation, total rise+fall time is supposed to be no more than 30% of one-half cycle of RF (source:http://www.norcalqrp.org/files/Class_E_Amplifiers.pdf).  At 146 MHz, that's 1.0 nanoseconds, so we are looking at 500-ps rise and fall times, with current C*dV/dt = 9e-12 * (3.3/500e-12) = 60 mA.  If we take the rise/fall time as 4*R*C_gate, then the required R (gate-drive impedance) is 1e-9 / (8*9e-12) = 14 ohms, of which the EPC2038 gate resistance accounts for 4.8 ohms.

So far this doesn't look too impossible, except... where do you find a 146-MHz square wave with 500-ps edge rates?  Some high-speed logic families, like Fairchild's UHS, apparently have edges which are almost that fast.  Can you just parallel several gates?  Maybe an approach like http://www.wenzel.com/wp-content/uploads/hcmos.pdf except with paralleled gates, driven from a lower-frequency oscillator or MCU pin, e.g. 20.8 MHz * 7 = 145.6.

So, tell me what I'm missing 

[JohnG]

You might be able to use a NB3L553 https://www.onsemi.com/pub/Collateral/NB3L553-D.PDF from ON Semi, and parallel all 4 outputs. I recommend using the DFN package since you really want to minimize inductance. Since the EPC parts are already in a chip-scale package, the DFN layout should not present any additional issues. EPC has some articles on layout of the power loop for half-bridges, but you can apply the same principles to the gate loop. Don't forget that the gate drive bus cap is part of the gate turn-on loop. You would have to put a lot of UHS gates in parallel to get the same output impedance, probably 8 or more, and the layout would be a nightmare.

The ISL55110 http://www.intersil.com/content/dam/Intersil/documents/isl5/isl55110-11.pdf might be worth a shot, again paralleling the outputs. The problem with this is that the min pulse width is spec'd at 6 ns, and this would be too long for your application. Maybe the part does better than the spec, but I have not tried.

Edit: I don't recommend using a 3.3 V gate drive. 4.5 is the recommended minimum. The ON Semi chip can do that, and you will get faster turn-on.

Hope this helps.

John

[mark03]

Thanks, I hadn't thought to look at clock chips.  Unfortunately, I was only planning for ~ 0.5W output power, so using the NB3L553 will knock the efficiency way down.  (Its rise time is specified into a 15-pF load, so I would think one output would be enough?  If it came in a 1x or 2x package, rather than 4x, that might save some power.)  Maybe this is telling me I really need a GaN device with even less gate charge.  I looked at an "RF" GaN datasheet and saw that the input capacitance was indeed somewhat lower.  Those are expensive parts!  ($30 and up, up, up)

Why 3.3V?  Actually it would be more like 3.7V.  The idea behind this was an ultra-light balloon beacon running off a tiny Li-ion cell.  I wondered how light one could make a telemetry transmitter with MCU and GPS.  I think ~ 8 grams is achievable, maybe a bit less.  Class E is nice because PSK is easy, and the efficiency is [potentially?] good.

One question I have about paralleling CMOS outputs regards their output capacitance.  If each CMOS output adds to the total capacitance of the gate-drive node, how do you know which effect "wins":  more capacitance => slower or constant rise time, versus greater drive strength => faster rise time?  The two effects seem to be at odds, and it's not obvious to me that tying outputs together will always result in a faster edge.

[T3sl4co1l]

Only 0.5W?  Why not use the clock generator directly?

Alternately, it would be a swish for linear mode -- you can run that class AB with plenty of heat dissipation to spare, if you've designed the thermal budget properly.  Any more (into class C or E) is just icing on the cake.

The general lesson is: don't try to use power switching devices at power levels they're really not suited to.  At low frequencies, you don't have much drive power to worry about (power gain is well over 40dB in most applications), so the mismatch can be pretty wide, but as you increase frequency, or tighten requirements on drive loss (say for an extremely high efficiency converter), it becomes just as important.

Are GaN FETs really that much cheaper than 1/2W class BJTs or LDMOS?  Or MMICs, for that matter!

Tim

[mark03]

Sorry for the necro-post, but I was searching on this same topic today, discovered my old thread, and realized that I'd lost track of it somehow    I wanted to follow-up on some of the responses for my own edification, otherwise I won't have learned much from posing the question in the first place.  Thanks in advance for indulging my curiosity.  I'm a licensed ham and a EE, but my experience is mostly in signal-processing theory and embedded systems.

So, as a reminder, this started off as nothing more than a thought experiment, although I suppose actually building something is still a possibility.  The design exercise was to come up with a ~0.5W VHF CW balloon-borne transmitter, MCU controlled, capable of running a frequency-shift keyed mode like FT8 (https://en.wikipedia.org/wiki/WSJT_(amateur_radio_software)#FT8).  It would be a single-use device (cheap), capable of being lofted by a single latex helium balloon (single-digit grams including battery and wire antenna), with the best possible power efficiency and very low sleep current between transmissions.  My idea had been to drive the output stage, whatever it is, from the "MCO" (auxillary clock output) pin of an STM32, using the internal PLL to multiply up from a VCXO which would be connected to the MCU DAC for FSK.

Only 0.5W?  Why not use the clock generator directly?

Yes, I'd considered hanging a filter off of a digital output.  But conceptually (remember I am not an analog-design guy) it seemed to make sense that if my signal source is a square wave, I could use that to drive some kind of resonant switching amplifier, with better efficiency than I'd get by just filtering out the square-wave harmonics and connecting an antenna.

BTW, EPC2038 won't work properly with 3.3V driving. You need at least 4.5V.

Help me understand this.  Is it because of part-to-part variation, specifically the spread in Vgs(th)?  If I hand-selected for a device with the "typical" (or better) Rds(on) curve, 3.3V-drive would be fine, correct?  And roughly 50% of the parts should be typical or better?

30pC*3.3V=100pJ
100pJ*150MHz=0.15W
Doesn't look good for a 0.5W amplifier.

This is off by a factor of 10; the input power is only 15 mW, not 150 mW.  Once you account for added capacitance at that node it will obviously be higher, but > 10 dB power gain seems possible unless I am mistaken. 

The problem remains how to get sufficient drive current to make this work, without burning additional power which will destroy the overall efficiency.  Actually, I was thinking it might be wiser to target the 6m band instead, which could improve the situation.

[iMo]

My idea had been to drive the output stage, whatever it is, from the "MCO" (auxillary clock output) pin of an STM32

Not knowing which stm32Fxxx you plan to use, but do mind the MCOs are frequency limited, to something like 100MHz max..
PS: Double check the stability of the STM32's PLL output frequency. Based on my measurements in past the STM32's PLL may drift in a sawtooth shaped manner dozens of Hz.

[mark03]

Not knowing which stm32Fxxx you plan to use, but do mind the MCOs are frequency limited, to something like 100MHz max..
PS: Double check the stability of the STM32's PLL output frequency. Based on my measurements in past the STM32's PLL may drift in a sawtooth shaped manner dozens of Hz.

Thanks, saw that in the other thread.  Yikes
My scratch design used an STM32L0 in QFN32.  But I have since reviewed my old notes, and realized that I was not going to use the PLL after all.

The idea was to run the MCU straight off of a 16.9344-MHz crystal, drive that out of MCO, and use this clever multiplier idea: http://www.techlib.com/files/hcmos.pdf  with UHS logic (NC7SZ__) to pluck out the 3rd harmonic at ~50.8 MHz.  Hopefully at 6m the UHS logic by itself will be an acceptable gate driver.  With this scheme, BPSK is easy (using NC7SZ86 XOR for the driving gate) and narrowband FSK can be achieved with the MCU's in-built DAC and a varactor crystal-puller.

Maybe I should get off the couch and actually prototype this

[David Hess]

I would probably try using step recovery to sharpen the edges driving the GaN FET, maybe a non-linear transmission line used for comb generation?

[JohnG]

There is this new gate driver. It's not the cheapest, but it's not crazy expensive, either: http://www.ti.com/product/LMG1020/description.

It is very fast!

John