Hi,
Our system should be capable to hop between 6000 channels in 4.4 - 5 GHz band at 1000 hops/sec rate, here, the channels are separated by 100 KHz. Hopping can happen from 1st channel (at 4.4 GHz)to the 6000th (at 5 GHz) channel and we are expecting that the settling time of the device for the new channel should not exceed more than 20us...
AD9361 have fast lock profile method feature by which we can create synthesizer coefficients for 6000 channels. During the application is running, the user program can load the respective coefficient to the synthesizer register in AD9361 when we want to hop to that frequency.
As per AD suggestion, one can achieve this less than 20us settling time by the above method only if frequency separation between the new hopping frequency (let us say 4400.1 MHz) and last calibrated frequency( calibrated at device initialization, let us say 4400 MHz) is less than 100 MHz. If it is above 100 MHz (that is the last calibrated frequency is 4400 MHz and the new hopping frequency is 5000 MHz ), the device has to perform DC offset calibration, TX quadrature calibration and Rx quadrature for that frequency(5000 MHz). Since these calibrations take at least 30 to 40ms, we are violating our 1000 hops/sec.
Please suggest...
Thanks,
Muthu