Discrete vs. IC MOSFET Characteristics

[beeboopbeep]

Hi everyone,

I'm trying to build a circuit with discrete MOSFET components as I would when designing circuits on an IC (e.g., using Cadence to design and build IC schematic and layout) for RF applications but I'm noticing something I can't explain.

I was planning to use RF MOSFETs like this one here: http://toshiba.semicon-storage.com/info/docget.jsp?did=17964&prodName=3SK291

If you look at the DC characteristics (Page 3, first figure), and if you use the saturation current equation I_D = (1/2)*k_n*((V_gs - V_th)^2) for different V_gs values, you notice that the value of 'k_n' differs significantly! I calculated for k_n with known I_D, V_gs, and V_th from the figure. My initial thought was maybe this is because V_th changes for different V_gs and I_D but the source is tied to the body in this circuit which means V_th should stay relatively constant with no body effects.

I noticed in the datasheet that V_th will vary as indicated on the first page (Gate 1 & 2 cut-off voltage values) but I don't understand why this is the case since source is tied to body. There are clearly some second order effects that I am unaware of and was wondering how would one calculate the V_th for various DC conditions for a discrete component like this?

[T3sl4co1l]

Yeah, literally no one uses that toy of an equation.

Even Ebers-Moll is out, in the real world -- at least, for BJTs, you're likely to have encountered the Gummel-Poon model in a typical EE curriculum (if not work with it much, directly).  Which is the more-or-less standard model used by SPICE.

AFAIK, practical MOSFET models are all much more complicated than this, and so you really only encounter them in SPICE: numerically, not symbolically.

Some detail here: http://nitkkr.ac.in/docs/MOSFET_LEVELs.pdf
LEVEL 1-3 models use KP, for varying reasons, mostly with a lot of tweak parameters to account for behavior and geometry of real devices, and parasitics (resistances and capacitances).  The tweaks get more numerous, and the models more advanced, as you go up in level (more or less).

A lot of general models available, are in levels 3 and 6, good enough for board-level work; BSIM and EKV are the most accurate (and rich), used by real foundries.

But, good luck getting example models, they're tightly controlled, proprietary!  But, if you [or your employer or school] can afford Cadence IC design tools, this is probably no problem.  That does leave the question: why haven't you been introduced to SPICE, and the fab's models, yet?  You may want to ask!

Tim