Half-decent diy RF generator utilizing AD9951 - an idea

[yl3akb]

Well, after spending a bit on google, it seems the calculation concepts may not be that different.

Based on this PDF I have found: http://www.imst.de/itg9_1/vortraege/oktober2001/koenigsmann_folien.pdf

The noise floor (noise power) at normal temperature is -174dBm/Hz.  Fine, I get. But how do I calculate the noise floor?  I need a say 160MHz of bandwidth, that would mean I need to add 10log(160E6) = 82dB to that -174dBm figure. But wait - the amplifiers bandwidth is not limited - at least the schematic I came up with does not limit the bandwidth intentionally. Is that a problem? As in this case, the amplifier would work well above 2 GHz. That would result in a figure of like 97dB (considering like 5GHz BW), instead of 82.   What to do with this?

Then there is the noise figure of the amps. The combined figure of the two is NF = F1 + (F2-1)/G1 = 2.34 + (2.63-1)/17.8 = 3.86dB noise figure. (Look at the slide 14 of the PDF above, I am not sure if they calculate the gain factor correctly - as 20dB amplifier neither does have a 100 times voltage gain, neither a 100 times power gain. A mistake?*)

So now we have -174dBm + 97dB + 3.86dB = -73dBm noise floor. Doesn't sound the greatest result of all times, but well.. the cascade has 28.5dB of gain on a bandwidth in GHz digits. And also the output signal I want to be on the scale of +20 downto 0dBm or so, meaning resulting SNR from 93dB to 73dB.

Those 90+dB SNR looks good, but those 73 not so much, but it may be sufficient for an application where the expected SFDR is like 65-70dBc.

Or have screwed somewhere? What about the bandwidth? How should I calculate that?

//EDIT: *Have verified from multiple sources, the cascaded NF calculation in that presentation seems correct. Verified the calculation on this website, guesssing Pasternack should be very reasonable to be trusted: https://www.pasternack.com/t-calculator-noise-figure.aspx It came up with the same value of 3.86dB.

I dont think that You can just assume that noise floor at the input of amplifier cascade is -174dBm/Hz or 290 K. AS9951 datasheet shows some spectrum graphs with 3 KHz noise floor of ~-85dBm (I assume that DDS noise dominates in those measurements), which is -120dBm/Hz or 54dB larger than 290 K or 73*10^6 K! The point is that in this case You can not simply add noise figure like that because NF is defined at 290 K input noise.

For example:
You got NF of 3.86 dB, this means that amplifier cascade adds 415 K noise to DDS noise (73*10^6 K) at the input. This means that amplifier worsens SNR only by 10*log((415 + (73*10^6))/(73*10^6)) dB which is absolutely nothing.

Other example:
Assume You got 60 dB attenuator. Its NF=60 dB, so it adds noise of 290*10^6 K at its input. Now SNR will be worsen by 10*log(( 290*10^6 + (73*10^6))/(73*10^6)) ~ 7 dB, which starts to get noticeable (but still nothing in my opinion)

[Yansi]

Inductors still not chosen (shame on me, I know), but a SCH + PCB is done.

Schematic below in the attachments. You can do a sanity check of it or hate it loud, or maybe both. It is somewhat more complicated than originally wanted it too, but after all, there are not so many things in there:

Schematic description:

(Note: Some of the values in the schematic are missing now, will be calculated later. This is just for a sanity check.)

The RF chain consists of an input pad, followed by the Macom FET attenuator and two amplifier stages.

The Macom FET attenuator requires negative voltage for operation. I hate to make aux negative voltage rails, hence the slight hack of the device (I think it will be good enough for the frequencies of interest here). The device ground is lifted using R10, R11 divider to a voltage slightly below +5V. D2 is a protection against the application of positive voltage to that device.  Control voltage is applied through R14.

Please check me: The FET attenuator has a kind of anti-intuitive control voltage characteristic. 0V control voltage means maximum attenuation, while negative -3V means minimum insertion loss, fully open.  Therefore 0V at the IC7B amplifier output means minimum attenuation (IC2 at full negative voltage), while positive voltage at the IC7B means zero voltage at IC2, hence full attenuation. The voltage output of IC7B is proportional with the attenuation. 

Based on the above polarity of the control loop was established. IC4 generates more positive voltage for higher RF amplitude. If the amplitude detected is higher then the setpoint from DAC IC9, the output of the IC7B servo must go up and the control voltage of IC2 must go towards zero (bigger attenuation).

The log detector is connected directly to the output through a about 20dB pad. IC2 log detector provides 0V for zero RF input, but we need it to provide zero volts for certain RF level, and amplify the slope of 25mV/dB to a higher level, as we will operate only within a 20dB range. IC7A amplifies the output of the IC4 AD8307 log detector to a suitable level, while R30 shifts the output of IC7A down.

IC10 makes for a window comparator with added hysteresis, that watches the IC7B output and determines whether the IC7B is out of range, meaning the RF output is unleveled.

The rest is just a power supply of +8 for the RF amplifiers (and the comparator IC10) and +5V for the control circuitry, including a 4.096V reference IC11.

The purpose of IC8 is to store calibration data of the output level versus frequency.  It would be better to use an SPI memory there, as there is already SPI present for the DAC, but I could not find any such suitable one with a write protection pin. The 24Cxx is just a cheap and good enough solution for it.

Regarding the PCB: Nothing too exciting there. Layout may be good enough for the girls I go out with. (Wait... there are no girls! So hopefully it will work at all) Made to fit an of the shelf tin shield box. Hopefully I can fit that in with both the angled IDC connector and those SMAs (I usually solder them to the tin from the outside).

Thanks for checking the schematic and/or PCB.

[Yansi]

Of course there is an error! Who spots it first?  (Hint: IC10).

Now fixed.

//EDIT: Another errata: The 20dB pad for the AD8307 goes through the coupling caps. I think it will be way better to DC couple the attenuator and AC couple the AD8307 to it. This way the caps won't have that much influence on the attenuation of the divider. The input of the AD8307 is rather high impedance (~ 1k+2pF). This mod will increase precision for sure.

Corrected schematic here:

[cdev]

This DDS looks interesting..

[xaxaxa]

This DDS looks interesting..

That's not a DDS, just a synthesizer chip; unfortunately the adf4351 only goes down to 35MHz, and the more common (cheaper) adf4350 only 137.5MHz. I have been looking for synthesizer chips with lower frequency limits for a long time, so tell me if you see one that can go down to <10MHz.

[phenol]

i do remember seeing a similar TI part that could go lower (and higher) in frequency.
You can easily divide down 35-100MHz to any lower frequency you need with commonly available parts...but those frac-n spurs don’t look great, especially with a wide-band loop filter in place

[Yansi]

Yes that is not a DDS, that is an integrated PLL + VCO. There is one interesting chip from MAXIM, that has even widest range but for half the price of ADF4350 (even when bought from reputable source, not china): Have a look at a MAX2871 (23MHz to 6000MHz). But I'd leave this out of this thread for now.

As noone is complaining about my pcb/schematic, I will send it manufactured too. 

[phenol]

why don't you at least test your attenuator setup on a 2-sided cu clad board by cutting out pads with an exacto knife?

[Yansi]

Simple: First I do not have any of the key components, except the AD8307 log detector and MAR-3 amplifier. While waiting for components, I have spent the time to design a proper PCB. And second, I want the ALC block as a more permanent one for my lab. It might come handy for future experiments. Is there anything wrong spending the time to do it properly?

[phenol]

nothing wrong--except for your doubts how to make it work without the negative bias the datasheet suggests and the likelihood of multiple board re-spins. If you can get them made cheaply, then i guess that'd be ok. The DDS portion of it should at least spit out something of a signal so you can use it as a signal source for testing the other stuff

[Yansi]

Well to achieve a negative voltage over a component, one can float it's ground of course, which is what I did exactly. Both ground pins are lifted using a resistor voltage divider to +4V and generously decoupled using three 100nF caps. Yes, this adds inductance to the ground connections, but that should be of not much issue, we are not talking here about GHz range or high attenuation either.

I only find the datasheet of the attenuator a bit incomplete in that regard of not providing the current needed to operate the device (or I could not find it  ) or if that device needs any other special treatments in circuit. I even couldn't find any evaluation or reference application schematic for this part on the manufacturer's website. So I kind of guessed a bit here and there, hopefully not too wrong.

If I haven't mentioned - both PCBs for the DDS and the ALC are currently being manufactured. The DDS is at a local PCB house, the ALC was sent to ALLPCB, because the local PCB house does not offer low quantity manufacturing on 0.8mm substrate. (Yes a thinner PCB, used a microstrip for the RF path this time).

So let's see which one will be delivered first. ALLPCB shoud be fast, right? So have they told me

[Yansi]

So I'll just continue my monologue. ALLPCBs have arrived today, however my stupid moron friend forgot to send the DDS board manufactured, so another week of delay now introduced. Doh! 
And still waiting for the Mouser components, but they should arrive tomorrow.

[Yansi]

Yet again continuing the monologue.

Power supply chain working. Got 8V, 5V and 4.096V reference.   DAC and E2P memory soldered, so is part of the RF path: attenuator and the first RF gain stage.  Unlevel detection window comparator working too.

Now I need to get it to a suitable lab so I 'd be able to verify the functionality of the FET attenuator.

Still waiting for the SGA6389Z amp to arrive, I could possibly solder the MMG3H21NT1 in there, I got three of those available now.   Lost the bag of AD8307 somewhere, need to find those or order new ones and continue with that. 

[TheUnnamedNewbie]

Looking good, curious to see how it goes once you get the remaining parts of this part installed!

[Yansi]

While waiting for AD8307 and the SGA6389Z, I have measured the attenuation as a function of control voltage - the voltage at the IC7B output.

What came a bit surprising is that the maximum achievable attenuation is larger, then specified in the datasheet of the MAAVSS0006 part. That is of course positive result.  Measurement was done at ~100MHz.
That means the "voltage shift hack" is working absolutely fine, as predicted.

It would be more interesting also to measure the maximum attenuation as a function of frequency - but as I do not have currently any other RF source (obviously, I am just building one), I can not measure that, yet. Maybe I will sneak into the university lab on Monday to measure that.   

[TheUnnamedNewbie]

Maybe I will sneak into the university lab on Monday to measure that.   

Depending on what your relation ship is with the PhD students or such (I don't know your function in the university, ie, are you a student/staffmember/etc), ask them about it. Around here, there are some that love making measurements, and will gladly take any half-decent reason to play around with the VNAs for a day. (Lets face it - if you have a lab full of fun toys high quality test-and-measurement gear, you would love to use it all the time desire verifying it performs well on a continuous basis)

Regarding the attenuation: keep in mind that at high frequencies, it will likely get bigger at the low end (because losses become more and more significant) and lower at the high end (because capacitive leakage and coupling becomes more and more significant).

Exciting to see first measurements!

[Yansi]

I know that attenuation will decrease with the increase of frequency. The datasheet suggest this for the MAAVSS0006 part:



We only care about the orange region I have marked there, as the AD9951 can go only up to 160MHz maximum. But because the AD8307 log detector can work up to 500MHz, I am kind of tempted to try to characterize the ALC unit all the way up to 500MHz and may be a bit beyond, as the AD8307 can demodulate even way after 500MHz.

The main measurements I am most curious about are the measurements of the minimum-maximum input levels the ALC unit will be able to still work with to achieve the desired output of +13 down to -7dBm.  I.e measuring the minimum input level to still achieve +13dBm output and measure the maximum input to achieve -7dBm output.  The input then has to be within these two curves for the ALC to level the output.

I am looking to see at least 10dB gain reserve in the full range, which should be enough to cover for DDS filter output variation and other stuff happening.

[Yansi]

Another random shriek:  I have found a bag of AD8307.    Soldered it in, seems it is doing something.  Trying to make sense of the output voltage that it produces.

The output circuit looks like this:



Output from the last amplifier is divided into two parallel branches of 100ohm. One being a voltage divider for the log detector (AD8307), the other branch being a 50ohm output resistor + 50ohm load.

The AD8307 output gives 1.715V. How much dBm should I have at the RF OUT?

The AD8307 should give 25mV/dB. The intercept point should be -84dBm (first page of AD8307 datasheet). I understand the intercept as a signal level where the output will be 0V.

Based on the above assumption, I get 1.715 / 0.025 = 68.8dB above the intercept, meaning I should ne 68.8 - 84 = -15.4 dBm of equivalent voltage at the AD8307 input terminals.

As the input of the AD8307 is connected through a voltage divider consisting of 91R : 8R2, this one adds 21.6 dB loss, meaning that at the node of the amplifier output, there should be voltage equivalent to -15.4 + 21.65 = +6.25 dBm.

Half the power being then consumed by the 50ohm output resistor, half the power into the load. Therefore RF OUT should deliver +3.25dBm. But that does not make sense, as I measure -3.5dBm at the RF out. Almost 6dB less. Wtf?

Where did I screw up or what is wrong?

//EDIT: I may just see what is wrong! I am feeding the thing a signal containig high amount of harmonics.  I have pushed the "total power" button on the spectrum analyzer, it then shows +3.1dBm. (The first harmonic being -3.5dBm). Maybe this is what is making the error?

[RadioNerd]

I think your assumption about the 50 Ohm series resistor. is wrong... Actually, only 25% of the MMIC output power (i.e. -6dB) is delivered to the load as this resistor forms a voltage divider, not a power divider. This reduces the discrepancy you found by 3 dB...

[Yansi]

Yes of course, it is -6dB in terms of voltage and power too.  I have later discovered that lil mistake I should not work that long into the night.

Later I have also closed the loop and woohoo, it did something. Then I have discovered the calculated values for IC7A are completely wrong.

Now I have new, correct values, which are E24 fun:  R16=6K8, R17=3K0, R30=4K3.  But it does (actually, have not soldered them there yet) according to a simulation what it is supposed to: Convert the dBm output range to a voltage range of the DAC.

Just a short explanation:
We need a +13 down to -7dBm output. There is +6dB at the MMIC output and then -21.6dB less (R3, R8) at the detector. The AD8307 detector produces a voltage in the range of 2.034 down to 1.533V.
This voltage range shall to be scaled to the DAC range, which is 0 to 4.096V.
The IC7A configuration if R16,17,30 above does this, with a reserve of about 5.5dB across the range. This means that the DAC output of 0V means  about -14.9dBm and 4.096V means 18.8dBm delivered to the load.
The reserve is there to account for resistor variation and stuff, to be able to calibrate that out.

I have still not soldered the output MMIC, but will do that in no time. MMG3H21NT1 prepared. 

Up to date schematic below, just for the giggles.

[Yansi]

Good news everyone!

[TheUnnamedNewbie]

Good news everyone!

That is good news! What PCB thicknesses are you going with? Standard 1.6mm? FR4, I assume? I ask because I'm looking at some options for my variable attenuator project and I don't know where to get non-FR4 boards as a non-commercial customer. Alternatives I have also considered is going for a thinner FR4 so those GCPW tracks are a bit more reasonable sized.

[Yansi]

Forget anything else than FR4, unless you want to spend half your earnings onto a single prototype PCB.

As far as I know, OSH park uses some "slightly better FR4" in terms of RF performace.

What kind of frequencies are you interested for your project? I wouldn't bother with Rogers  if you stay within a couple of GHz. After all, you are making attenuator

With FR4, if the substrate is a 1.6mm standard, to achieve 50ohms one should use a co-planar  waveguide, on a 0.8mm substrate a microstrip is the way to go. I use both, depending on a lot of things. (If I remember correctly, CPWG has lower loss than microstrip)

See the attached loss plot of FR4 compared to Rogers.

[TheUnnamedNewbie]

I'm not just worried about loss but also mismatch. Not all FR4 is the same, and I have access to very fancy substrates for cheap through my uni (just use the leftovers from other projects), the problem is just that they can't make plated vias. Not a big problem for the waveguide, but it's very annoying for those chips with big ground planes.

I wanted to use GCPW because it matches the chip footprint better and I believe less sensitive to mismatches of the substrate (since a good portion of the fields are on the top plane between the copper, and not in the substrate). 

And yeah, this is just an attenuator so it's not vital, but in the future I might do projects where it is not, so I thought it could be a good idea to start out. Perhaps I can also look at getting hold of some substrates for home etching... I'll ask around my research department.

Perhaps I'm just having bad expectations... My research involves working on a design where we have 50 um wide CPW lines that are 74 ohms (175 um thick LCP substrate), so seeing the 1.7 mm wide traces on my current design made me frown... Might just throw things into HFSS later this week to see what gives.

[Yansi]

having 50um wide traces is crazy, what is the thickness? Guessing this is completely not standard.  From my little experience in the RF field, this is a complete nonsense to do. The wider the trace, the better, as the etching imprecision will be only a small variation of the overall width.

If you are concerned about missmatch and work at a uni, then have a prototype board manufactured, trace impedance measured, design corrected and done.