Half-decent diy RF generator utilizing AD9951 - an idea

[TheUnnamedNewbie]

having 50um wide traces is crazy, what is the thickness? Guessing this is completely not standard.  From my little experience in the RF field, this is a complete nonsense to do. The wider the trace, the better, as the etching imprecision will be only a small variation of the overall width.

If you are concerned about missmatch and work at a uni, then have a prototype board manufactured, trace impedance measured, design corrected and done.

This is something that works at D-band (the waveguide band, not the NATO one) and uses GSG probes for measurement. Substrate thickness is is 180 um. I'll make a post and maybe even a video on it after all the publishing work is done, for now I'm restricted as we will present this work at a conference in the near future.

That aside: I am going to stick to plain-old FR4 this time I think, I'm starting to realize it is just not worth the hassle to go to fancier stuff. My perception is just a bit skewed since my day-work is on a different scale of frequency. Where most people who do electronics underestimate the impact of trace sizes and discontinuities at a few GHz, I may be part of the few in the world that tend to overestimate the impact 

[Yansi]

Bad news everyone. I have fried the DDS chip. The only one I had. But seriously, I do not know how or why. No fucking idea.

AD9951 soldered on the board, schematic below. Voltages applied correctly, verified 1.8V and 3V3 for DVDD_IO section. There was a large current draw ~50mA from the 5V input, although the DDS was in the full power down mode (PWRDWNCTL = 3V3).

When measured in circuit, the 1V8 rail was pushed to about 2.2V due to current leaking from the 3V3 domain to it. I then even tried powering the 1V8 or 3V3 domain separately, but either of them gulps unhealthy amounts of current.

I just can not figure out what went wrong.

...until my friend have noticed that AD9954 has 1V8 maximum voltage limitation on the CLKMODESELECT pin. I've had that pin hooked up directly to 3V3. BUT! The AD9951 datasheet does not prohibit doing so! There is not a single word that you can't apply 3V3 to the CLKMODESELECT pin. 

So am I the stupid one or does Analog Devices owe me a DDS chip?

I have attached the schematic, so you can verify. The only fault known I haven't noticed before is that with AD9954 you can not connect the CLKMODESEL pin to 3V3.  I have used AD9951, so that should have been fine.

Please double check the schematic for me if you can.

[Yansi]

After a bit of tinkering, the DDS may not be fried (at least not definitely too much), so I'll try to throw some data at it to see if it is alive.

The root cause? The fucking CLKMODESELECT pin. They just do not tell you the critical fact that you can't apply more than 1.8V to this damn pin. They only tell you this in the AD9954 datasheet. Fuck!!!  Yes I should probably read the 9954 datasheet more carefully, since I have designed the board to be compatible with 9954 too, but this should be stated in the 9951 datasheet in the first place. 

I have tried to contact the ADI technical support. My friend tried same. They just ignore it, they just don't care.

[Yansi]

After a bit of necessary wrestling with the DDS, I have finally managed to get it working.

I have found a few issues that, that I can't explain just yet: First, small output amplitude. I'd expected it to produce a lot closer to 0dBm, not -13dBm. 

Second, the signal doesn't look clean as it should have. See the below image. There are significant side-lobes present around the carrier. I can't explain that now, but when I will manage to get an external REFCLK going, I will measure again, to exclude the internal PLL, which is supposed not to be the greatest (but still I thing there might be something else wrong with it. Mainly the power supply, as I took 5V from the ARM board, that is powered from a laptop's USB).

And third the frequency is off by 560ppm. No, my SA is not that much out of cal. I measured 100.056MHz instead of 100. Even my oscilloscope, which uses a bog standard TCXO at best as a ref clock source, thinks the frequency is 100.6MHz or thereabout.

Here is a picture of the garbage around the carrier.

[cdev]

Does the amount of noise vary with different frequencies?

[Yansi]

Haven't done any further testing with it. I was rushing other PCBs to get manufactured. Will check different frequencies. What might cause that crap around the carrier?

Currently I have sent an ADF4360-7 board to be manufactured - as a clean 400MHz reference source for the DDS (to compare performance with the internal PLL in the DDS)
and a simple USB control board with STM32F042 was just sent to be manufactured minutes ago. Small board that can connect all three modules together: DDS, PLL, ALC.

Y.

[phenol]

The side lobes may be generated by noisy avdd. The bigger problem is the offset in amplitude and frequency you are seeing. Wrong register programming?...
As for Adf4360, what makes you think that it’s going to be anything much better than 9951’s internal pll under similar power supply noise  environment ? Maybe the scope of applications that your dds covers doesn’t care too much about close -in phase noise; in this case adf4360 with its fairy wide-band VCOs would be fine. Otherwise, i would either take a stable reference and multiply its output frequency as needed or make a narrow-band shielded vco with some external pll(adf4106 or whatever).
I think you can find narrow-band vcxo (saw-based) low phase noise oscillators, but those are not exactly cheap...

[Yansi]

I'd not really be so sure on the PSU noise. The DDS has local supply regulation, even I have separated the DVDD pins using ferrite beads.  I mean, nothing fancy about the supply, but I have used similar concepts in other designs, that produced much higher frequencies with much cleaner outputs.

Wideband or narrowband VCO... What's the definition of? I think what mostly we are after the tuning slope, MHz/V.  Then I'd consider the ADF4360 to be narrow band VCO. It has a range of 350 to 1800 MHz, but the specific place of operation is set using external inductors, relative bandwidth being not that large, i.e. maybe 20-25%?



Similar chips like ADF4350, these switch in between banks of narrowband VCOs internally, resulting in something about 30MHz/V if I remember correctly, even though the range is like 2200-4400MHz and tuning voltage range just few volts.

So should these be considered wideband? I am not sure.

Why I don't like the internal PLL in the AD9951? A good question! First, it's capabilities in terms of multiplier ratios is quite limited, one might even say idiotically, as it requires at least 20MHz input and can not  work from a 10MHz standard. Second, even the datasheet and the manufacturer suggest that performance of the integrated PLLVCO is not the greatest. See the last sentence in the capture below. 



Is this really a show stopper here? I really do not know. Hence why I want to compare using a decent external PLL, that will also allow me to multiply from 10 MHz reference, which is a welcomed option.

I will try another measurement later today, to see how the supply influences the output.

[Yansi]

Just out of curiosity, I have done the slowest sweep on my SA possible (SWP 430s, VBW 10Hz, RBW 3kHz), to see what the result will be.  The result is, the SA has a slight alignment problem under these conditions, as obviously the signal should have been centered.
I have also moved the reference to -20dBm to better show the noise floor. Now the noise floor is below -90dBm. 

My measurement techniques may be not all that correct anyway, I do not know how to do better. How should I really measure this?

The frequency is still 58ppm off. I think the SA reference osc is quite still in cal, if I remember comparing to a precise TCXO. Maybe the crystal I have used is junk (even though I chose 10ppm one), or I might have soldered there a wrong loading capacitor. Will check.




//EDIT: Replaced the load caps, now it sits -6ppm, which is well within spec.

[phenol]

i remember that ad9910 +internal PLL gave significant improvement in phase noise that even a mediocre spectrum analyzer could show when i replaced a bog standard lm317 regulator with something much quieter.
as for the  vco, this is what i would call narrow-band: http://www.crystek.com/microwave/admin/webapps/welcome/files/vco/CVCO55CX-1000-1000.pdf

[Yansi]

Gave significant improvement against what?

I think that having a local voltage regulation plus separation of DVDD using ferrite beads is about the reasonable maximum. Otherwise I'd consider it hunting ghosts.

We could then start the topic of DGND vs AGND, but I think in most cases it is better to have no separation, then wrong separation, while the latter is much easier achieved.

The only other trick I know which is still kind of reasonable to implement is to use a capacitance multiplier with a transistor, as this provides for a very low noise. Not sure if it would help here anyway.

What I also think might be the cause is the Qtal oscillator (being quite high impedance circuit) is picking up crap. On the board I have designed I have accounted both for the crystal and external reference input, so the traces might be a few mm longer than is usual. Any kind of disturbance to the oscillator will be directly seen at the output.

If you think the internal PLL is good enough, then there is not much choice left. Either the power supply (which I kind of doubt), or the oscillator. That could be easily proven, if I'd connect an external oscillator (a good one, eg. a TCXO) but still use the internal PLL to multiply up to 400MHz.

[Yansi]

 No, not the crystal oscillator. Have tried connecting an external one, the crap is still there, without any visible change. So what else? I don't think there is anything particularly wrong with the PSU circuit, please see attached below, you can check.

//EDIT: Added missing tantalum cap values in the schematic.
//EDIT2: Also tried if there is difference when board supplied 5V from USB or from a cleaner 5V linear supply. Result: No difference visible in the output crap amount.

[phenol]

The improvement was in close-in phase noise up to 10k or so away from the carrier. I observed the noise go down 10-15db 1k away from the carrier when i placed 3300u cap on the output of lm317. This was clearly the 1/f (kind of)noise contribution of the voltage regulator that was modulating the internal vco. Note that it didn’t have the ‘spiky’ lobes  your analyzer shows and that i used the actual ad9910 demo board, which seems to have split ground.
ground loops? digital noise coming from your controller/laptop/pc?...

[Yansi]

As I have already said, there is no influence whether powered from USB or completely isolated linear PSU.

There's a single GND plane below, still not sure how the sidelobes could be caused by it. Please find the PCB layout attached.

I will try disabling the internal PLL and using external high frequency XO, if I will find one.  I am still suspect the crap comes from the internal PLL.    I have cobbled together some other PLL circuits in the past, on a home etched pcbs that were way worse than this. Never had such crap on the output, unless idiotic me thought it would be good to run the tuning voltage to the VCO using a 30cm of unshielded wire. Well, no...

[phenol]

i doubt it’s your ground plane causing this... i was referring to other external devices that may be hooked to your dds board. how do you program it? can you configure it and then somehow disable all digital crap nearby? can you make a scan with 50k-100k span and RBW=100-300Hz?

[Yansi]

The registers of the DDS gets set, and then the communication is silenced.  The MCU on the board nearby is still running, but it is unlikely it does that (my 1627MHz PLL did not have any visible issues with the same MCU board). It has also it's own local voltage regulation and if I remember correctly, I have even tried powering the MCU and DDS from a completely separate PSUs, with no change.

No, I can't do that, the minimum RBW of my SA is 1kHz. But if you want (and will be useful for you), I can do 50k or 100k span, 1k RBW. What VBW do you want to set?

//Looking in the manual, they mention 300Hz RBW in the specs. Have no idea how to set it there. It never did allow me to set less than 1k. Interesting.

[Yansi]

Here's the 50k SPAN, 1k RBW, 1k VBW capture.

[phenol]

https://www.eevblog.com/forum/projects/1ghz-clock-source/25/

i did some comparisons between PLL vs external 100MHz x 10 clock as described in the thread above. I can’t remember if this was before or after low noise regulators were installed...

[Yansi]

I've managed to get to a better SA for a few hours... Here's the result.

The sidelobes are there, -80dBc. Should I be really concerned about them?

There are a few measurement with different spans and RBWs. The last one being 10kHz SPAN with the lowes possible RBW/VBW setting. Pretty awesome result I would say.

As a sidenote, the power was drawn from a USB port of a PC. Not exactly a clean 5V source

[phenol]

it doesn't look bad... the screenshot (of the original AD9910 eval board clocked by an external source) i've attached was taken with a FSL analyzer, which has inferior phase noise to FSP. There's a 10-dB external attenuator in order to bring the signal down to -10dbm. The humps around the main tone are most probably reciprocal mixing products of the analyzer's own phase noise, which isn't all that great...

[yl3akb]

I've managed to get to a better SA for a few hours... Here's the result.

We also have R&S SA at work, and first thing when I see that red (*) on the right is check if SA is not been overdriven. But probably it is not the case here as spectrum seems quite pretty.

[Yansi]

The red asterisk did randomly appear and diminish the whole time. Have no idea what it means.  -10dBm should not overdrive any SA, when the attenuators are in automatic mode.

Y.

[parasole]

Interesting project, any progress update?

[cdev]

Different chips, but similar goals.

[Yansi]

Interesting project, any progress update?

No updates, not enough free time to proceed.

So far a DDS module is finished, working. Need to solve why the output is lower than expected.
I have finished also an ALC module, to control output level in the range of  20dB, rest gets dealt by a relay attenuator (not yet verified). ALC module seems working correctly (verified partially). Haven't had available any suitable test equipment to verify, now I have so proper verification of ALC is on the list.
Control board also has been made for this project:  A small USB equipped microcontroller to interface with both the DDS, ALC and also ADF4360 board, which should serve as a 400MHz reference locked to a 10MHz standard. (AD9951's PLL unfortunately requires 20MHz minimum if I remember correctly).

Some time ago I have scored a rusty & crusty Agilent E4432B for really cheap, so this DDS project got how to say that ... a low priority. I do not plan abandoning this little project, but I have more stuff to do than I ever probably could, so...     (I guess typical EE enthusiast is the diagnosis).

I have also some more advanced concepts on the list, using the well known ADF4350.  Two of those mixed together could make a really nice RF synthesizer, say from (almost) DC to about 1 GHz. Using the ALC block invented in the project above (yes, could work up to GHz), only the RF mixer and filters would need to be tested. Off-the shelf monolithic ceramic filters and MMIC mixers with high linearity would probably make this quite usable result. However I would not like to anticipate to much here. 

Important stuff needs to get done first.