Half-decent diy RF generator utilizing AD9951 - an idea

[Yansi]

Hello,

currently lacking a RF generator in my "lab". As there is not enough funds to buy anything half-decent and components, PCBs or time investment is not a problem, I have jumped to the conclusion I should build one myself and get some new experience from that.

I have a bunch of AD9951 available. I know that there are some chinese modules with them, but they are not pretty. By half decent I mean:
A proper balun for the DDS, ALC and attenuator.  Up to 150MHz, starting at 100kHz (preffered). Up to 20dBm output power (at least 15dBm). Maybe AM/FM mod.

Here is the block diagram I have cobbled together. Nothing too complicated, but still a lot of work I think:



Description of the blocks:
DDS: AD9951 (datasheet)(400MSps with 14bit DAC - reasonable SFDR may be achieved).
Balun: I have a bunch of MiniCircuits TC1-1T+ transformers here.  (However not the best choice for the low end - requires 400kHz or more)
LPF: Some kind of elliptical filter - yet to find what the manufacturer recommending is.
AMP1: Whatever general purpose MMIC amplifier.
PIN attenuator: This is the part of the ALC block. I have mady my mind I could use BAP64Q PIN Quad to do this. May work still respectable at 150MHz.
LOG Detector: AD8307 (datasheet). I have bunch of those too. Has enough dynamic range to fully utilize the PIN Quad and is cheap.
AMP2: MMG3H21NT1, HMC482 or whatever I will be able to get or find.
Two output resistor pads with Omron G6K-2F-Y relays.

I am yet to calculate thoroughly the dBm in every part of the circuit, if I will be able to do it like so.  But it seems I can get about -5dBm (10mA DAC current, 1:1 balun at 50ohm) from the DDS itself, loose some dB more in the LPF. Then use the AMP1 to compensate the loss and to drive the "PA" through the PIN ATT, which sounds about right, that the AMP1 will need about 10dB of gain (cruel estimation).  The two output ATT stages will be done using relays and resistor pads.

The ALC loop utilizing the AD8307 and the PIN quad BAP64Q seems to be able to achieve about 50dB dynamic range at 150MHz. Which if the requirement was +20dBm output maximum, means the minimum with this configuration will be somewhere about -70dBm. Which sounds about halfway decent. The ALC servo amplifier will get a setpoint from a DAC to set the output level anywhere in its range.

As the AD9951 has an integrated multiplier before the DAC, I was thinking I could utilize that to to implement a simple AM modulation using just that, if one makes sure the ALC servo loop bandwidth will be low enough (<20Hz) to pass the modulation. The modulation signal (say audio bandwidth would suffice) would get sampled by an ADC, and converted into the amplitude control word for the DDS.
FM modulation of course also possible, by directly manipulating the FTW. This may be to cruel, but will do the job - so I am thinking.

A nice feature would also be to sync the generator onto a 10MHz external standard. What is not so nice is that the AD9951 requires at least 20MHz input. One would need an external PLL (and probably bypass the internal one in the AD9951 in that case to achieve better phase noise).

Can you please apdisprove my ideas are correct?

Thanks, Y.

[DC1MC]

I'm a bit of an older guy and form experience I was thinking that best is to define the the project goals:

 - Frequency range ?
 - Output range, impedance ?
 - Will it be modulated, and if yes, what kind of modulation will be ?
 - Will it have some kind of external reference (10MHz GPS source) ?
 - Will it be syncronizable with an external signal ?
 - What resolution and stability are targeted ?
 - Any other waveforms besides sine ?

 Once you defined your project goals, is much easier to do the architecture and practical design, of course IMHO and IMMV.

 Cheers,
 DC1MC

[Yansi]

I think all is defined above.

To sum up:

- Frequency range: 400k - 150M
 - Output range, impedance: +20dBm (or at least +15), down to at least -50dBm. 50ohm standard.
 - Will it be modulated, and if yes, what kind of modulation will be: AM/FM, audio BW.
 - Will it have some kind of external reference (10MHz GPS source): Would be nice to support one
 - Any other waveforms besides sine: Only "pure" sine.

Please bear in mind, I am doing this mainly to gather more experience in the RF field, so I will prefer to work with what I have already available and make some useful piece of equipment at the same time. 
I am not designing based on spec, I will be designing mainly based on what is available.

[rhb]

Looks damn good to me.  Build it.  I'll gladly buy a couple of your excess boards. 

Rather than jump through hoops over the reference frequency, just use what is convenient.  While 10 MHz is the most popular, there are lots of things that require different frequencies.  A number of QRP-Labs devices and the SDRplay RSP2 come immediately to mind. 

Leo Bodnar had designed a GPSDO with two selectable output frequencies which is sold by SDR-Kits.  As Leo's unit is at the same price as a BG7TBL 10 MHz GPSDO (~$200 US), I can't see any reason to complicate your design. Just use something other gear uses. 

However, the RSP2 uses a 24 MHz clock.  So with an RSP2 and your SG phase locked together you've got a cheap VNA which can be upgraded by adding one of Leo's GPSDOs.  I've urged SDRplay to produce something like what you're describing, so maybe they would be interested in producing your design. 

I should like to suggest you look at the FeelTtech FY-6600 thread especially around pages 14-15.  There are spectrum analyzer plots comparing it to an R&S AWG.  I do *not* recommend buying a FeelTech unit until they address the UI FW problem discussed in the reflashing thread.  Mine is a V 3.0 unit which borked itself just after I went through all the work of adding a grounded power cord.

A clean, low cost ($100-150), 14 bit sine wave from 0.4 to 150 MHz in combination with a 12 bit RSP2 would be an awesome piece of kit for HF design and test. 

[Yansi]

Well I will certainly build it simple parts first. Especially I would like to tinker a bit with the PIN quad. Never used any PIN diode attenuators before. Some testing boards are being prepared for it already.

I will take a look at the FY-6600 thread. Not going to buy that - at least not now.

[RadioNerd]

How do you plan to realize the 0.4 - 150MHz directional coupler for the ALC?

[Yansi]

It does not necessarily have to be directional.  I think a resistive splitter would work fine too in there.

[rhb]

Consider using FET muxes for the attentuators.  It might lead to a nice design.  Though perhaps at the price of having to select parts for each step in the attenuator to match the Ron of the FETs.

[Yansi]

What FET MUXing do you mean exactly? Can you give example please?

I do only know about off the shelf RF switches, but their isolation usually very much suck balls and the realys are still superior, at least to those cheap RF switches.

The Omron G6K-2F-Y relays are rather cheap - so I do not see an issue.  At 100MHz they are supposed to offer >45dB isolation.  An equivalent DPDT RF switch would cost a shitton more I guess.

[rhb]

Look at the TS5N412 SPDT for $2.96 quantity 1 from Digikey.  -50 dB isolation.  But if you use two, one at the attenuator input and one at the output I think the isolation would be better. Two devices would give you 5 attenuator steps.

I do *not* know if these would be better for your project.  I'm merely suggesting looking at them. 

Another possibility is the HMC349 for $6-7.  Great specs, but probably overkill in this case.  Though it does look attractive for the switching of an S parameter test set for my new VNWA 3EC.

When I was looking for such things a few years back there were a lot more options.  I don't know if Digikey doesn't list everything or if the higher pole count switches were all discontinued.

[Yansi]

Those TS5N412 does not look right as an RF switch. The HMC349 is nice otherwise.  Mouser does have a lot of interesting RF switches available, including multipole ones.

Mouser has this one for similar price as the HMC349, but seems with better isolation, 74dB at 2Ghz is awesome: http://www.mouser.com/ds/2/464/IDT_F2923_DST_20151124-883678.pdf 

But for now I will stick with the relays. I have those available, can buy more for about $1.5 a pop and this part of circuit can easily be replaced by an electronic switch later.


Currently I am puzzled a bit how to design the ALC loop. (the output atten. seems to be the easiest part) I'd like to test this part of circuit first. And then the DDS implementation with AD9951.

[rhb]

Where can you get RF relays for $1.50?  Please do tell.  I need 4 SPDT relays good to 1.5 GHz.

[RadioNerd]

I would also recommend relays for this application.
Electronic switches as nice but with most of them performance (especially power handling and linearity) drops considerably at frequencies below approx. 10 MHz. An average SP2T may handle 30dBm at 1 GHz but can be limited to less than 10 dBm at 1 MHz... And only very few (expensive) parts can cope with DC. These are all non-issues for traditional relays.

[RadioNerd]

Another comment regarding the leveling circuit:

In the current block diagram, the power sampling is done after the AMP2 block. If you use a resistive splitter (this means poor isolation) at this point, the output power will depend quite a lot on the load attached to the output. This is because you are implicitly leveling the output voltage rather than output power.

A possible way to alleviate this issue is to realize AMP2 with an opamp (or 2-3 paralleled for minimum impedance) with a 50 Ohm series resistor to the output. If you now sample the voltage between the opamp and the 50R output resistor you should achieve both a constant impedance at the signal generator output and a considerably more accurate power leveling without having to use a directional coupler.

[Yansi]

Where can you get RF relays for $1.50?  Please do tell.  I need 4 SPDT relays good to 1.5 GHz.

Those G6K-2F-Y Omrons aren't exactly RF relays, you can buy them cheap from China.  And they work just fine.

RadioNerd: Good point on that one. However... what if I would build a generator up to some hundreds of MHz? I do not think the opamp way is the right one to choose. Also I do not think there are opamp output stages in any of the RF generators. There must be a simpler way to achieve this. But you are absolutely correct, that by sensing just the voltage you won't achieve constant power.  There would be a lot of problems driving nonlinear loads (like diode ring mixers) too.

Directional coupler for the 400k-150M range could be made using RF transformers. (Have bunch of these MiniCircuits ZEDC-15-2B laying around - they use two small transformers inside. It is a 15dB directional coupler 1 to 1000MHz.  I think it could be possible to make a directional coupler on the same principle.

Or is there any other solution to output power leveling, that would level power indeed, instead of just voltage?

I do not like the opamp idea too much, as I am afraid that OPamp capable of 100mW @50ohm at 150MHz would cost quite a lot more.

[DC1MC]

I would agree with the RadioNerd about using the relays instead of any strange solid state devices, EVERYBODY uses them, from FeelTech to R&S and Tek, so it has to be something in it , the dynamic and frequency range it's actually too large for an off the shelf component.

[Yansi]

Well, is it after all possible to use an opamp? I have done a small research and am not sure about this solution would work.

I did find THS3001 to be the No1 for arb generator output stages.  Its availability is bad and it cost like $10 a pop.
A  GBW of 420MHz would allow me only to produce a gain of 2 at 150MHz. That is just poor 6dB.  If I wanted 20dBm output, well... that's a LOT of drive signal on the input, considering even that I would burn half the power on the series resistor to make it behave like 50ohm source. So I would need it to amplify the signal up to 23dBm level, which means 4.47Vrms output swing - well... I doubt this opamp is gonna cut the mustard, as the voltage swing required at 150MHz calls for almost 6kV/us slew rate... Well, no sorry bob. The opamp has only 6.5kV/us SR rating - am afraid of some nasty distortion happening in there.

I could probably find a better opamp, but is it worth it to use even more expensive part in there?    The price of the opamp would become a significant portion of what the AD9951 would cost.  I am not liking that 

So back to the MMIC amps... ?

[Yansi]

Regarding the directional coupler: If this would solve the power leveling issue RadioNerd noted: I'd prefer to use an off the shelf solution for it, rather then trying to make custom transformers (even though it would cost less, as many of us have hoardered a lot of different RF cores) - just to make the result more repeatable.

After a quick search, I could not find any suitable directional coupler for this frequency range. All of them have just too high minimum operating frequency and well, I do not want to give up on those 400kHz (and probably will try to push it as low as it will be possible).

One can get MiniCircuits TC4-1T+ transformers for quite reasonable $, so why not use two of those to make a 12dB directional coupler? It would produce +8dBm maximum for the log detector - which is very reasonable amount and overall solution I think.

Does anybody know of some off the shelf 10-20dB directional coupler for the frequency range of 0.4 to 150MHz?

But still I am not sure, if the directional coupler solves the issue of output power leveling to "strange loads" like short circuit and non-linear loads (mixer diodes). I hope it does. 

//EDIT: Just found this. I am stunned things like this can be patented  http://www.freepatentsonline.com/5337006.pdf

[RadioNerd]

Regarding the opamp approach:

1) Your 20 dBm requirement makes it indeed not easy to find a suitable opamp. 20dBm @50Ohm actually means 12.6Vpp before the series resistor... I would rather suggest to relax this requirement to something like +13 to +15 dBm (like most RF signal generators) and using an external amplifier in the situations where you really need more than that.

2) Many wide bandwidh opamps (like the THS3001) are of the current feedback type. Current feedback opamps do not have the traditional GBW limitation of voltage feedback opamps. Another possible candidate would be the LMH6703. It has a somewhat lower slew rate but it is much cheaper and easy to find (e.g. digikey).

3) some amount of distortion at the high frequency end is not that terrible for a sine wave signal generator. This will mainly result in harmonics that can be filtered with a low pass filter. At lower frequencies the opamp gets increasingly linear anyway as the open-loop gain ant thus the effect of the feedback increases.

[Yansi]

Well.. that LMH6703 is interesting and even seems to be cheaper than the THS3001.  But still - not enough swing can be done at such frequency to achieve the desired power level.

What are otherwise the drawbacks of the solution using the +20dBm MMIC and a directional coupler? Pricewise it seems it will end up similar, may be a little cheaper ($2 MMIC, $4 coupler). MMIC + coupler can provide more power, but seems to be a more complicated solution.

Still I do not know how the  solution with a dir. coupler will behave when the output will be short, open or put across a load that will limit voltage (diodes).

Maybe I could relax the output power requirement to 15dBm (32mW) or 13dBm (20mW)... but I did not think of 20dBm being such big problem at 150MHz. Be it a GHz or two, I'd expect a problem, but certainly not at 150MHz. I wanted the larger power to be able to characterize stuff with it (being able to overdrive stuff a bit) without the use of additional amplifier.

So what do you recommend, how would you design an ALC circuit, that could work up to 13/15/20dBm? I do not really know how is it supposed to be done to work properly under different loading conditions.

I already know that simple voltage sensing will not work, as it will regulate voltage (obviously), but not the output power. (In a short circuit condition, it will maybe even try to blow itself up. With a voltage limiting load, it won't work either, as it will try to push the voltage up resulting in more power delivered, than expected).

So how it is supposed to be done?  Without opamps... you can't use those very much at the higher frequencies either. I'd rather leave those for arbitrary waveforms. (1Gsps DDS is also waiting here, but I wanted to start with something more easy first - at just 400Msps / 150MHz)

[RadioNerd]

The frequency range is the difficult part in my opinion... for 10-150 MHz I would certainly take the MMIC+directional coupler approach, which should also allow to reach the desired output power goal. For the range below 10 MHz however I would rather use the series resistor approach with an opamp or discrete transistors. This would make it also much easier to add DC offset to the output if desired.

Minicircuits has directional couplers with good directivity in the frequency range from 0.2-250 MHz. I newer used one of these however and they are also quite expensive. I assume they would work, though...

[Yansi]

So the directional coupler approach (my first thought as per the diagram) would actually work? Even in case of a non-linear load? How would it behave in such case?

I have some gaps in knowledge - what forward power will the directional coupler give to the detector, with the output shorted / open? Just to be sure I understand that correctly.

(I have browsed through the MiniCircuits web and did not found any suitable couplers. All of the couplers have too high minimum frequency, or their cost speaks directly against using them. Hence why I have proposed to make a custom one, using off the shelf transformers.)

[RadioNerd]

coupling factor flatness and directivity are the most important parameters of the coupler for leveling applications.

The coupling factor flatness (i.e. frequency response) indirectly determines the number of frequency points at which you have to calibrate the amplitude of the signal generator to acheve a constant output power over frequency (toghether with the response of the detector of course).

The directivity defines how well the coupler isolates the forward and backward travelling energy on the coupled port. The extremes are short/open (100% reflected) and perfect load (0% reflected). The better the directivity the less the coupled power is altered by the reflected power.

[Yansi]

To sum that up, you are telling me what? That it will not work good enough using directional coupler? What else do you recommend then to make output leveling?

If multipoint calibration is so much of an issue in a RF generator, what is used in commercial equipment to do so, that it does not need so much calibration?  Based on what principles are the ALC circuits made in such units?

And don't tell me they use OPAMPs,  please    I imagine they use a different synthesizers for different bands - at least for the low band. - that may utilize the opamp, sure. But the rest?

[RadioNerd]

Sorry if I was not clear. The coupler approach will definitely work. However, its performance directly determines the performance of the leveling circuit (frequency response and accuracy).
Whereas commercial parts come with a nice datasheet and sometimes S-parameters, the custom coupler must be tested first to see whether its performance is OK.

regarding your other points:

1) Wideband RF signal generators usually use a separate DDS based signal path for the low frequency end. Its quite possible that opamps (e.g. like the ARB output stage amp you mentioned) are used for this range... The high end (from about 100 MHz) is of course leveled using a directional coupler.

2) Commercial RF generators do use multiple calibration points (who said that this is not an issue in commercial equipment?). And a lot of them. For example, in the description of the TSG4100A series signal generator, Tektronix states that its power leveling is based on a calibration matrix with 40000 entries... (https://www.tek.com/datasheet/tsg4100a-rf-vector-signal-generator-datasheet). The only difference is that they put a lot of effort in the efficiency and automation of the calibration routines, which may not be the most exciting part for a homebrew project.

[Yansi]

Maybe I did not understand you well - but what is then the problem of having a custom coupler made?  As far as I can see (or googled respecively) there are none couplers made for this frequency range, or these low frequencies. Even those that are close either are unobtanium or expensive, likely combination of both.

Therefore I have proposed to use a pair of TC4-1T transformers to make a custom 12dB coupler.  Characterization of such beast is another story, as my lab is well under-equipped, regarding RF test equipment. But I can make it happen, including S parameters on a commercial VNA - just to see how bad it will be.

[RadioNerd]

All I want to say is that both approaches have their strengths and weaknesses.
Unfortunately, your desired frequency band lies between the optimum range of the two. Therefore some compromises must be made. You have to decide which criteria are most important to you and choose the best approach based on that:


Directional coupler + MMIC:
+ Easier to get high output power above 50 MHz
+ No issues with high frequencies; design could be re-used for a generator based on higher frequency DDS or RF PLL IC
- Lower frequency limit (coupler and bias tee for MMIC, 1/f noise, stability etc.)
- Output matching depends on MMIC characteristics
- harder to achieve flat response (more ripple and thus calibration points required)


Opamp + 50 ohm
+ Works down to audio frequencies & DC
+ Very good stability and linearity in the range DC-20 MHz (opamp feedback)
+ Easier to achieve flat frequency response (only dependent on log detector response)
+ Good 50 ohm output matching
- Limited output swing and slew rate (distortions at high frequencies and power)
- Limited to about 100 - 150 MHz using "realistic" parts
- suitable opamps may be expensive

[Yansi]

The frequency range is mainly defined by the DDS chip chosen, however I mainly want to use the generator in the upper part of its frequency range. Those 400kHz I insist upon are mainly due to being able to work with standard 450kHz IF chains.  I'd prefer a design, which I could reuse for even higher frequencies (400MHz - 1Gsps DDS is waiting in the drawer too). If the characteristics of the generator craps out a bit on the low band, I'd not be so mad if it will crap out at the upper band.  I can use bog standard "1MHz all shape generator" to produce a 400kHz sine too. I would also like to have more output power built in, rather than using external amplifier whenever needed.

Based on this I'd prefer the solution using MMIC + coupler. It could be also made as a standalone ALC unit, maybe useful for some experiments in the future - as the achievable bandwidth of the MMIC + PIN attenuator can be quite substatial.

Now the question remains: What part to use for the coupler, or how to make one? Any suggestion is welcomed! Currently I have only two solutions:

1) Use two pieces of MiniCircuits TC4-1T to make the coupler. Can be obtained for $2 a pop. But it leads to a rather difficult pcb layout.
2) Wind myself one using either two separate  toroidal cores, or better use single dual-aperture core - I think that should behave better. Question is, what dual-aperture core to choose?

I can then characterize both of these on a VNA, or probably I can - if they let me use it. 

[rhb]

A daft idea to consider.  Use something like a pair of ADF4351s running in the 2-4 GHz range, filter the harmonics and mix.  It is my understanding from various forum posts that this is what some high end HP synthesizers do. It won't give you the frequency agility of a DDS, but it will give you low THD.

I've got an AD9851 and an ADF4351 awaiting application.  So I'm watching closely.

[Yansi]

Well..  that might work, but isn't that a freaking overkill? I just wanted to make some use of the AD9951 I have, by adding output level control to it. Not to build the worlds best and cleanest RF generator   But I have also a bunch of ADF4350s here, just in case 

BTw, just out of pure fun, I have made myself a 15dB coupler out of completely unknown 2-hole ferrite core. I will measure it's performance later. Currently making a connection kit for it with SMAs.

Does anybody have any tip, where to source suitable dual hole ferrite cores for such an application? (up to 150MHz) Where to source these, with a reasonable price?  Maybe it's time to make my own coupler, as there is really nothing useful manufactured for this kind of application - except for those things that begin at $20 a piece.

[rhb]

Hell, if you've got one just build it, measure its performance and iterate!

I'm also  quite interested in the problem posed by unknown magnetic cores.  And *really* annoyed that my $1800 Instek MSO-2204EA won't let me make an X-Y plot of ch1 and integral(ch2)!

That said, if you've got a signal generator and a DSO, you can dump the data to a PC and use Gnu Octave to plot the hysteresis curve and make other measurements.

[Yansi]

You could always integrate in post-processing.  In this case I am a bit afraid the core will be tooooo much high frequency one, with a low mu.  It is from an oooooold analog SAT TV tuner. It was a part of some diode ring mixer in there. Haven't bothered to investigate further.  I have only four of these cores. Need to source other ones! If I would know where...

[Yansi]

So now some fun is ready to be executed. 

//Sry, pcb not yet cleaned.

[Yansi]

 A quick dirty test  of that little bastard, using the very limited equipment I have at home:

Used a fixed frequency 118MHz source of +7dBm and a SA as the power meter:
Connected to the IN port, CPL is terminated -> measured OUT is 0.75dB lower than IN (about 6dBm).
OUT terminated instead, CPL is measuring about 15.6dB below OUT, at about -9.6dBm.
Now reversing the ports, OUT is being powered, IN terminated, CPL measures -34dBm.

So: We have 0.75dB insertion loss.  Fair enough.
We have a 15.6dB coupling, which is nice, as 1:6 ratio coupler should theoretically be exactly 15.56dB.
Directivity - am not sure how to measure one, but if it is the diference between  CPL levels for the same FWD / REV power, than we have 34-9.6 = 24.4dB directivity. Thaaaats very disappointing unfortunately.

Please bear in mind, the measurement is very dirty and the dBm values can not be taken that seriously, there might be about 0.5dB (or even more) inaccuracy of the reading.

//EDIT: As a reference, I took a measurement on a MiniCircuits ZEDC-15-2B. Loss: About a dB or so.  Coupling 15.2dB. Directivity 45dB. Which is about right on the money with the datasheet.

Why is my coupler so bad? Is that due to the single core construction? (The ZEDC-15-2B uses a pair of toroids).

[DC1MC]

When I need magnetic cores; I always buy one of these and dismantle:
https://www.ebay.de/itm/RF-SWR-Reflection-Bridge-0-1-3000-MHZ-Antenna-Analyzer-HF-VHF-UHF-return-loss/222740607922

[ogden]

Mouser has this one for similar price as the HMC349, but seems with better isolation, 74dB at 2Ghz is awesome:

That's huge overkill. 20dB or better per switch will be good enough - considering two switches per 20dB attenuator.

Coupler will only screw-up linearity of your gen w/o adding any useful function. Better just use simple resistor power splitter (1:20 dB or so).

[yl3akb]

Exactly. You are not measuring reflected signal, so no need for good directivity. Leveling calibration would only be correct when loaded with 50 ohm loads anyway. Check this about unequal resistive power splitters: https://www.highfrequencyelectronics.com/Mar07/HFE0307_Adams.pdf

[Yansi]

I know, those unequal resistor splitters aren't exactly fun to be calculated. 

Well, I'd be glad if I would not need a coupler. But that what I am trying to figure out the whole time. The fact that the levelling will only work at 50ohm load may be a problem!

Imagine I have a highly non-linear load: A diode mixer.  The mixer will be a level 7 type, i.e. requiring the LO source to deliver +7dBm into 50ohm load. If I set now the generator to 7dBm and load it with the mixer, the voltage will get clamped and highly distorted, by the diode load in the mixer. Due to this fact, the ALC in my generator will go nuts, as it will see the output having lower voltage, than expected. Due to this, the servo amp will saturate, making the PA in the generator to go full power, trying to force the required voltage over the nonlinear load.

I do not think that this is how the ALC is supposed to work. (It'll not work for this case at all!)

[RadioNerd]

You are not building a VNA. For ALC applications a directivity of 15-20 dB should be OK.

[Yansi]

Okay, I do not have any kind of reference as what directivity may be required for what application.  Still I do not know how the ALC using a coupler will respond to open/short/nonlinear loads.

Guessing at the open condition, no forward power will be seen, therefore one would expect silly ramp up of the output level to the max. Guessing the same will happen with the output shorted.
But I understand it as it may work with the nonlinear load - somehow.
/\ really not so sure about these


But what about this one?  Using an asymmetric power divider for the ALC followed by an attenuator?  The attenuator will definitely have two advantages:
1) Makes the output match better
2) Load isolation. Seems it is just what we want. The output will behave more in a "resistive" fashion and will tolerate non-linear loads much better.

The main drawback being it is deliberately lossy. I would need either to pull back the requirement of +20dBm output, or amplify it even more (I'd rather not do that).

Supposed I could live with only +13dBm output, the following could be done using a 20dBm P1dB amplifier:



What I find also interesting about this solution is that it will be a lot more linear. Definitely more than a coupler, where the loss, coupling and even directivity change significantly across the frequency span.

It is a kind of win-win solution, it seems.  Or does anyone have any better solution than this? (I am still not liking the coupler approach due to it being almost unobtanium component and also complicated to make and even more complicated to make behaving well over 400k-150MHz)

[yl3akb]

Good point regarding to nonlinear loads. It is an interesting topic, so I did a quick simulation of Your coupler schematic with different extreme loads (open, short and single, parallel diode), just to get the idea. By increasing transformer inter-winding capacitance, I intentionally corrupted directivity to just ~10dB. Here are few waveforms of signal at coupled port with different loads. In all graphs, gray is case with ideal 50 ohm load (for easier comparison). With directivity of ~20 dB the load impact is even smaller of course. If it is helpful, I can try different quick things also, like S-params, etc (Its AWR microwave office)

[ogden]

Okay, I do not have any kind of reference as what directivity may be required for what application.  Still I do not know how the ALC using a coupler will respond to open/short/nonlinear loads.

You can check schematics of signal generators to see how ALC is usually done. Keysight (Agilent/HP) provides service guides for obsolete instruments, with schematics. Anritsu as well. For instance HP8648 uses diode detectors, obviously w/o coupler (attach).

[edit] Note that amp output is 4db above set level which means they use ~3..4dB "impedance matching attenuator".

One more thing: AD9951 output level can be controlled using DAC_Rset pin. You can consider to drop pin diode attenuator and use "digital ALC".

[Yansi]

I do not think the schematic capture you have posted is definitive enough one could guess how they do it.

If you think of using only a diode detector, i.e. voltage measurement, then it just won't work with non-linear loads that tend to clamp voltage to a certain level. That is what I am trying to solve here the whole time. Putting a non-linear load, in the simplest form a diode ring mixer, which definitely can be connected to a RF generator, will cause the generator to ramp up the output power to silly level, because it only measures the output voltage, not power. What you set with the dBm is POWER not voltage.

Also note that the LO input of a diode ring mixer presents a load consisting of two diode junctions in series plus the leakage inductance of the LO transformer. Usually these mixers are specified in the equivalent dBm level that would the Zo=50ohm  LO source give into ZL=50ohm load.  How is then one supposed to use an RF generator to feed such load?

[ogden]

If you think of using only a diode detector, i.e. voltage measurement

When you measure voltage on 50ohm load, it's just math "problem" to make it power, not voltage measurement.

I do not think the schematic capture you have posted is definitive enough one could guess how they do it.

For sure they do not use couplers

One more: http://www.dennlec.com/images/manuals/hp-8647a-op-service-manual.pdf

[edit] You regulate power level of attenuator input, not generator output. Think what will happen with your diode mixer argument if you switch 20dB output attenuator on.

[Yansi]

You set the POWER, not voltage.

The load is not always 50 ohms and not always linear. How is your mathematics gonna deal with that one?

If I set +13dBm on an RF generator and give it a two antiparallel diodes as a load, what will be the output voltage? Will the generator say "OUTPUT UNLEVEL"? I don't think so. It should deliver 13dBm  (20mW) to the load, not 1V RMS - which indeed is not possible with a nonlinear diode load.

I still do not know how this is supposed to work in an RF generator. I am still trying to figure out. I am not liking the fact, that a voltage self limiting load will make the ALC go nuts. Just trying to find a solution for that.

[ogden]

If I set +13dBm on an RF generator and give it a two antiparallel diodes as a load, what will be the output voltage, huh?

How regulation of attenuator input will help in case of nonlinear load? Huh? What I am telling - generators do not deal with problems you are trying to solve They regulate output *voltage* for 50ohm load. If your load is not 50 Ohms, then output voltage will not match. In case you set output POWER, then your load *must* be 50ohms.

[phenol]

check out the output section of an old Marconi 2019 sig gen. It uses matched pairs of detector diodes and no directional couplers. The low frequency portion of the output stage has jfets acting as voltage-controlled emitter feedback resistors.
https://doc.xdevs.com/doc/Marconi/MARCONI%202018A_2019A%20Service.pdf
page 222

[Yansi]

Okay, supposed it is as you present it: There is always an attenuator in line.  That is a solution I have already presented a few posts back. (see image below).

But what about the case, where the attenuator is set to zero and ALC connected right to the output? That is the problem I am trying to solve.

Maybe it got already lost in the thread becoming lengthy, but the original goal for my AD9951 gizmo was to use the ALC to directly set output level in the range of +20 downto -30dBm and then use two* additional 20dB attenuator stages to widen the range downto -70dBm.

*I do not think that a single 40dB attenuator stage is easily diy-able, as it would require switches with rather high isolation .. ? But maybe it is still possible, who knows.

[ogden]

But what about the case, where the attenuator is set to zero and ALC connected right to the output? That is the problem I am trying to solve.

Maybe it got already lost in the thread becoming lengthy, but the original goal for my AD9951 gizmo was to use the ALC to directly set output level in the range of +20 downto -30dBm and then use two* additional 20dB attenuator stages to widen the range downto -70dBm.

Well, all generators (I know) outputs twice voltage when unloaded. Think about that for a moment.

*I do not think that a single 40dB attenuator stage is easily diy-able, as it would require switches with rather high isolation .. ? But maybe it is still possible, who knows.

As I already said - you can use quite crappy switches for attenuator switching at given frequencies. 20dB leakage per switch can be considered good for 20dB attenuator - because two switches will leak -40dB of incoming 0dB signal, -40dB will be added to -20dB of attenuator output. Anyway nonlinearity of your whole thing will be worse than that.

[ogden]

*I do not think that a single 40dB attenuator stage is easily diy-able, as it would require switches with rather high isolation .. ? But maybe it is still possible, who knows.

As I already said - you can use quite crappy switches for attenuator switching at given frequencies. 20dB leakage per switch can be considered good for 20dB attenuator - because two switches will leak -40dB of incoming 0dB signal, -40dB will be added to -20dB of attenuator output. Anyway nonlinearity of your whole thing will be worse than that.

Anyway single 40dB output switch is not that good idea. Better have narrow ALC regulation range (like max 10dB) and more attenuator steps on the output.

[Yansi]

I understand, why it outputs twice as many volts unloaded. Thats because Zs = ZL.

If I place ALC, a voltage regulator, at the point the ALC senses the voltage, will be a node with a zero impedance, not 50ohm.  And that is the clue how to do it, isn't it?

The biggest help was the Marconi manual phenol has posted, so thanks for that! From observing the schematic and reading a bit of  the text above, I now understand the problematic a lot more.

Great help guys, thanks for helping me to see the truth.

The reason why the Marconi RF generator has only 10dB of ALC range is obvious - it uses a linear detector!  I intend to use a log detector for the output level, so I can leave out some of the attenuator switches - I won't need that fine attenuator step.  Maybe I should reconsider what the ALC range will be though, as 50dB is kind of many.

[ogden]

I understand, why it outputs twice as many volts unloaded. Thats because Zs = ZL.

If you understand that then why you still believe that signal generators regulate power, not voltage?

[Yansi]

Many reason which lead me to believe many things.

I have even thanked you guys for helping me understand some facts and better apply them, are you going to offend me for that now or what? 

[ogden]

Many reason which lead me to believe many things.

I have even thanked you guys for helping me understand some facts and better apply them, are you going to offend me for that now or what?

No offense indeed (because it's obvious that you don't have experience regarding subject), but you offended me by implying that I do not know how generators regulate: "If you think of using only a diode detector, i.e. voltage measurement, then it just won't work with non-linear loads that tend to clamp voltage to a certain level."

[Yansi]

But that is true. It will not work if the ALC detection point will be at the load directly. However I could not come up with  the idea to use the detection point of the ALC as a zero impedance voltage source point and then connect the load to that point using a convenient 50ohm series resistor. 

In this case it makes sense to measure just the voltage before the 50ohm output resistor.

But it also kind of screws my plan of +20dBm output. If I would use +20dBm P1dB amplifier (I planned to use OnSemi MMG3H21NT1 MMIC amp), then I would get only +14dBm out, otherwise the amp would become grossly overdriven.

So:
1) either I will find a suitable MMIC amp that would do a +26dBm or more on the output at the whole range of 400k to 150MHz. (Can anybody recommend a specific one?)
2) or I will have to settle with a 13dBm output only which I find not enough.

There is also always other possibility, for example to make a discrete amplifier... but that is a task for an experience person, certainly not me. So back to looking for a 0.4W+  MMIC that can be run from DC upwards (150MHz). 

[Kleinstein]

The ALC loop is relatively slow. So the point where the ALC is measuring is not really 0 Ohms.

For the relevant high frequency the impedance is still unchanged it is only the added load to the ALC sense circuit that lowers the impedance a little. A suitable configuration is more like an asymmetric power splitter from the output amplifier with some loss (e.g. 2-3 dB) for the output and quite some damping (e.g. 12 dB) towards the ALC circuit.  So the loss in output power can be smaller than 6 dB. Some damping from the power splitter can actually be a good idea, to isolate the amplifier from possible load mismatch - one usually wants a generator to survive an open output and also a open end cable.

The main thing that changes with the ALC is the amplitude with a non matched output. It would reduce the amplitude with an open output and increase it with too low an load impedance.

[Yansi]

Okay, for small signal analysis it is not 0 ohm, however I think for slow load changes, the node really behaves as an AC voltage source with zero internal resistance.

Or how would you for example explain the Marconi output stage, where I can clearly see a 50ohm resistor in the output path - meaning an assumption was made, that the sensed node at the output of TR10 has 0ohm impedance? The sensing diode matched pair is visible on the screen capture too.

//Btw, what is the purpose of D8 to D10? Kind of interesting construction considering also the two RFCs - one being 2.4uH and the other 1mH. The amp seems to be a wide band from 80kHz up to a GHz.

[yl3akb]

But that is true. It will not work if the ALC detection point will be at the load directly. However I could not come up with  the idea to use the detection point of the ALC as a zero impedance voltage source point and then connect the load to that point using a convenient 50ohm series resistor. 

In this case it makes sense to measure just the voltage before the 50ohm output resistor.

But it also kind of screws my plan of +20dBm output. If I would use +20dBm P1dB amplifier (I planned to use OnSemi MMG3H21NT1 MMIC amp), then I would get only +14dBm out, otherwise the amp would become grossly overdriven.

So:
1) either I will find a suitable MMIC amp that would do a +26dBm or more on the output at the whole range of 400k to 150MHz. (Can anybody recommend a specific one?)
2) or I will have to settle with a 13dBm output only which I find not enough.

There is also always other possibility, for example to make a discrete amplifier... but that is a task for an experience person, certainly not me. So back to looking for a 0.4W+  MMIC that can be run from DC upwards (150MHz). 

Here is nice summary about signal generator output stage, which also describes voltage source+50ohm resistor concept. Why dont You just use switchable PA (with good gain-temp. stability) at the output for high levels, like shown in the document?
http://aeroflex-cdip.ru/eng/pdf/nav-750-an2.pdf

[Yansi]

Well that looks as a viable idea! ... however requiring additional relay to the path.  But would help with a lot of things. As it seems, DC-to-Daylight MMIC amps with more like 20dBm P1dB are unobtainium or only for those with higher income.

The other solution left is to try building a discrete amp. Replicating the output stage from the Marconi does not seem to bu that much of an problem, at least it would be a nice experiment. However would must first have equipment to be able to fully characterize it. Sigh.

[rhb]

This and related threads have got me to looking at eBay and AliExpress offerings.  Which leads in turn to the question, how good an instrument can one build using cheap Chinese modules based on chip vendor reference designs?  This seems to me particularly useful in light of the fact that many instruments incorporate the same functional elements.  So a bunch of modules and SMA jumpers would allow someone to set up an instrument for a single test and then reuse the parts for something different the next time.

I'm old now and can finally square buying toys with my conscience.  But I have painful memories of trying to build a transceiver from scratch with nothing but a 5 MHz recurrent sweep scope and a VOM.  Oh, how I envied the EEs who could use the class lab gear.

[DC1MC]

This is my plan as well, get modules implementing reference designs on well known signal generator chips and build around them.
I pray that our Chinese friends didn't apply too many of their "optimize for cost" rules to them or at least let the pads to solder your own quality stuff there.

[Yansi]

Not only optimized for cost, but usually very bad in terms of PCB layout.  I have some nasty examples of chinese RF pcb routings, but I'd leave that for a separate thread.

If we talk about the chinese modules - does anybody know what MMICs they use on these 0.5W RF amplifier modules? I couldn't figure that out.

https://www.ebay.com/itm/1PC-0-5W-40-1500MHz-RF-amplifier-40-1500MHz-0-5W-13dB-gain/141981673312?hash=item210ec46760:g:OdoAAOSwiYFXKfyJ
https://www.ebay.com/itm/50MHz-1GHz-0-5W-Broadband-RF-Power-Amplifier-Radio-Signal-Amplifier/181797531492?hash=item2a53fa2f64:g:losAAOSwyQtVnzfc

and then those modules (they seem to have a discrete transistor output stage, not a MMIC in there):
https://www.ebay.com/itm/1PC-2W-RF-wideband-power-amplifier-1-930MHz-2-0W/122061596083?epid=881797178&hash=item1c6b7025b3:g:jEUAAOSwIgNXmLZF

[Yansi]

I may have made a rather stupid thing. I have replicated the RF output stage from the Marconi generator.  But used a bit different components.  The RF transistor is BFG193 (the beefiest SOT223 one I could find in my garbage pile).  Biased Ic 45mA , Uce 8V.  I think that is the reasonable maximum for him.

I would like to test this using for example a BFG253 - much beefier one, but I don't have any yet.

The question about the three series connected diodes still remains. Does anybody know their purpose? The schematic of my test gizmo is almost the same, as the Marconi.

I will test the circuit in a moment. Unfortunately, my  lab is still lacking any kind of RF generator, so for further proper testing it will have to wait till I get some proper tools for that. At least I will try to test it at multiple frequencies.

[Yansi]

To my biggest surprise, that damned thing works 

Testing it so far using only my 118MHz LC oscillator, I am able to get about 17.5dB of gain and almost 20dBm output power.

I have found a bunch of BFG541 - a little bit more beefy transistor. So I have beefed up the supply voltage to 12V (becoming close to the BFG541 limit... oops) so that the Ic bias goes up to 70mA.   Now the beefed up amplifier is giving 23dBm. 200mW! Nice!

For the RF generator using the AD9951, I would need it to deliver 200mW into 100ohm load in the whole range of 400kHz up to 150MHz. Which may seem very possible, using something as BFG235.

I would be also interested to know, how to estimate what kind of bias do I need to achieve a specific amount of output power. 

I will put the amplifier through a more thorough test later - to measure the gain dependence on frequency and then the P1dB over tthe frequency range. With my current home rf test equipment setup, I am not able to do it unfortunately. 

[rhb]

The question about the three series connected diodes still remains. Does anybody know their purpose? The schematic of my test gizmo is almost the same, as the Marconi.

It took a bit of time for me to locate the schematic in the Marconi manual.  Ahh, the days when they told you everything.  Though it's a lot easier to flip through paper than a PDF.

The function of those is to hold the collector of the Darlington pair at 12.9 V or higher.  Consider the case of TR9 at Vce of 0.2 V.  They do a similar setup in the PS for the HP 8601A voltage regulators using 2 diodes.  The voltage drop is tightly controlled, but without the noise of a zener in reverse breakdown.

That I happen to know this is a strong argument for enduring the aggravation of fixing old gear instead of buying new.  It *is* educational.

[phenol]

if you are talking about the string of 3 diodes (d8-d10), those are clamping the output and act as protection against transients. There’s another clamp (d21) placed after c30.

[Yansi]

The function of those is to hold the collector of the Darlington pair at 12.9 V or higher.  Consider the case of TR9 at Vce of 0.2 V.  They do a similar setup in the PS for the HP 8601A voltage regulators using 2 diodes.  The voltage drop is tightly controlled, but without the noise of a zener in reverse breakdown.

Errr... what darlington pair? Maybe you look at a different diodes.

I have already posted the part of the schematic in the thread, you might have overlooked And also the diodes are in the schematic of my test gizmo.

Yes, they are obviously clamping the voltage to Vcc + 1.8V or so. But that does not make much sense for me, as to why the clamp is connected into the rf choke split point.  That means that the clamp will behave non-linear with frequency. The higher the frequency, the larger the clamping voltage.  At low frequency (the amp in the Marconi does the whole range from 80kHz up) the larger valued 1mH choke will act as the main one. However the swing will become very limited by the diode string.
If I remember correctly, the Marconi is also 20dBm output, so it needs 4,5Vrms  voltage at the collector. That kind of contradicts what the clamp does there.   

How is one supposed to estimate what kind of bias (Uce x Ic)  is needed for a transistor to achieve a given amount of power into a load?

[rhb]

Sorry, it's not a Darlington.   I just assumed that from the double emitter symbol which I had not seen before.  It's a 4 GHz transistor with 2 emitter leads.  I'd never seen that before.

I did not notice any schematic other than @phenol's link to the manual.

The function of the diodes is to limit the current through R39 to ~210 mA ((3* 0.7)/10).  If the voltage drop across R39 exceeds ~2.0 volts the diodes conduct.

[DC1MC]

I'll take a shot on the bias vs. delivered power.

I assume that we're talking here about class A amplifiers.

So assuming the transistor it's fully linear (it isn't) you set the biasing point to burn without signal exactly 50% of the power needed. The input signals should swing the Ic between 0 - 2xIcIdle.

But of course, all perfect transistors are sold-out and you have to do with you have in the drawer. And then discover that on very low and and very high currents the guys have a lot of nonlinearity, so you have to burn much more energy in idle mode to move the low further away from 0 and also select a transistor with a high enough dissipated power and beta to not "suffocate" at high currents.
That means no hard rules, a lot of experiments and lot sorting is needed, that somehow explains the prices of good signal generators.
 

[Yansi]

Sorry, it's not a Darlington.   I just assumed that from the double emitter symbol which I had not seen before.  It's a 4 GHz transistor with 2 emitter leads.  I'd never seen that before.

I did not notice any schematic other than @phenol's link to the manual.

The function of the diodes is to limit the current through R39 to ~210 mA ((3* 0.7)/10).  If the voltage drop across R39 exceeds ~2.0 volts the diodes conduct.

Still do not understand your explanation. The diodes simply can not conduct when the R39 voltage drop rises. They are reverse biased all the time. Except when the node between the RF chokes swings about 1.8V above supply voltage (+15V).

But then I do not understand how is that power stage able to deliver  4.5Vrms (13Vpp) of swing into the load at lower frequencies, where the bigger 1mH choke is the significant one for the operation. The collector voltage has to swing around the +15V rail, in between +9 to +21V.  (I have omitted the R39 drop, which is by the looks of it 0.9V - the stage is biased at 15V 90mA)

I'll take a shot on the bias vs. delivered power.

I assume that we're talking here about class A amplifiers.

So assuming the transistor it's fully linear (it isn't) you set the biasing point to burn without signal exactly 50% of the power needed. The input signals should swing the Ic between 0 - 2xIcIdle.

But of course, all perfect transistors are sold-out and you have to do with you have in the drawer. And then discover that on very low and and very high currents the guys have a lot of nonlinearity, so you have to burn much more energy in idle mode to move the low further away from 0 and also select a transistor with a high enough dissipated power and beta to not "suffocate" at high currents.
That means no hard rules, a lot of experiments and lot sorting is needed, that somehow explains the prices of good signal generators.

That's what I have thought. In reality, you need to have it operating deeply in class A to obtain the best linearity. But I think there are other factors t consider: For example at 0.2W into 100ohm, I need a peak current of 64mA. The bias therefore has to be larger than 64mA and the supply voltage bigger than the peak voltage value expected at the load. The C of the NPN then sees twice the Udc. That makes indeed sense. (The RF stage in the Marconi is biased 90mA, supply voltage 15V)

[phenol]

iirc, the instrument delivers 13dbm max into 50 ohms

[Yansi]

Yea, I have just noticed that I dunno why I was thinking still about 20dBm.  With 40mW into 100ohms, that diode limiter makes sense and just barely makes the voltage swing available for the 13dBm output. There is not much margin left, if any.

[rhb]

Ooops.  Still not awake then  :-(   Up rather later than normal.

The diode transition capacitance decreases as the reverse voltage increases.  So L8 and L9 form series resonant circuits whose tuning varies with the current through R39. I don't have a clear mental concept of what the ac behavior of such an arrangement looks like.   This rather begs for some SPICE runs.   From when it was designed I'd guess that this was arrived at empirically to suppress oscillation.

[Yansi]

I'd believe it is a clamp.  But with only 40mW output into 100ohms it makes sense. I was thinking the whole time the Marconi 2018A was specced at 20dBm output. Which is not true. My fault there.

So some really nice solutions for the ALC are coming together.  For just 13dBm (20mW) output, one could get out easily with just the 20dBm+ P1dB MMIC from Onsemi (MMG3H21NT1, readily available from Mouser for reasonable price).  (you need 16dBm into 100ohm, but I'd rather let the MMIC work into its rated load of 50ohms, so then you need 19dBm to obtain the same 13dBm at the output. The other 100ohm load will be the ALC detector input)

But still I don't want to give up on those 20dBm. Not that easily. I'd like to at least try making a power stage using a discrete transistor. However it is a bit complicated for me, as I do not have the required RF test equipment in my lab to verify the performance of such an amplifier. Having occasional access to a local RF lab at work (or maybe will try local university?) is a rather lengthy process.

[Yansi]

I could not help myself,  but due to the lack of proper PIN diode quad (BAP64Q), I must have tried something. I took an old analog TV tuner a grabbed the PIN diodes from it: I got three BA283 diodes.

So I breadborded the following circuit:




Where R1 = 2k2, R2 = 1k, R3 = 2k7. All diodes BA283, all capacitors 100nF. L1 some kind of RF choke from the same tuner as the PINs are.

I have yet again used my crusty trusty 118MHz LO source and measured the attenuation as a function of control voltage. The reference voltage V+ was 2.65V. I swept the control voltage from 0 to 5V.



What I quickly found very interesting is the hump on the attenuation plot. The attenuation is not monotonic function of the control voltage. Why is that? This makes it of very limited range usable for any kind of servo loop. What might went wrong that I got such a curve?

The only positive thing about the bread-borded rats nest I can say is it has only about 0.7dB insertion loss minimum and a decent attenuation of 57dB maximum with zero control voltage, both at 118MHz, 0dBm input level.

[DC1MC]

I'd say grab a quad or find another tuner , for a triplet attenuator the results are pretty OK, also have a look on this article:
http://www.mwrf.com/semiconductor/diode-quad-foundation-pin-diode-attenuator

[Yansi]

So you say the curve gets better, if the diodes will be paired and in the quad configuration?

//EDIT: Here is the PIN's nest...

[ogden]

//EDIT: Here is the PIN's nest...

You shall consider programmable (digital step) RF attenuator as well.

[DC1MC]

Generate the voltage with a DAC, and presto, programmable RF attenuator  . 

[Yansi]

I think I will rather not. These come usually with only very limited attenuation ranges (16/32 dB typical is what I have seen), secondly they usually can not work from DC signals and I would guess they will degrade the linearity more, than a single PIN quad attenuator (but just a guess). The biggest disadvantage is their attenuation step is not small enough. Typically 0.5dB. That is not what I want.  And of course the cost of a PIN quad is insignificant fraction of a $, compared to a digital controlled step attenuators.

Using the pin quad I can easily achieve much larger attenuation range while not being limited to attenuation steps - as the PIN att. is analog voltage controlled. Using a sensible design considerations, I will be able to get easily better than 0.1dB calibrated resolution of output amplitude.

I do not see much if any advantages of using a digital step attenuator. Or do you have any specific part numbers to consider?

//Yes DC1MC, that is my plan the whole time   But not only DAC, but a whole ALC loop.

[phenol]

your band switching diodes are not necessarily pin diodes. The datasheet has no mention of carrier lifetime, i layer thickness, etc. These parameters limit the lower frequency range before the onset of non-linear behavior (rectification) and severe IIP3 degradation. There are special pin diodes with thick intrinsic layer for sub-MHz operation. I’v seen people use strings of 1N4007 as pin attenuators and switches at HF frequencies... Anyway, there’s a good reason why marconi sg has two paths-HF and LF- with two different leveling mechanisms.
A properly compensated dual-gate mosfet may work as an early small signal gain controlled stage with a range of more than 20-30 db of(hopefully) linear performance.

[yl3akb]

I think I will rather not. These come usually with only very limited attenuation ranges (16/32 dB typical is what I have seen), secondly they usually can not work from DC signals and I would guess they will degrade the linearity more, than a single PIN quad attenuator (but just a guess). The biggest disadvantage is their attenuation step is not small enough. Typically 0.5dB. That is not what I want.  And of course the cost of a PIN quad is insignificant fraction of a $, compared to a digital controlled step attenuators.

Using the pin quad I can easily achieve much larger attenuation range while not being limited to attenuation steps - as the PIN att. is analog voltage controlled. Using a sensible design considerations, I will be able to get easily better than 0.1dB calibrated resolution of output amplitude.

I do not see much if any advantages of using a digital step attenuator. Or do you have any specific part numbers to consider?

//Yes DC1MC, that is my plan the whole time   But not only DAC, but a whole ALC loop.

Why do You need range larger than 20..30dB? Cant You just switch in those 20 dB attenuators in, when needed? Also, small nonlinearity (no dips like that though) should be taken care by negative feedback.

[Yansi]

Well I have thought about that too.  I have found this PDF file from Vishay, that seems to state that BA283 are example of a PIN diode. See page 4, the "PIN diode" paragraph: https://www.vishay.com/docs/84078/84078.pdf 

In the BA283 datasheet, it is mentioned as a switching diode for 50-1000 MHz, which indirectly states what the carrier lifetime in the PIN might be.  Maybe the intrinsic region in these diodes is not that wide, but who knows.

Compensated dual gate mosfet you say? That seems interesting too. Because if I will be able to obtain a bunch of T1-1T-KK81 transformers, I will then be able to go from 80kHz or so with the DDS, but the the PIN quad BAP64Q will be useless for this low frequency end.  Using the dual gate mosfet approach this still may be possible.

Can you recommend any specific appnotes regarding such "compensated mosfet" circuits? I have  readily available quite a lot BF998 dual-gate MOS-FETs for making experiments, so I could even prototype that out quickly.


yl3akb: Because I want to have as little relay attenuator stages as possible.  But sure 20-30dB range at the ALC might be what is needed.  With a 30dBm ALC range and +13dBm maximum output, I will be able to go down to -77dBm using just two 30dB relay
pads.  Or down to -85dBm from +20dBm (which would be a lot nicer to have) with 35dB ALC range and two 35dB pads.  It all depends on measurements yet to be done.

[ogden]

I think I will rather not. These come usually with only very limited attenuation ranges (16/32 dB typical is what I have seen), secondly they usually can not work from DC signals and I would guess they will degrade the linearity more, than a single PIN quad attenuator (but just a guess). The biggest disadvantage is their attenuation step is not small enough. Typically 0.5dB. That is not what I want.  And of course the cost of a PIN quad is insignificant fraction of a $, compared to a digital controlled step attenuators.

Digital attenuators exist for a reason. Indeed many operate from DC, are quite linear and better matched than pin diodes.

http://www.analog.com/en/products/rf-microwave/attenuators/digital-step-attenuators.html

Using the pin quad I can easily achieve much larger attenuation range while not being limited to attenuation steps - as the PIN att.

I would consider to digitally ALC-regulate using DAC_Rset like shown in this appnote:

http://www.analog.com/media/en/technical-documentation/application-notes/AN-423.pdf

If 10dB range is achievable using such approach, then add external 10, 20, 40 steps and that's it.

[phenol]

By 'compensated' i really mean one having a reasonably flat gain across your range of frequencies such that the ALC loop stays in stable regulation. This means a wide-band load in the drain with ample resistive damping, if needed. BF998 may work, but something self-biased like BF1105 or similar is probably easier to control.
BF998, BF992 and the likes are frequently used in HF receiver IF strips with automatic gain control.

[RadioNerd]

How about something like that:
https://www.digikey.com/product-detail/en/m-a-com-technology-solutions/MAAVSS0006TR-3000/1465-1300-1-ND/4429997

It should be able to cover 20 dB with reasonable (log-)linearity

[Yansi]

It seems there is a large variety of how one could approach the output leveling. Lets make a summy and write the obvious  dis/advantages.

The table was made based on the following assumptions:

• +20dBm max output power
• At least down to -70dBm
• Omron G6K-2F-Y relays for the step ATT, assuming no bigger step than about 30-35dB will be possible due to not the best isolation (40dB @100MHz)
• I want the best bang for the buck (keeping the cost the lowest without seriously degrading performance)
• Not requiring any too obscure parts
• Wanting lowest possible bottom frequency

Solution			Bottom Freq			ALC Range			Advantages	Disadvantages
PIN ATT (BAP64Q)			300 kHz			>40dB			+ Cheap ($ Fraction) + Very high attenuation range (50dB) + Least amount of relays required: Probably just two 30-35dB steps (downto -70..85dBm) + Voltage controlled	- Only down to 0.3MHz
DDS DAC Bias tweak			from DC			10dB			+ No other attenuator components (apart from shitton of relays)	- Likely screws SNR/SFDR, DDS DAC not operating with optimal current - Limited range of only about 10dB ALC range - Large number of attenuator relays: At least 4, likely 5 (steps 10 20 20 30 30dB) - A sort of hack of the Rset pin, another OPAMP required
FET Attenuator (MAAVSS0006)			from DC			20dB			+ Voltage controlled	- Starting to be a bit on the expensive side ($3+) - Sort of limited range of 20dB - Higher step attenuator relay count: At least 3 steps (20 30 30dB) downto -80dBm - Control voltage needs to be NEGATIVE, but could be hacked for positive too
Dual gate NMOS			almost from DC			maybe 25dB			+ Cheap + Voltage controlled	- More complicated design, thorough circuit testing required - Higher step attenuator relay count: At least 3 steps
Digital step attenuator			maybe from DC			< 32dB			+ Good 50ohm match, respectable IP3	- Can be good deal expensive - Step typically of 0.5dB - In steps, not fully variable attenuation - AM modulation not possible using this ATT

To be honest, it is quite hard to pick the poison. Some of the requirements are quite against each other. But we are not building $10.000 instrument, but just a decent toy. TBH I could live with only +13dBm output power, and even 400kHz bottom frequency. But I will try to do my best about it.
So far after reviewing the available solutions, the PIN ATT is still very nice solution.  The DDS DAC bias tweak is just a rather ugly hack and the digital step attenuator a nonsense.

However the FET attenuator is a bit more interesting, as the ALC dynamic range may be up to 25dB, requiring only 3 attenuator relays (20, 30, 30 dB steps), offering +20 down to -80dBm and operation from DC. This would let me use the MiniCircuits T1-1T-KK81 balun and achieve operation from 80kHz, which would be quite awesome.

So still can not decide between the less evil: PIN ATT or the Macom FET ATT.  The PIN ATT clearly will not operate down to DC.  But thinking about it, the Macom FET atten. solution requires just one additional relay, which is not that big of a deal, so is the price of that FET device. The price of the balun is however another story, as those TC1-1T+ mini transformers can be obtained very cheap. But having the bottom frequency just 80kHz would be handy, considering I might use the AD9910 next time. That is a 1Gsps DDS (up to 400MHz) and good luck finding such a very wideband balun (from below 100kHz) for that one.

So probably I should try attacking the solution with the Macom FET attenuator MAAVSS0006. This device is not just as much obscure it seems. It is also readily available from Mouser. (Sorry, no Digikey here guys). I will leave the BAP64Q PIN Quad for the faster 1GSps DDS.

Thanks RadioNerd for mentioning the MAAVSS0006, a nice find.

Bottomline: I know there are many more solutions to this, for example making a multi-path design separating all the LF stuff from the RF and switching between the two, but for now I will start with something easier with higher possibility of success.

[phenol]

as expected, linearity craps out at certain bias voltages with that part.  you should really measure the level of the output harmonics

[Yansi]

With what part? You mean the Macom FET thingy?  Those IP3 and P1dB have a very scary dip around 2.5V for sure. But I will try to design the voltage levels at the attenuator as such there will be enough headroom left or so I hope.

[ogden]

Most of potential choices are voltage-controlled. Maybe it's good idea to prototype PIN, FET and bias control, compare performance.

Why do you plan to use (expensive) relays for step attenuator switching? At those frequencies you can use virtually any pair of RF solid state switch, leakage is not an issue at all. After all you are not building TR switch or preselector. Even if -30dB will leak around attenuator - it's just 0.1% of added power, most likely your PI attenuator error will be worse than that

[Yansi]

Why expensive? Those Omrons G6K-2F-Y can be sourced for as low as $1.5 a piece. I do not think a DPDT RF switch will cost much lower than that, won't it?

I also have concerns about using active devices in the step attenuator: Doesn't it worsen the noise figure?  I think it will become an issue if one attempts the microvolt region down there. I mean my -80dBm is like about 100uV if I am correct, but still... What do you guys think about that?

If -30dB leaks around 30dB attenuator, the error is not 0.1%, but 50% error. The result will  be 27dB attenuation. I think that would be pretty bad.

For today, I have something special. I've managed a meeting at a local university in a lab, and some keen guy have done a quick measurement of S21 of the wide band amplifier that I have made with the NPN transistor, inspired by the Marconi output stage design.

We have done a sweep from 100kHz up to 1GHz. The gain drops off rather quickly, as the frequency increases. Please note that the measurement was done without the compensating bypass caps across the emitter resistors. Unfortunately the second screen capture with the caps got somehow lost in the transfer and there was no spare time to repeat the measurement. So maybe next time. But as far as I remember, the gain dropped a bit slower, with a two 10pF caps installed. (The transistor has physically two emitter leads).

Those ripples on the gain are quite puzzling for me, but they are supposed to be due to impedance mismatch (so was I told by the guy). We've used a rather  long coax cables for the measurement setup (maybe like 1m cables?). The measurement setup was calibrated for flat response, sure.

The input power was set that the output will be about +13dBm near 100MHz, as the schematic includes the same diode clamp topology as the Marconi. I have copied that just to see it's influence on the amp.  Next time I also plan to try to measure P1dB of that, at least for a few frequencies.  There is unfortunately no simple way of  having an easy automated P1dB measurement across a frequency span.

[ogden]

If -30dB leaks around 30dB attenuator, the error is not 0.1%, but 50% error. The result will  be 27dB attenuation. I think that would be pretty bad.

Two switches are needed, so leakage will be -60dB not -30

Those ripples on the gain are quite puzzling for me, but they are supposed to be due to impedance mismatch (so was I told by the guy).

Those ripples are cable reflections indeed. I wonder why he did not calibrate setup for measurement plane at the end of the cables! Knowing that you are getting cable reflections while measuring amplifier is kinda   Next time ask him to properly calibrate setup. At least add external 6dB attenuator at the amp input - if they for some reason do not calibrate VNA (rofl)

[yl3akb]

It looks measurement is taken with scalar network analyzer (or at least in scalar mode, if there is such thing). And with scalar analyzer it is not possible to calibrate port match, only do normalization, which will not solve the ripple issue.

[Yansi]

The calibration plane was right at the end of the cables. It was measured by a SA+TG, as I have advertised in one of the previous posts.

Btw, what would the external attenuator on the amp input help with? 

[ogden]

The calibration plane was right at the end of the cables. It was measured by a SA+TG, as I have advertised in one of the previous posts.

Ups, I missed SA+TG. Sorry

Btw, what would the external attenuator on the amp input help with?

It will act as impedance matching pad between cable and amp input.

[Yansi]

Okay, I get that. In that case, shouldn't connecting a pad also directly on the output of the measured amplifier help reducing the spurious resonances? We have had an attenuator at the amplifier output, to protect the SA (it was only 20dBm rated and the amp can definitely deliver more than that), but it was connected at the end of the coax cable, right at the SA input.

On a different note: Maybe it's a time to start making and doing, instead of theoretical discussing. So for the weekend, I will make a PCB module to be populated with the AD9951 (9954) and then will start working on the ALC module.

I want to take a modular approach for this, at least to begin with that.  After all parts will be fully working, I'll proceed to design a final PCB. I think this approach is better, as I could easily evaluate number of different solutions. For example compare ALC design using a FET or PIN attenuator.

[ogden]

Okay, I get that. In that case, shouldn't connecting a pad also directly on the output of the measured amplifier help reducing the spurious resonances? We have had an attenuator at the amplifier output, to protect the SA (it was only 20dBm rated and the amp can definitely deliver more than that), but it was connected at the end of the coax cable, right at the SA input.

For scalar measurements you better put attenuators or matching pads close to DUT, not at the other end of the cable where instrument provides correct impedance already. Obviously with VNA it's opposite - you do not try to correct impedance mismatch because you would want to measure it with S11 and S22.

[Yansi]

Roger that.    I'll try to get to a VNA somewhere.

Meanwhile I got an idea for a next (but maybe a bit more complex and interesting) project: I got a shitton of MiniCircuits Directional Couplers ZEDC-15-2B (like 10 of them) I hamstered from an old telcom equipment I have dismantled. Maybe four of those together with my RF generator could be used to make a nice diy VNA. One would only need to add a few RF switches and a receiver (I'd probably go the SDR route). 

[phenol]

You mentioned you had AD9910 in your drawer. Why don’t you start with it instead?
Also, if you give a damn about phase noise performance, the analog supply voltages have to be very clean, even more so if the internal PLL clock multiplier is engaged. For example, i saw that LM317 regulator was producing prominent side bands that tended to shrink when insanely big caps were added on the output.
All in all, i decided to not use the PLL of AD9910 due to degraded PN performance and sensitivity to power supply noise but inject the 1GHz clock externally. The voltage regulators are some sort of AD stuff meant for VCO power supplies.

[Yansi]

I have both a piece of AD9951 and AD9910. Bought them quite a while ago. I'd start with the 9951. It is cheaper and better for my training and also currently fits the basic needs.

Regarding the AD9910.. I saw that AD9957 is also 1Gsps, but has a digital I-Q modulator built in, with a parallel data inputs. It might be worth playing with this one instead.  One could make quite interesting generator capable of a ton of different modulations. And I'd like to improve my skills with FPGA / VHDL, so maybe I will leave the 9910 in my drawer and get a 9957 instead.   

Do you think the AD9951 is also that much sensitive to power supply noise? Currently I am designing a small testing board (not a final one) for it and planned to use a generic 1117 voltage regulator for the 1V8 supply rail,  while the input for the board being a generic 5V supply from anywhere.  I will post a schematic for a review once it will be finished.

As I wanted the final generator to be lockable on external 10MHz reference, it would make sense to use an external PLL anyway, as the internal one can't work with lower than 20MHz reference clock. External PLL could be used to produce a clean 400MHz reference.

[phenol]

It is going to be sensitive to power supply noise if the internal PLL is enabled. I guess it would be fine with a generic 1117 and an external reference clock, but you still have to exercise great care with the external PLL source as it WILL be sensitive to any sort of noise that can modulate the VCO. You could use capacitive multipliers to filter the power for the sensitive parts of the reference source.
I went medieval on it and made an analog-only 10x multiplier that multiplies an external 100MHz OCXO signal in 5x and 2x stages to clock AD9910. 3 different versions of it. No PLLs, no VCOs.
One important feature of AD9951 that is missing in AD9910 is the DACBP pin. The external capacitor connected to that pin filters the bandgap DAC reference. The unfiltered bandgap noise manifests itself as somewhat elevated AM noise in AD9910...

[Yansi]

Looking through the datasheets, even the AD9957 does not have the DACBP pin. Doh! Hopefully it ain't not that bad.

Currently designing the oscillator section on the AD9951/4 module, I have stumbled across this in the documentation. It seems they (Analog Devices) know well the internal PLL is junk. The datasheets tells you exactly to use external REFCLK when higher performance is required.

For best phase noise performance, a clean, stable clock with a high slew rate should be used to drive the REFCLK pin and bypass the multiplier.

[Yansi]

Finally, the AD9951/9954 module is done.  I have put in a lot more time than originally intended, but whatever... Not the best of layouts, but maybe better than the Chinese ones. I think it is good enough for a 2-layer jobbie.

Have managed to squeeze almost all functionality on that little 50x50mm board, except the COMParator in the 9954 that I don't care of and the XTAL_OUT pin that likely won]t ever be needed, as it will likely be supplied using the REF input with external CLK source.

If you see any major fail in there, please scream. I will have it sent to be manufactured on Tuesday otherwise.

//EDIT: Corrected schematic file.

[ogden]

You shall read AN-837 regarding filter layout. Also line between filter and socket does lot look like 50 Ohm conductor-backed coplanar waveguide  (CBCPW), but luckily it's short.

http://www.analog.com/media/en/technical-documentation/application-notes/351016224AN_837.pdf?doc=cn0304.pdf

http://wcalc.sourceforge.net/cgi-bin/coplanar.cgi

[Yansi]

Why doesn't it look like a 50ohm CBCPW? 

Putting the dimensions I used into your calculator yields 50.8 ohm characteristic impedance, so what? I think you can't make that much better, considering manufacturing tolerances.   I don't get it where you see the problem. (H=1.5, W=1.26, S=0.25, T=0.035, eps_r=4.7)
 
But thanks for mentioning, you have forced me to to look up what material exactly will the manufacturer use. The eps_r is slightly lower than I have expected (4.4 actually), so I will correct my design for that. It would be 52ohms otherwise, which I don't think would be a major problem of any sort.

I have seen that exact filter app note somewhere.  It is nice, but I have followed the evaluation board for that AD9951. I guess making the shunt caps symmetrical would help, however it would mess the filter a bit up, as I could not combine the specified values using two caps  in parallel.  Currently I am not willing to spend time fiddling and redesigning the filter.

Regarding the last paragraphs of AN-837 linked above, I have done this way:
 - I have solid uninterrupted ground plane below all RF circuitry. I have also top layer ground plane near the filter, as they are suggesting.
 - Capacitors unfortunately not split, due to reasons stated above. (not willing to spend time redesigning the filter to account for slightly changed capacitance not being able to combine the required ones from two caps). Multiple vias used on the ground lead of the shunt capacitors.
- Regarding placement of filter components - didn't exactly try to make it crowded, but I don't think that having the components far apart will help with anything. In fact I think it get worse.
 - Components ... well. I will use whatever will I be able to find. At least for the prototype.
 - Traces external to the filter when possible are 50ohm (at least on the output side)

Do you have any specific ideas how to make the filter layout better?

//EDIT: Fixed a lot of typos. Added dimensions of the CBCPW.

[ogden]

Why doesn't it look like a 50ohm CBCPW? 

Putting the dimensions I used into your calculator yields 50.8 ohm characteristic impedance, so what?

It just seemed to me that S is too small compared to trace width. If you verified and it's 50 +/- few ohms then it's completely fine, end of the story. - Especially for length of the track which is close to nothing.

not willing to spend time redesigning the filter

Sure it is not that important, especially for first prototype. Just wanted to let you know such article exist. After all frequencies they fight in the article are above 400MHz.

Do you have any specific ideas how to make the filter layout better?

It's good already. You can possibly flip it vertically so power trace is not so close to filter components.

[Yansi]

Ok then, I will get it manufactured. We'll see how good or bad it will be.

Now a rather lengthy post, sorry for that. But many thanks for reading throuh!

Meanwhile, I started prototyping the ALC module. I am not sure what the best topology should be and I'd like to discuss that a bit.

First we need to solve for the DDS output signal level: The DDS dac is set at it's nominal current of 10mA. As the loading impedance is 50ohm (differentially, using a proper balun trnasformer), I will get a 500mV peak-peak signal into the 50ohm load. (Each leg of the DAC drives a 25ohm load, meaning a maximum 250mV per leg.)  That means I will get about 1.25mW (+1dBm) of power out of the DDS.

Now considering the insertion loss both of the balun (which can be up to 3dB at the edge of the band) and considering insertion loss of the filter which is currently unknown (guessing few dB will be lost in there to), I will likely end up with something in the range of -1dBm downto -5dBm. But we'll measure that later exactly.

To ease the ALC design, currently I will be fine with getting only +13dBm out maximum, as I can use general purpose MMIC ICs for that sort of range. In fact, I need a +19dBm or more of output from the MMIC. Why?  The output has got a 50ohm series resistor. That means the MMIC will need to deliver 40mW (+16dBm) into 100ohm load.  Now the MMIC is loaded only with a 100ohm load, I will add a second load of 100ohm, which will be the input of the log. detector. Now the MMIC is loaded properly with 50ohm, but needs to deliver 4 times the output power of the generator, i.e. +19dBm (80mW).

So I need to be able to amplify those -1 downto -5dBm  to +19dBm.   So I need at least 24dB of gain. Supposed the output MMIC (likely SGA6389Z) will have a 15dB of gain, I will need a second amplifier delivering the missing 9dB (will likely use a MMIC with a higher gain than that and add a fixed attenuator). So far so good.

The question is: Should I put the variable attenuator in front of the two amplifier stages, or should I put it in between?
I see both advantages and disadvantages for that. Let my try formulate those I came up with:

MMIC in front of the amps:
 - both amps working full gain even with the smallest amplitude. As the overall gain of the MMICs combined will be from 30 to 35dB, I guess this will give a worse noise figure. Question is, does it matter so much here? We are working with mV signal levels, not uV.
 + the first amplifier will work with the least amount of signal level possible, giving least amount of distortion.

MMIC in between the AMPS
 - first stage amplifier working with high signal level, as it both must feed the second stage and also cover the insertion loss of the variable attenuator -> higher distortion. (it seems the first amp will need to give up to +8dBm continually in this case)
 + probably better noise figure, as the signal levels will be higher.

I do not have enough experience to judge here, but guessing noise figure is not much in play here, as we are working with quite large signals anyways. So maybe the the first option (variable attenuator in front of both amps) is the right to choose here. Signal purity (low distortion) should be preferred, rather than a few dB of added noise. What do you think about that?

I can now clearly see, why the Marconi generator has the variable attenuators distributed in between all amplifier stages. It combines the advantages of both solutions.  But I think it will be enough in here to use a single variable attenuator in front of both amplifier stages.

Here's the schematic I am working on. The first stage is MAR-3SM - chosen based on the P1dB requirement - it's the only one I have here that will be sufficient, apart from an overkill like ERA-5 (I have those too). The PA will be SGA6389Z (now obsolete, but who cares for one off projects), I can get those, or the Onsemi MMG3H21NT1 (in that case I'd probably choose an amp with less gain for the first stage)

(Note the slight hack of the MACOM variable FET attenuator. I don't want to bother with negative voltage rails)
(Note2 the input pad will also make the input match better as a load for the DDS filter, too which it will be connected)

BTW: Does anybody know if the FET attenuator should have a DC return to ground from the RF ports? The datasheet doesn't say shit about that or about how much current the control pin needs.



//EDIT: Added Note 2, fixed typos

[xaxaxa]

Are the sma connectors going to be mounted on the top or bottom side of the pcb? on the top side the body of the connector will "pinch" against the rf trace and mess up the impedance near it; with this layout be sure to put the sma connectors on the bottoms side.

[Yansi]

That is a correct note (I usually do not press them directly against the board), however what will mess up worse: Connector fitted from top or a nasty layer switching hack using a VIA to the bottom side? You tell me...
 I think the RF via is much nastier thing on a 2-L board then a trace being in close proximity of the SMA jack body for a half a milimeter or so.

Unfortunately, I do not have those pcb side SMA, only these right angle ones or straight ones.

[Yansi]

Should this really be better, than a trace sneaking under the connector?

[xaxaxa]

At <100MHz it probably doesn't matter, but higher than that i'd go with an edge connector or just solder it on the back side; is there a reason the connector can't be on the back side?

btw straight sma connectors can be edge mounted too

[Yansi]

Here we are talking about up to 160MHz and 400MHz.

Why not soldered bottom?   ... cannot find the puking smiley ...   THT components have only one place: On the top of the board.

Yes, they can be edge mounted. But it is also a nasty hack. Why not doing it properly?

That would be like this... having THT stuff sticking from it in every possible direction. Yuck!




//EDIT: Maybe I could cobble up a board just to test the behavior of the vias/connectors and measure it using a proper VNA. That might be an interesting idea to do. Like Analog did the research with the filters.

[TheUnnamedNewbie]

Ok then, I will get it manufactured. We'll see how good or bad it will be.

Now a rather lengthy post, sorry for that. But many thanks for reading throuh!

Meanwhile, I started prototyping the ALC module. I am not sure what the best topology should be and I'd like to discuss that a bit.

First we need to solve for the DDS output signal level: The DDS dac is set at it's nominal current of 10mA. As the loading impedance is 50ohm (differentially, using a proper balun trnasformer), I will get a 500mV peak-peak signal into the 50ohm load. (Each leg of the DAC drives a 25ohm load, meaning a maximum 250mV per leg.)  That means I will get about 1.25mW (+1dBm) of power out of the DDS.

Now considering the insertion loss both of the balun (which can be up to 3dB at the edge of the band) and considering insertion loss of the filter which is currently unknown (guessing few dB will be lost in there to), I will likely end up with something in the range of -1dBm downto -5dBm. But we'll measure that later exactly.

To ease the ALC design, currently I will be fine with getting only +13dBm out maximum, as I can use general purpose MMIC ICs for that sort of range. In fact, I need a +19dBm or more of output from the MMIC. Why?  The output has got a 50ohm series resistor. That means the MMIC will need to deliver 40mW (+16dBm) into 100ohm load.  Now the MMIC is loaded only with a 100ohm load, I will add a second load of 100ohm, which will be the input of the log. detector. Now the MMIC is loaded properly with 50ohm, but needs to deliver 4 times the output power of the generator, i.e. +19dBm (80mW).

So I need to be able to amplify those -1 downto -5dBm  to +19dBm.   So I need at least 24dB of gain. Supposed the output MMIC (likely SGA6389Z) will have a 15dB of gain, I will need a second amplifier delivering the missing 9dB (will likely use a MMIC with a higher gain than that and add a fixed attenuator). So far so good.

The question is: Should I put the variable attenuator in front of the two amplifier stages, or should I put it in between?
I see both advantages and disadvantages for that. Let my try formulate those I came up with:

MMIC in front of the amps:
 - both amps working full gain even with the smallest amplitude. As the overall gain of the MMICs combined will be from 30 to 35dB, I guess this will give a worse noise figure. Question is, does it matter so much here? We are working with mV signal levels, not uV.
 + the first amplifier will work with the least amount of signal level possible, giving least amount of distortion.

MMIC in between the AMPS
 - first stage amplifier working with high signal level, as it both must feed the second stage and also cover the insertion loss of the variable attenuator -> higher distortion. (it seems the first amp will need to give up to +8dBm continually in this case)
 + probably better noise figure, as the signal levels will be higher.

 
//EDIT: Added Note 2, fixed typos

There are two things that drive this design: The small signal performance of the amplifier (=noise) and the large signal performance of the amplifier (=linearity).

For obvious reasons, you have to keep your signal above the thermal noise floor at all times. If you want a SNR of 70 dB at your output without any fancy filters or whatever, you need to have that SNR be above 70 dB at all times (I just chose a random number, plug in your SNR). I don't know what your target output power range is, but if you want to get a high SNR at the output, it means that at no point in the signal path, with maximum attenuation, are you allowed to have less SNR. Sounds obvious, but I am just making sure that we keep that in mind!

At the same time, you want to signal at your amplifiers to be as small as possible, such that they are as linear as possible.

This is why you might find alternating variable attenuators and amplifiers - keep riding the sweet-spot between noise and linearity as long as possible (in addition, it can mean less variation in the signal levels of the amplifiers with respect to operating settings, which means less thermal drift issues to deal with).

In addition, if you have some padding between amplifiers it can result in higher stability. The same goes for power rails - you might have to best S11 and S22 of your amplifiers, and the simulations all say it should be stable, but then suddenly you have oscillation because your power rail acts as a feedback path. Make sure you have a lot of filtering on there.

Don't underestimate noise though. You have wide-band circuits, which means the thermal noise might be higher than you expect...

[Yansi]

re are two things that drive this design: The small signal performance of the amplifier (=noise) and the large signal performance of the amplifier (=linearity).

I have already figured that out, as seen above.  However the "dB noise figures" of the RF amps are still a mystery for me. I am familiar with noise calculations regarding standard AF amplifiers and stuff, but the approach used there seems to be very different.

How can one calculate the noise floor of a RF amplifier? For example, suppose we have the two cascaded stages consisting of MAR-3 (12.5dB gain, 3.7dB NF) and second stage of SGA6389Z (16dB gain, 4.2dB NF). How can I calculate using just that, what is the smallest signal possible, to achieve a 70dB SNR at the output? Or do I likely need more information than this to estimate the output SNR?

The signal levels were already stated in the thread: Originally I wanted a +20dBm out. As that requires  a discrete output stage, I have temporarily backed off with just a MMIC amp, as that way I could produce up to those +13dBm, which is enough for most applications.

[Yansi]

Well, after spending a bit on google, it seems the calculation concepts may not be that different.

Based on this PDF I have found: http://www.imst.de/itg9_1/vortraege/oktober2001/koenigsmann_folien.pdf

The noise floor (noise power) at normal temperature is -174dBm/Hz.  Fine, I get. But how do I calculate the noise floor?  I need a say 160MHz of bandwidth, that would mean I need to add 10log(160E6) = 82dB to that -174dBm figure. But wait - the amplifiers bandwidth is not limited - at least the schematic I came up with does not limit the bandwidth intentionally. Is that a problem? As in this case, the amplifier would work well above 2 GHz. That would result in a figure of like 97dB (considering like 5GHz BW), instead of 82.   What to do with this?

Then there is the noise figure of the amps. The combined figure of the two is NF = F1 + (F2-1)/G1 = 2.34 + (2.63-1)/17.8 = 3.86dB noise figure. (Look at the slide 14 of the PDF above, I am not sure if they calculate the gain factor correctly - as 20dB amplifier neither does have a 100 times voltage gain, neither a 100 times power gain. A mistake?*)

So now we have -174dBm + 97dB + 3.86dB = -73dBm noise floor. Doesn't sound the greatest result of all times, but well.. the cascade has 28.5dB of gain on a bandwidth in GHz digits. And also the output signal I want to be on the scale of +20 downto 0dBm or so, meaning resulting SNR from 93dB to 73dB.

Those 90+dB SNR looks good, but those 73 not so much, but it may be sufficient for an application where the expected SFDR is like 65-70dBc.

Or have screwed somewhere? What about the bandwidth? How should I calculate that?

//EDIT: *Have verified from multiple sources, the cascaded NF calculation in that presentation seems correct. Verified the calculation on this website, guesssing Pasternack should be very reasonable to be trusted: https://www.pasternack.com/t-calculator-noise-figure.aspx It came up with the same value of 3.86dB.

[RadioNerd]

You are mixing up power spectral density (in dBm/Hz) and absolute noise power (dBm or Vpk-pk)
PSD is only affected by the noise figure bit is independent from the bandwidth of your system (ie noise floor of a spectrum analyzer).
Absolute noise powe however is, and thats for example the reason why high-speed scopes look noisier than band limited ones

[Yansi]

If one needs the noise power, one takes the spectral density and multiplies by the bandwidth. In decibels, it is the same as adding those together. I do not see what I have done wrong. Please explain.

Noise power  Pn = k T B = -174 + 10log(B)  [dBm]

[RadioNerd]

Yes, that's right. I was mainly confused about how you use the term noise floor... For me, noise floor implicitly means a spectral density (i.e. as you see it on a spectrum analyzer). In that case, the noise floor after all stages (again in dBm/Hz) is simply -174 dBm/Hz + total amplifier gain + cascaded noise figure...

In my opinion, calculating the absolute nose power is only of interest if you are going to use or look at the signal in the time domain, i.e. using an oscilloscope or a very fast ADC. In this case absolute SNR (within the BW of your receiver/measurement equipment) is much more of concern.
If you don't have a 5 GHz scope or similar you will never see the full noise power as all systems are inherently bandwidth limited.

The main problem I see is that too much noise power can limit the dynamic range of the ALC loop as you are planning to use a wideband detector. But you probably still have quite some headroom there...

[Yansi]

If I need to calculate the output SNR then after the amplifier cascade: It is a ratio of the signal vs. the noise floor, as I understand it. (My terminology may be a little off, having hard time with the translation)

You stated that the noise floor, as seen on the SA, is without multiplying by B, i.e. one gets the spectral density instead. Okay than, but then there's a problem I think:

SNR is by definition the ration of signal and noise power. How am I supposed to calculate the SNR at the amplifier output, if I can not use the whole Pnoise formula, as it would account for all he noise in the specified bandwidth?

It seems that SNR needs always to be specified  for an amount of bandwidth, as the SNR is directly proportional to the bandwidth itself.

But I understand your point the the wide band log detector. The AD8307 can detect pretty much above those 500MHz. It therefore seems right to have a band limiting filter (low pass) in front of the wide band log detector, to not detect the power of out of band noise. Which makes sense. 

In this case I need only a 20dB range at the the output so I think the full bandwidth output noise power may not be an issue (yet). But as I will need higher output power range, it may become an issue. Is that correct?

[Yansi]

So a set of a new question, as those above does not seem attractive 

Currently am solving an issue with the wide band MMIC amplifiers.  Specifically:

1) The DC blocking capacitors.  As I need a very wide band operation (100kHz up to hundreds MHz), I don't think that a single capacitor will work. I need it to have a very low impedance at the band of operation, ie. both at 100kHz (which seems like I need like 1uF cap there) and even at the high end (hundreds MHz).  So it seems likely I need to use at least two caps in parallel, expecting the 1uF not to work well at the mid- and high- band frequencies.

What combinations should I use there? Currently I have put there 1uF + 1nF, but am not sure I should use a larger value second cap, otherwise the impedance spike from the larger cap will happen early before the other one has low enough impedance.

Looking in the Marconi schematic (again!) they use "just 220nF" output capacitor for the whooooole range of 80kHz up to 1040MHz and a set of small (even series connected) 39nF caps in the small signal section. Thats interesting. I don't quite get how that works at the low end.  Single 39nF cap has impedance of 51 ohm at 80kHz. If there are even three in series, that is quite some amount of attenuation due to weak coupling.

2) The broadband RF chokes for the bias. The same applies here. I need a broad band choke to operate within like 100kHz up to 500MHz. What I have done already, I have split the choke into two series ones. But I think here applies the same as for the capacitors, regarding the impedance. I need the SRF of the smaller one to be above the maximum operating frequency, but the SRF of the larger one to be high enough as when the smaller one stops operating (is low impeadnce to the operating frequency), the larger one takes all the work. What values should I use? (In the marconi there is a 2.4uH + 1000uH combination at the output stage).

[xaxaxa]

So a set of a new question, as those above does not seem attractive 

Currently am solving an issue with the wide band MMIC amplifiers.  Specifically:

1) The DC blocking capacitors.

In some cases a single large cap will work; as long as the cap has very low ESR at the higher frequencies, it doesn't matter that the resonance peak is at a lower frequency, because at worst the impedance of the cap is no worse than a equivalently dimensioned metal link.

2) The broadband RF chokes for the bias.

Above the SRF of the lower frequency choke it looks capacitive, so you need to make sure that that capacitance does not resonate with the high frequency choke to form a low impedance. For the higher frequencies you might want to look into smt ferrite beads as well, as ferrite beads can have a high impedance over a wider frequency range than inductors, as well as offer some resistive impedance so helps with the resonance problem. FBMH1608HM601 has high impedance from 20MHz to >3GHz. Combine this with some (through hole?) larger ferrite bead and you could potentially get a nice ultra wideband choke. Check with spice/rfsim99 to make sure there are no resonances.

[Yansi]

So you think that probably using a single 1uF capacitor may be just enough?   Or could there be some unforeseen problem combining a larger coupling cap with a smaller one, to improve at the high band end? Like 1uF + 10nF, or there is no point in doing that?


Nice find with the ferrite bead. I did not think these could be used too.  The impedance curve looks good enough for sure, in between the 20MHz to GHz range. Price is good to.  But still need to find the other choke to complement this one, as for the low band region from 0.1 up to some tens of MHz.

Btw, just thinking about it... if the bead is supposed to have Z = 200ohm at 20MHz (according to the FBMH1608HM601  datasheet and the DCR is just below 0.2 ohm, it means it looks like a 1.6mH inductor at 20MHz. How do they do that?

[xaxaxa]

So you think that probably using a single 1uF capacitor may be just enough?   Or could there be some unforeseen problem combining a larger coupling cap with a smaller one, to improve at the high band end? Like 1uF + 10nF, or there is no point in doing that?

I just did a search and it seems very few manufacturers quote ESR or impedance values for chip capacitors in the nF - uF range; personally i'd measure a few caps and see whether their impedance at high frequency is low enough; if not, you can parallel several caps of different values and check with simulations to make sure there are no resonances.

Btw, just thinking about it... if the bead is supposed to have Z = 200ohm at 20MHz (according to the FBMH1608HM601  datasheet and the DCR is just below 0.2 ohm, it means it looks like a 1.6mH inductor at 20MHz. How do they do that?

My calculations say 1.6uH at 20MHz, which is easily achievable btw also found the FBMH1608HM102 which extends the frequency down to about 10MHz.

A quick search on mouser didn't turn up any suitable low frequency beads, so you may try an inductor or wind your own; then simulate the combination in spice or rfsim99 (googling "FBMH1608HM102 spice" turns up the models).

[Yansi]

Yeh, I have found later I have pressed the wrong button on my calculator. Of course it is 1.6uH.

Still have not found a suitable inductor to complement the ferrite bead at the low band end though. 

[Yansi]

While not being able to find a suitable inductors, some progress is being made with the ALC PCB module.

Well it might look a bit over engineered looking on those six SO-8 packages, but indeed it is and for a purpose. I'd like to have that ALC block available as a more permanent one, so I have added some more support circuitry in there like a calibration E2PROM and a output unleveled comparator. Also the module is designed to fit inside an off the shelf tin shield box, sticking all connectors outside, including two status LEDs.

On the other hand it is quite under engineered on the RF side of the thing. Hopefully, it will work. At least a bit, so I won't get too much disappointed. 

[yl3akb]

Well, after spending a bit on google, it seems the calculation concepts may not be that different.

Based on this PDF I have found: http://www.imst.de/itg9_1/vortraege/oktober2001/koenigsmann_folien.pdf

The noise floor (noise power) at normal temperature is -174dBm/Hz.  Fine, I get. But how do I calculate the noise floor?  I need a say 160MHz of bandwidth, that would mean I need to add 10log(160E6) = 82dB to that -174dBm figure. But wait - the amplifiers bandwidth is not limited - at least the schematic I came up with does not limit the bandwidth intentionally. Is that a problem? As in this case, the amplifier would work well above 2 GHz. That would result in a figure of like 97dB (considering like 5GHz BW), instead of 82.   What to do with this?

Then there is the noise figure of the amps. The combined figure of the two is NF = F1 + (F2-1)/G1 = 2.34 + (2.63-1)/17.8 = 3.86dB noise figure. (Look at the slide 14 of the PDF above, I am not sure if they calculate the gain factor correctly - as 20dB amplifier neither does have a 100 times voltage gain, neither a 100 times power gain. A mistake?*)

So now we have -174dBm + 97dB + 3.86dB = -73dBm noise floor. Doesn't sound the greatest result of all times, but well.. the cascade has 28.5dB of gain on a bandwidth in GHz digits. And also the output signal I want to be on the scale of +20 downto 0dBm or so, meaning resulting SNR from 93dB to 73dB.

Those 90+dB SNR looks good, but those 73 not so much, but it may be sufficient for an application where the expected SFDR is like 65-70dBc.

Or have screwed somewhere? What about the bandwidth? How should I calculate that?

//EDIT: *Have verified from multiple sources, the cascaded NF calculation in that presentation seems correct. Verified the calculation on this website, guesssing Pasternack should be very reasonable to be trusted: https://www.pasternack.com/t-calculator-noise-figure.aspx It came up with the same value of 3.86dB.

I dont think that You can just assume that noise floor at the input of amplifier cascade is -174dBm/Hz or 290 K. AS9951 datasheet shows some spectrum graphs with 3 KHz noise floor of ~-85dBm (I assume that DDS noise dominates in those measurements), which is -120dBm/Hz or 54dB larger than 290 K or 73*10^6 K! The point is that in this case You can not simply add noise figure like that because NF is defined at 290 K input noise.

For example:
You got NF of 3.86 dB, this means that amplifier cascade adds 415 K noise to DDS noise (73*10^6 K) at the input. This means that amplifier worsens SNR only by 10*log((415 + (73*10^6))/(73*10^6)) dB which is absolutely nothing.

Other example:
Assume You got 60 dB attenuator. Its NF=60 dB, so it adds noise of 290*10^6 K at its input. Now SNR will be worsen by 10*log(( 290*10^6 + (73*10^6))/(73*10^6)) ~ 7 dB, which starts to get noticeable (but still nothing in my opinion)

[Yansi]

Inductors still not chosen (shame on me, I know), but a SCH + PCB is done.

Schematic below in the attachments. You can do a sanity check of it or hate it loud, or maybe both. It is somewhat more complicated than originally wanted it too, but after all, there are not so many things in there:

Schematic description:

(Note: Some of the values in the schematic are missing now, will be calculated later. This is just for a sanity check.)

The RF chain consists of an input pad, followed by the Macom FET attenuator and two amplifier stages.

The Macom FET attenuator requires negative voltage for operation. I hate to make aux negative voltage rails, hence the slight hack of the device (I think it will be good enough for the frequencies of interest here). The device ground is lifted using R10, R11 divider to a voltage slightly below +5V. D2 is a protection against the application of positive voltage to that device.  Control voltage is applied through R14.

Please check me: The FET attenuator has a kind of anti-intuitive control voltage characteristic. 0V control voltage means maximum attenuation, while negative -3V means minimum insertion loss, fully open.  Therefore 0V at the IC7B amplifier output means minimum attenuation (IC2 at full negative voltage), while positive voltage at the IC7B means zero voltage at IC2, hence full attenuation. The voltage output of IC7B is proportional with the attenuation. 

Based on the above polarity of the control loop was established. IC4 generates more positive voltage for higher RF amplitude. If the amplitude detected is higher then the setpoint from DAC IC9, the output of the IC7B servo must go up and the control voltage of IC2 must go towards zero (bigger attenuation).

The log detector is connected directly to the output through a about 20dB pad. IC2 log detector provides 0V for zero RF input, but we need it to provide zero volts for certain RF level, and amplify the slope of 25mV/dB to a higher level, as we will operate only within a 20dB range. IC7A amplifies the output of the IC4 AD8307 log detector to a suitable level, while R30 shifts the output of IC7A down.

IC10 makes for a window comparator with added hysteresis, that watches the IC7B output and determines whether the IC7B is out of range, meaning the RF output is unleveled.

The rest is just a power supply of +8 for the RF amplifiers (and the comparator IC10) and +5V for the control circuitry, including a 4.096V reference IC11.

The purpose of IC8 is to store calibration data of the output level versus frequency.  It would be better to use an SPI memory there, as there is already SPI present for the DAC, but I could not find any such suitable one with a write protection pin. The 24Cxx is just a cheap and good enough solution for it.

Regarding the PCB: Nothing too exciting there. Layout may be good enough for the girls I go out with. (Wait... there are no girls! So hopefully it will work at all) Made to fit an of the shelf tin shield box. Hopefully I can fit that in with both the angled IDC connector and those SMAs (I usually solder them to the tin from the outside).

Thanks for checking the schematic and/or PCB.

[Yansi]

Of course there is an error! Who spots it first?  (Hint: IC10).

Now fixed.

//EDIT: Another errata: The 20dB pad for the AD8307 goes through the coupling caps. I think it will be way better to DC couple the attenuator and AC couple the AD8307 to it. This way the caps won't have that much influence on the attenuation of the divider. The input of the AD8307 is rather high impedance (~ 1k+2pF). This mod will increase precision for sure.

Corrected schematic here:

[cdev]

This DDS looks interesting..

[xaxaxa]

This DDS looks interesting..

That's not a DDS, just a synthesizer chip; unfortunately the adf4351 only goes down to 35MHz, and the more common (cheaper) adf4350 only 137.5MHz. I have been looking for synthesizer chips with lower frequency limits for a long time, so tell me if you see one that can go down to <10MHz.

[phenol]

i do remember seeing a similar TI part that could go lower (and higher) in frequency.
You can easily divide down 35-100MHz to any lower frequency you need with commonly available parts...but those frac-n spurs don’t look great, especially with a wide-band loop filter in place

[Yansi]

Yes that is not a DDS, that is an integrated PLL + VCO. There is one interesting chip from MAXIM, that has even widest range but for half the price of ADF4350 (even when bought from reputable source, not china): Have a look at a MAX2871 (23MHz to 6000MHz). But I'd leave this out of this thread for now.

As noone is complaining about my pcb/schematic, I will send it manufactured too. 

[phenol]

why don't you at least test your attenuator setup on a 2-sided cu clad board by cutting out pads with an exacto knife?

[Yansi]

Simple: First I do not have any of the key components, except the AD8307 log detector and MAR-3 amplifier. While waiting for components, I have spent the time to design a proper PCB. And second, I want the ALC block as a more permanent one for my lab. It might come handy for future experiments. Is there anything wrong spending the time to do it properly?

[phenol]

nothing wrong--except for your doubts how to make it work without the negative bias the datasheet suggests and the likelihood of multiple board re-spins. If you can get them made cheaply, then i guess that'd be ok. The DDS portion of it should at least spit out something of a signal so you can use it as a signal source for testing the other stuff

[Yansi]

Well to achieve a negative voltage over a component, one can float it's ground of course, which is what I did exactly. Both ground pins are lifted using a resistor voltage divider to +4V and generously decoupled using three 100nF caps. Yes, this adds inductance to the ground connections, but that should be of not much issue, we are not talking here about GHz range or high attenuation either.

I only find the datasheet of the attenuator a bit incomplete in that regard of not providing the current needed to operate the device (or I could not find it  ) or if that device needs any other special treatments in circuit. I even couldn't find any evaluation or reference application schematic for this part on the manufacturer's website. So I kind of guessed a bit here and there, hopefully not too wrong.

If I haven't mentioned - both PCBs for the DDS and the ALC are currently being manufactured. The DDS is at a local PCB house, the ALC was sent to ALLPCB, because the local PCB house does not offer low quantity manufacturing on 0.8mm substrate. (Yes a thinner PCB, used a microstrip for the RF path this time).

So let's see which one will be delivered first. ALLPCB shoud be fast, right? So have they told me

[Yansi]

So I'll just continue my monologue. ALLPCBs have arrived today, however my stupid moron friend forgot to send the DDS board manufactured, so another week of delay now introduced. Doh! 
And still waiting for the Mouser components, but they should arrive tomorrow.

[Yansi]

Yet again continuing the monologue.

Power supply chain working. Got 8V, 5V and 4.096V reference.   DAC and E2P memory soldered, so is part of the RF path: attenuator and the first RF gain stage.  Unlevel detection window comparator working too.

Now I need to get it to a suitable lab so I 'd be able to verify the functionality of the FET attenuator.

Still waiting for the SGA6389Z amp to arrive, I could possibly solder the MMG3H21NT1 in there, I got three of those available now.   Lost the bag of AD8307 somewhere, need to find those or order new ones and continue with that. 

[TheUnnamedNewbie]

Looking good, curious to see how it goes once you get the remaining parts of this part installed!

[Yansi]

While waiting for AD8307 and the SGA6389Z, I have measured the attenuation as a function of control voltage - the voltage at the IC7B output.

What came a bit surprising is that the maximum achievable attenuation is larger, then specified in the datasheet of the MAAVSS0006 part. That is of course positive result.  Measurement was done at ~100MHz.
That means the "voltage shift hack" is working absolutely fine, as predicted.

It would be more interesting also to measure the maximum attenuation as a function of frequency - but as I do not have currently any other RF source (obviously, I am just building one), I can not measure that, yet. Maybe I will sneak into the university lab on Monday to measure that.   

[TheUnnamedNewbie]

Maybe I will sneak into the university lab on Monday to measure that.   

Depending on what your relation ship is with the PhD students or such (I don't know your function in the university, ie, are you a student/staffmember/etc), ask them about it. Around here, there are some that love making measurements, and will gladly take any half-decent reason to play around with the VNAs for a day. (Lets face it - if you have a lab full of fun toys high quality test-and-measurement gear, you would love to use it all the time desire verifying it performs well on a continuous basis)

Regarding the attenuation: keep in mind that at high frequencies, it will likely get bigger at the low end (because losses become more and more significant) and lower at the high end (because capacitive leakage and coupling becomes more and more significant).

Exciting to see first measurements!

[Yansi]

I know that attenuation will decrease with the increase of frequency. The datasheet suggest this for the MAAVSS0006 part:



We only care about the orange region I have marked there, as the AD9951 can go only up to 160MHz maximum. But because the AD8307 log detector can work up to 500MHz, I am kind of tempted to try to characterize the ALC unit all the way up to 500MHz and may be a bit beyond, as the AD8307 can demodulate even way after 500MHz.

The main measurements I am most curious about are the measurements of the minimum-maximum input levels the ALC unit will be able to still work with to achieve the desired output of +13 down to -7dBm.  I.e measuring the minimum input level to still achieve +13dBm output and measure the maximum input to achieve -7dBm output.  The input then has to be within these two curves for the ALC to level the output.

I am looking to see at least 10dB gain reserve in the full range, which should be enough to cover for DDS filter output variation and other stuff happening.

[Yansi]

Another random shriek:  I have found a bag of AD8307.    Soldered it in, seems it is doing something.  Trying to make sense of the output voltage that it produces.

The output circuit looks like this:



Output from the last amplifier is divided into two parallel branches of 100ohm. One being a voltage divider for the log detector (AD8307), the other branch being a 50ohm output resistor + 50ohm load.

The AD8307 output gives 1.715V. How much dBm should I have at the RF OUT?

The AD8307 should give 25mV/dB. The intercept point should be -84dBm (first page of AD8307 datasheet). I understand the intercept as a signal level where the output will be 0V.

Based on the above assumption, I get 1.715 / 0.025 = 68.8dB above the intercept, meaning I should ne 68.8 - 84 = -15.4 dBm of equivalent voltage at the AD8307 input terminals.

As the input of the AD8307 is connected through a voltage divider consisting of 91R : 8R2, this one adds 21.6 dB loss, meaning that at the node of the amplifier output, there should be voltage equivalent to -15.4 + 21.65 = +6.25 dBm.

Half the power being then consumed by the 50ohm output resistor, half the power into the load. Therefore RF OUT should deliver +3.25dBm. But that does not make sense, as I measure -3.5dBm at the RF out. Almost 6dB less. Wtf?

Where did I screw up or what is wrong?

//EDIT: I may just see what is wrong! I am feeding the thing a signal containig high amount of harmonics.  I have pushed the "total power" button on the spectrum analyzer, it then shows +3.1dBm. (The first harmonic being -3.5dBm). Maybe this is what is making the error?

[RadioNerd]

I think your assumption about the 50 Ohm series resistor. is wrong... Actually, only 25% of the MMIC output power (i.e. -6dB) is delivered to the load as this resistor forms a voltage divider, not a power divider. This reduces the discrepancy you found by 3 dB...

[Yansi]

Yes of course, it is -6dB in terms of voltage and power too.  I have later discovered that lil mistake I should not work that long into the night.

Later I have also closed the loop and woohoo, it did something. Then I have discovered the calculated values for IC7A are completely wrong.

Now I have new, correct values, which are E24 fun:  R16=6K8, R17=3K0, R30=4K3.  But it does (actually, have not soldered them there yet) according to a simulation what it is supposed to: Convert the dBm output range to a voltage range of the DAC.

Just a short explanation:
We need a +13 down to -7dBm output. There is +6dB at the MMIC output and then -21.6dB less (R3, R8) at the detector. The AD8307 detector produces a voltage in the range of 2.034 down to 1.533V.
This voltage range shall to be scaled to the DAC range, which is 0 to 4.096V.
The IC7A configuration if R16,17,30 above does this, with a reserve of about 5.5dB across the range. This means that the DAC output of 0V means  about -14.9dBm and 4.096V means 18.8dBm delivered to the load.
The reserve is there to account for resistor variation and stuff, to be able to calibrate that out.

I have still not soldered the output MMIC, but will do that in no time. MMG3H21NT1 prepared. 

Up to date schematic below, just for the giggles.

[Yansi]

Good news everyone!

[TheUnnamedNewbie]

Good news everyone!

That is good news! What PCB thicknesses are you going with? Standard 1.6mm? FR4, I assume? I ask because I'm looking at some options for my variable attenuator project and I don't know where to get non-FR4 boards as a non-commercial customer. Alternatives I have also considered is going for a thinner FR4 so those GCPW tracks are a bit more reasonable sized.

[Yansi]

Forget anything else than FR4, unless you want to spend half your earnings onto a single prototype PCB.

As far as I know, OSH park uses some "slightly better FR4" in terms of RF performace.

What kind of frequencies are you interested for your project? I wouldn't bother with Rogers  if you stay within a couple of GHz. After all, you are making attenuator

With FR4, if the substrate is a 1.6mm standard, to achieve 50ohms one should use a co-planar  waveguide, on a 0.8mm substrate a microstrip is the way to go. I use both, depending on a lot of things. (If I remember correctly, CPWG has lower loss than microstrip)

See the attached loss plot of FR4 compared to Rogers.

[TheUnnamedNewbie]

I'm not just worried about loss but also mismatch. Not all FR4 is the same, and I have access to very fancy substrates for cheap through my uni (just use the leftovers from other projects), the problem is just that they can't make plated vias. Not a big problem for the waveguide, but it's very annoying for those chips with big ground planes.

I wanted to use GCPW because it matches the chip footprint better and I believe less sensitive to mismatches of the substrate (since a good portion of the fields are on the top plane between the copper, and not in the substrate). 

And yeah, this is just an attenuator so it's not vital, but in the future I might do projects where it is not, so I thought it could be a good idea to start out. Perhaps I can also look at getting hold of some substrates for home etching... I'll ask around my research department.

Perhaps I'm just having bad expectations... My research involves working on a design where we have 50 um wide CPW lines that are 74 ohms (175 um thick LCP substrate), so seeing the 1.7 mm wide traces on my current design made me frown... Might just throw things into HFSS later this week to see what gives.

[Yansi]

having 50um wide traces is crazy, what is the thickness? Guessing this is completely not standard.  From my little experience in the RF field, this is a complete nonsense to do. The wider the trace, the better, as the etching imprecision will be only a small variation of the overall width.

If you are concerned about missmatch and work at a uni, then have a prototype board manufactured, trace impedance measured, design corrected and done.

[TheUnnamedNewbie]

having 50um wide traces is crazy, what is the thickness? Guessing this is completely not standard.  From my little experience in the RF field, this is a complete nonsense to do. The wider the trace, the better, as the etching imprecision will be only a small variation of the overall width.

If you are concerned about missmatch and work at a uni, then have a prototype board manufactured, trace impedance measured, design corrected and done.

This is something that works at D-band (the waveguide band, not the NATO one) and uses GSG probes for measurement. Substrate thickness is is 180 um. I'll make a post and maybe even a video on it after all the publishing work is done, for now I'm restricted as we will present this work at a conference in the near future.

That aside: I am going to stick to plain-old FR4 this time I think, I'm starting to realize it is just not worth the hassle to go to fancier stuff. My perception is just a bit skewed since my day-work is on a different scale of frequency. Where most people who do electronics underestimate the impact of trace sizes and discontinuities at a few GHz, I may be part of the few in the world that tend to overestimate the impact 

[Yansi]

Bad news everyone. I have fried the DDS chip. The only one I had. But seriously, I do not know how or why. No fucking idea.

AD9951 soldered on the board, schematic below. Voltages applied correctly, verified 1.8V and 3V3 for DVDD_IO section. There was a large current draw ~50mA from the 5V input, although the DDS was in the full power down mode (PWRDWNCTL = 3V3).

When measured in circuit, the 1V8 rail was pushed to about 2.2V due to current leaking from the 3V3 domain to it. I then even tried powering the 1V8 or 3V3 domain separately, but either of them gulps unhealthy amounts of current.

I just can not figure out what went wrong.

...until my friend have noticed that AD9954 has 1V8 maximum voltage limitation on the CLKMODESELECT pin. I've had that pin hooked up directly to 3V3. BUT! The AD9951 datasheet does not prohibit doing so! There is not a single word that you can't apply 3V3 to the CLKMODESELECT pin. 

So am I the stupid one or does Analog Devices owe me a DDS chip?

I have attached the schematic, so you can verify. The only fault known I haven't noticed before is that with AD9954 you can not connect the CLKMODESEL pin to 3V3.  I have used AD9951, so that should have been fine.

Please double check the schematic for me if you can.

[Yansi]

After a bit of tinkering, the DDS may not be fried (at least not definitely too much), so I'll try to throw some data at it to see if it is alive.

The root cause? The fucking CLKMODESELECT pin. They just do not tell you the critical fact that you can't apply more than 1.8V to this damn pin. They only tell you this in the AD9954 datasheet. Fuck!!!  Yes I should probably read the 9954 datasheet more carefully, since I have designed the board to be compatible with 9954 too, but this should be stated in the 9951 datasheet in the first place. 

I have tried to contact the ADI technical support. My friend tried same. They just ignore it, they just don't care.

[Yansi]

After a bit of necessary wrestling with the DDS, I have finally managed to get it working.

I have found a few issues that, that I can't explain just yet: First, small output amplitude. I'd expected it to produce a lot closer to 0dBm, not -13dBm. 

Second, the signal doesn't look clean as it should have. See the below image. There are significant side-lobes present around the carrier. I can't explain that now, but when I will manage to get an external REFCLK going, I will measure again, to exclude the internal PLL, which is supposed not to be the greatest (but still I thing there might be something else wrong with it. Mainly the power supply, as I took 5V from the ARM board, that is powered from a laptop's USB).

And third the frequency is off by 560ppm. No, my SA is not that much out of cal. I measured 100.056MHz instead of 100. Even my oscilloscope, which uses a bog standard TCXO at best as a ref clock source, thinks the frequency is 100.6MHz or thereabout.

Here is a picture of the garbage around the carrier.

[cdev]

Does the amount of noise vary with different frequencies?

[Yansi]

Haven't done any further testing with it. I was rushing other PCBs to get manufactured. Will check different frequencies. What might cause that crap around the carrier?

Currently I have sent an ADF4360-7 board to be manufactured - as a clean 400MHz reference source for the DDS (to compare performance with the internal PLL in the DDS)
and a simple USB control board with STM32F042 was just sent to be manufactured minutes ago. Small board that can connect all three modules together: DDS, PLL, ALC.

Y.

[phenol]

The side lobes may be generated by noisy avdd. The bigger problem is the offset in amplitude and frequency you are seeing. Wrong register programming?...
As for Adf4360, what makes you think that it’s going to be anything much better than 9951’s internal pll under similar power supply noise  environment ? Maybe the scope of applications that your dds covers doesn’t care too much about close -in phase noise; in this case adf4360 with its fairy wide-band VCOs would be fine. Otherwise, i would either take a stable reference and multiply its output frequency as needed or make a narrow-band shielded vco with some external pll(adf4106 or whatever).
I think you can find narrow-band vcxo (saw-based) low phase noise oscillators, but those are not exactly cheap...

[Yansi]

I'd not really be so sure on the PSU noise. The DDS has local supply regulation, even I have separated the DVDD pins using ferrite beads.  I mean, nothing fancy about the supply, but I have used similar concepts in other designs, that produced much higher frequencies with much cleaner outputs.

Wideband or narrowband VCO... What's the definition of? I think what mostly we are after the tuning slope, MHz/V.  Then I'd consider the ADF4360 to be narrow band VCO. It has a range of 350 to 1800 MHz, but the specific place of operation is set using external inductors, relative bandwidth being not that large, i.e. maybe 20-25%?



Similar chips like ADF4350, these switch in between banks of narrowband VCOs internally, resulting in something about 30MHz/V if I remember correctly, even though the range is like 2200-4400MHz and tuning voltage range just few volts.

So should these be considered wideband? I am not sure.

Why I don't like the internal PLL in the AD9951? A good question! First, it's capabilities in terms of multiplier ratios is quite limited, one might even say idiotically, as it requires at least 20MHz input and can not  work from a 10MHz standard. Second, even the datasheet and the manufacturer suggest that performance of the integrated PLLVCO is not the greatest. See the last sentence in the capture below. 



Is this really a show stopper here? I really do not know. Hence why I want to compare using a decent external PLL, that will also allow me to multiply from 10 MHz reference, which is a welcomed option.

I will try another measurement later today, to see how the supply influences the output.

[Yansi]

Just out of curiosity, I have done the slowest sweep on my SA possible (SWP 430s, VBW 10Hz, RBW 3kHz), to see what the result will be.  The result is, the SA has a slight alignment problem under these conditions, as obviously the signal should have been centered.
I have also moved the reference to -20dBm to better show the noise floor. Now the noise floor is below -90dBm. 

My measurement techniques may be not all that correct anyway, I do not know how to do better. How should I really measure this?

The frequency is still 58ppm off. I think the SA reference osc is quite still in cal, if I remember comparing to a precise TCXO. Maybe the crystal I have used is junk (even though I chose 10ppm one), or I might have soldered there a wrong loading capacitor. Will check.




//EDIT: Replaced the load caps, now it sits -6ppm, which is well within spec.

[phenol]

i remember that ad9910 +internal PLL gave significant improvement in phase noise that even a mediocre spectrum analyzer could show when i replaced a bog standard lm317 regulator with something much quieter.
as for the  vco, this is what i would call narrow-band: http://www.crystek.com/microwave/admin/webapps/welcome/files/vco/CVCO55CX-1000-1000.pdf

[Yansi]

Gave significant improvement against what?

I think that having a local voltage regulation plus separation of DVDD using ferrite beads is about the reasonable maximum. Otherwise I'd consider it hunting ghosts.

We could then start the topic of DGND vs AGND, but I think in most cases it is better to have no separation, then wrong separation, while the latter is much easier achieved.

The only other trick I know which is still kind of reasonable to implement is to use a capacitance multiplier with a transistor, as this provides for a very low noise. Not sure if it would help here anyway.

What I also think might be the cause is the Qtal oscillator (being quite high impedance circuit) is picking up crap. On the board I have designed I have accounted both for the crystal and external reference input, so the traces might be a few mm longer than is usual. Any kind of disturbance to the oscillator will be directly seen at the output.

If you think the internal PLL is good enough, then there is not much choice left. Either the power supply (which I kind of doubt), or the oscillator. That could be easily proven, if I'd connect an external oscillator (a good one, eg. a TCXO) but still use the internal PLL to multiply up to 400MHz.

[Yansi]

 No, not the crystal oscillator. Have tried connecting an external one, the crap is still there, without any visible change. So what else? I don't think there is anything particularly wrong with the PSU circuit, please see attached below, you can check.

//EDIT: Added missing tantalum cap values in the schematic.
//EDIT2: Also tried if there is difference when board supplied 5V from USB or from a cleaner 5V linear supply. Result: No difference visible in the output crap amount.

[phenol]

The improvement was in close-in phase noise up to 10k or so away from the carrier. I observed the noise go down 10-15db 1k away from the carrier when i placed 3300u cap on the output of lm317. This was clearly the 1/f (kind of)noise contribution of the voltage regulator that was modulating the internal vco. Note that it didn’t have the ‘spiky’ lobes  your analyzer shows and that i used the actual ad9910 demo board, which seems to have split ground.
ground loops? digital noise coming from your controller/laptop/pc?...

[Yansi]

As I have already said, there is no influence whether powered from USB or completely isolated linear PSU.

There's a single GND plane below, still not sure how the sidelobes could be caused by it. Please find the PCB layout attached.

I will try disabling the internal PLL and using external high frequency XO, if I will find one.  I am still suspect the crap comes from the internal PLL.    I have cobbled together some other PLL circuits in the past, on a home etched pcbs that were way worse than this. Never had such crap on the output, unless idiotic me thought it would be good to run the tuning voltage to the VCO using a 30cm of unshielded wire. Well, no...

[phenol]

i doubt it’s your ground plane causing this... i was referring to other external devices that may be hooked to your dds board. how do you program it? can you configure it and then somehow disable all digital crap nearby? can you make a scan with 50k-100k span and RBW=100-300Hz?

[Yansi]

The registers of the DDS gets set, and then the communication is silenced.  The MCU on the board nearby is still running, but it is unlikely it does that (my 1627MHz PLL did not have any visible issues with the same MCU board). It has also it's own local voltage regulation and if I remember correctly, I have even tried powering the MCU and DDS from a completely separate PSUs, with no change.

No, I can't do that, the minimum RBW of my SA is 1kHz. But if you want (and will be useful for you), I can do 50k or 100k span, 1k RBW. What VBW do you want to set?

//Looking in the manual, they mention 300Hz RBW in the specs. Have no idea how to set it there. It never did allow me to set less than 1k. Interesting.

[Yansi]

Here's the 50k SPAN, 1k RBW, 1k VBW capture.

[phenol]

https://www.eevblog.com/forum/projects/1ghz-clock-source/25/

i did some comparisons between PLL vs external 100MHz x 10 clock as described in the thread above. I can’t remember if this was before or after low noise regulators were installed...

[Yansi]

I've managed to get to a better SA for a few hours... Here's the result.

The sidelobes are there, -80dBc. Should I be really concerned about them?

There are a few measurement with different spans and RBWs. The last one being 10kHz SPAN with the lowes possible RBW/VBW setting. Pretty awesome result I would say.

As a sidenote, the power was drawn from a USB port of a PC. Not exactly a clean 5V source

[phenol]

it doesn't look bad... the screenshot (of the original AD9910 eval board clocked by an external source) i've attached was taken with a FSL analyzer, which has inferior phase noise to FSP. There's a 10-dB external attenuator in order to bring the signal down to -10dbm. The humps around the main tone are most probably reciprocal mixing products of the analyzer's own phase noise, which isn't all that great...

[yl3akb]

I've managed to get to a better SA for a few hours... Here's the result.

We also have R&S SA at work, and first thing when I see that red (*) on the right is check if SA is not been overdriven. But probably it is not the case here as spectrum seems quite pretty.

[Yansi]

The red asterisk did randomly appear and diminish the whole time. Have no idea what it means.  -10dBm should not overdrive any SA, when the attenuators are in automatic mode.

Y.

[parasole]

Interesting project, any progress update?

[cdev]

Different chips, but similar goals.

[Yansi]

Interesting project, any progress update?

No updates, not enough free time to proceed.

So far a DDS module is finished, working. Need to solve why the output is lower than expected.
I have finished also an ALC module, to control output level in the range of  20dB, rest gets dealt by a relay attenuator (not yet verified). ALC module seems working correctly (verified partially). Haven't had available any suitable test equipment to verify, now I have so proper verification of ALC is on the list.
Control board also has been made for this project:  A small USB equipped microcontroller to interface with both the DDS, ALC and also ADF4360 board, which should serve as a 400MHz reference locked to a 10MHz standard. (AD9951's PLL unfortunately requires 20MHz minimum if I remember correctly).

Some time ago I have scored a rusty & crusty Agilent E4432B for really cheap, so this DDS project got how to say that ... a low priority. I do not plan abandoning this little project, but I have more stuff to do than I ever probably could, so...     (I guess typical EE enthusiast is the diagnosis).

I have also some more advanced concepts on the list, using the well known ADF4350.  Two of those mixed together could make a really nice RF synthesizer, say from (almost) DC to about 1 GHz. Using the ALC block invented in the project above (yes, could work up to GHz), only the RF mixer and filters would need to be tested. Off-the shelf monolithic ceramic filters and MMIC mixers with high linearity would probably make this quite usable result. However I would not like to anticipate to much here. 

Important stuff needs to get done first. 

[parasole]

Thanks for update Yansi, so you say ALC is working properly and is ok to be reused?
Any significant changes from the last version posted over here?