Has anyone ever seen an SDR design that uses a QSD to feed a fast 100MSPS+ ADC?

[rwgast_lowlevellogicdesin]

I have a few nice 16bit LT 105MSPS  ADCs laying around and I've been thinking about trying to design an affordable HF SDR with a broad(~10mhz) instantaneous bandwidth. Something more along the lines of an SDR-IQ/FLEX system. I know these expensive higher end HF SDRs all use DDC with and FPGA/ASIC. Could something with comparable performance be made by feeding a QSD in to a nice ADC then doing DSP work on a faster micro or even something like an allwinner a10?

I have searched and searched for an SDR using something like a soft-rock or any QSD to feed a fast ADC and I can't find anyone using anything besides audio codecs for some reason, 48khz of bandwidth sucks so I cant figure out why no one has done this, unless the performance is no better than using a cheap tuner chip. From what I understand you can switch a QSD up to 1ghz so this gives the ability to build a wideband SDR or a really performance focus narrowband SDR.

This is all kind of just thoughts here but if one could build a QSD SDR that does DSP on a micro or streams to a PC and gets close to DDC performance, it seems like a great inexpensive way to build a nice low noise base to down convert other bands too! Especially if you dont have to have 105MSPS ADC, a 40MSPS is much cheaper! Some micros like the NXP's even have 80MSPS ADCs built in if your willing to go down to 12bit.

[mark03]

Wouldn't you be hard-pressed to get the data out of the ADC at those speeds, without an FPGA?

If the idea is that getting rid of the FPGA makes this a substantially easier project, I would suggest otherwise.  At those frequencies, good layout, and keeping digital crud out of the front end, is the bigger challenge.  That's what I heard from the openhpsdr folks (the best-known direct-sampling design).

Don't forget to factor into your supposed cost savings that you now need two ADC channels instead of one.

I also believe it's difficult to get that kind of bandwidth out of the Tayloe-style QSD, due to finite source impedance and reasonable capacitance at the four phase outputs, but I'm not an expert.

More interesting (to me) would be a moderate-bandwidth QSD-based receiver which is designed around fast and high-resolution successive-approximation ADCs, say 1 to 2 MSPS, rather than a sound card.

[NiHaoMike]

Beaglebone can do 100MSps, but I don't see much advantage using that instead of a FPGA.

[CopperCone]

well its probobly alot easier to program it and test algorithms with high probability of intercept signals before going to fast FPGA detectors.