Huawei RRU3908 base station teardown and circuit analysis (part 1 & 2)

[madsbarnkob]

The Huawei RRU3908 is an outdoor Radio Base Station with one to four carriers and one to six sectors at 20/40 Watt RF output power per carrier.

Part 1 is the teardown itself with a walkthrough of different design highlights.



Part 2 is coming online in the following 1-2 weeks.

Part 2 is a complete circuit analysis and will also have high res pictures uploaded to this article.

[TheUnnamedNewbie]

Was interesting to see. Those cavity filters are always interesting to look at.

Looking forwards to part 2!

[drew23]

Likewise, very good. There is little modern or detailed information on designing cavity filters, most being proprietary, so seeing what is commercial practice is very useful.

The duplexer seems to be iris-coupled cavity filter, with some inter-cavity coupling. The coupling of input and output is a delta T, a connection part way up the resonator, rather than a coupling loop. The frequency is adjusted by a capacitive hat. The filter is band pass for a wide signal.

It would have been useful to see the filter responses.

I have something similar in the post and will report on my blog. Google callsign. Many posts on cavity filters.

Drew VK4ZXI

[madsbarnkob]

EDIT July 12 2018: See next post for new video with fixed audio. Sorry for the problems with low audio recordings on the first one.

Unfortunately I can not post the high resolution pictures here due to file size restrictions, so you can see them at my website: http://kaizerpowerelectronics.dk/teardown/huawei-rru3908-base-station-circuit-analysis-part-2-of-2/

Central Processing Units

Network communication is handled by a Freescale MPC8321 PowerQUICC2 CPU which runs at 200 MHz and has 2x 256 MB Hynix DDR2 RAM. It utilises a PMC QuadPHY 10 GB controller for the two optical input / output.

Decoding and encoding of the single bit streams for ADC and DAC are handled by the 3 Altera Cyclone III FPGA and the custom Huawei SD6151RBI controllers.

The single bit streams are treated by the Texas Instrument TMS320 series DSP CPUs. TMS320C6410 which is a fixed-point DSP that only calculates with integer numbers and the TMS320CT16482 1 GHz DSP CPU calculates floating point numbers.

Receive part

The input signal comes in two out of phase lines and are first treated by a Skyworks SKY73021-11 1.7 to 2.2 GHz downconversion mixer to get the frequency from 2.2 GHz to 550 MHz.

The local oscillator for the downconversion mixer is a Analog Devices ADF4110B.

A SIPAT SAW filter is used for isolation.

Depending on signal origin or type, I assume that the Analog Devices AD8376 Variable Gain Amplifiers are used before the signal lines split out into either a 3G ADC line or 4G ADC line.

The 3G line analog to digital conversion is handled by the Analog Devices AD6655-10 which is a 14-bit 150 MSPS chip that is specifically targeted for the 3G base stations.

The 4G line has a few more components as there is 2 MCL HSWA+1110 SPDT RF switch that feeds into 2 Maxim MAX2039E up/dowoconversion mixer and through a additional MCL HSWA+1110 SPDT RF switch it is handled by the Analog Devices AD9230-11-200 ADC which is a 11-bit 200 MSPS chip.

All timing is handled by the Analog devices AD9516-3 which is a 14-output clock generator with a built in 2 GHz local oscillator.

Transmit part

The single bit datastream from the Altera Cyclone III FPGA is handled by 2 Analog Devices TxDAC AD9788 which are specified for 16-bit 800 MSPS.

To get the signal up in frequency to the broadcast carrier frequency 2 Analog Devices ADL5375-05 upconversion modulators are used. These has a range from 400 MHz to 6 GHz.

The signal is then sent through a 5 staged ceramic resonator band pass filter.

Signal phase can be switched from the setup of transistors and EMC Technology & Florida RF Labs HPJ2F hybrid couplers.

The pre-amplifier before the signal is sent to the power amplifier is a Freescale MMG3004NT1 high linearity amplifier capable of 17 dB amplification in the range of 400 MHz to 2.2 GHz.

To control the signal strength a MCL 31R5 digital step attenuator sits before the output connector. This is a 31.5 dB attenuator that can work in 0.5 dB steps from a 6-bit serial control interface.

Power Amplifier

The power amplifier uses two stages where the first is a Infineon PTMA180402FL 40 Watt RF LDMOS that through a Xinger II XC1900A-03S hybrid coupler feeds two 90 degree out of phase signals to the output stage transistors which are NXP BLF6G20LS-140 140 Watt RF LDMOS.

The output is recombined in a Xinger II XC1900A-03S hybrid coupler before leaving to the diplexer through a circulator.

[madsbarnkob]

Part 2 of 2 video, with fixed audio as good as possible, it was a low microphone level at the recording stage that was the problem, so also +12dB was possible in editing.