Idea for weak signal decoding at or below noise floor

[rhb]

There are quite a few modes above the MUF, e.g. meteor scatter.

I'd not heard of OFDM.  That looks rather interesting as it would certainly simplify antenna design.  What FPGA are you using?  I have a Zybo Z7-20, MicroZed and Terasic DE-10 Nano which uses  Altera's response to the Zynq, the Cyclone V. My primary project is FOSS DSO FW for Zynq based scopes.  And hopefully any Cyclone V based units which might appear in the future.  I'm expecting it will take 2000-3000 hours of effort. But it's the only way we will ever have a DSO with FOSS FW.  The economics of manufacturing make OSHW impractically expensive.

I'm a complete novice at FPGAs, but an old hand at DSP in recorded time (i.e. reflection seismology).   I also now have for the first time a fairly complete test bench going up to 3 GHz.

[OwO]

I'd not heard of OFDM. 

It's the modulation scheme used in ~everything today including wifi, LTE, and DVB/DAB because of its superior ability to deal with multipath and selective fading over a wide bandwidth.

I have a Cyclone V DE1-SoC but I'm also looking at getting a PlutoSDR and doing signal processing on the Zynq included in it. A custom board with Zynq 7010/7020 is also in the plans.

I wouldn't discount OSHW manufacturing since the price of parts and PCBA services in China makes such a thing feasible and competitive at even just 10 units. Not sure about an oscilloscope but a PlutoSDR (with a zynq 7010) can be built for <$50 each at quantities of 5 to 10.

[rhb]

For other things I completely agree about OSHW.  It's the DSO in particular that's unrealistic.  The analog design is seriously non-trivial and you need really large volumes and a distribution network to compete with Rigol, Siglent and Instek.

I'll be interested to hear what your experience is working on both the Cyclone V and the Zynq.  I learned long ago that writing, compiling and testing no more than 50-100 lines of code at a time on multiple systems made a huge difference in code quality.  It provides an early warning of edge cases which interfere with portability.  I wrote a couple of 15,000 line libraries that had *no* bugs reported in 6 years of heavy use and which continued in service without support for another 6-8 years.

Part of that was careful programming and good  test suites,   but lots of it was compiling with all warnings enabled on multiple systems.  In particular, the AIX FORTRAN compiler caught a large number of violations of the F77 standard.  At that point we had already ported 500,000 lines of VAX FORTRAN to the BSD based  SunOS 4.1 and the Intergraph Clipper chip based 16 character file name SysV implementation.  The IBM took 4 months to clean up the GO TOs, the HP took 4 weeks and I did DEC Ultrix and  and SGI IRIX both in four hours.