MICRO STRIP TRANSMISSION LINE REVERSE LOSS

[rgarnett1923]

Hello All,

I am building a radar system just for the hell of it and am trying out filters and transmission lines on FR4  4-Layer pcb.

I tested a 77 mm long 0.349 mm wide microstrip on a Seeed Studio FR4 4 layer substrate with a 0.2 mm prepreg layer.  The top copper was 1 oz the inner ground plane was 0.5 oz.  The finish was ENIG which I know can have second order effects due to the nickel.

I didn't ask for impedance control.  The T'line is terminated on edge mounted 3.5 mm SMA connectors.

I tested the4 board with an SOLT calibrated TTR506A VNA using high quality test leads. I also tested the board with a RSA607A with a return loss bridge and got the same result.

Sadly the results weren't good.  The S11, S22 reflection coefficients were only OK up to 1 GHz, beyond that they are very poor.  I want to use the board in the 3 to 4 GHz range.  I am inexperienced with UHF board design and request that someone has a look at the attached plots.  I tested the SMA connectors by soldering a couple back to back and only saw about 0.5 db return loss.

I used the KiCad microstrip calculator to design the T'Line. I also checked these results with a couple of other calculators.

The questions I have are:

1. Are the plots typical of FR4 performance
2. Is the performance drop off above 1 GHz most likely due to the board electrical properties or could there be some other reason.
3. Will impedance control by the board manufacturer fix/improve the problem or,
4. Will I have to go to a better rf board material.

I don't really want to go away from Seeed as they have been a very reliable supplier. They do an RF material, but I will have to contact them to find out the details. A lot more expensive than FR4 of course.

Most of the tracks on the radar board will only be 5 to 10 mm long, but there are a couple that will have to about 30 mm long which would result in high losses if my results are anything to go by.

Looking forward to any thoughts on my problem.

RJG

[TheUnnamedNewbie]

I'm not an expert on FR4 performance at any frequency, but those strong ripples suggest that you have a mismatch going on. The fact that the peaks are about 800 MHz apart, and your microstrip is about 77 mm long, suggests that you are just having poor matching between the microstrip and your VNA.

Ideally, you want to make a number of structures on a test board, and do something like a TRL calibration on the PCB material. This allows you to extract what is loss and what is mismatch. I think the low \$S_{21}\$ is largely due to the poor matching - if your \$S_{11}\$ is -1 dB, even with a lossless transmission line you will be looking at about -6 dB \$S_{21}\$.

[hagster]

Surface finish wont make much difference the current flows mostly on the under side of the track.

My guess is that the width of the track is too narrow. Can you create a smith chart. The return loss should rotate round the characteristic impedence of the tx line.

Alternatly you can produce a test PCB with different width lines amd see which works best.

You dont mention how the SMA is connected to the internal ground. I presume with some vias, but details could be important.

You could consider using CPW tracks rather than mstrip. The loss would be better for this, but the design in kicad is harder.

[rgarnett1923]

Hi

Thanks for that.

I will try the VNA with a couple of resistive attenuators. I have a 3 dB and a 10dB both good to 18 GHz.

I have heaps of via stitching on the board including the earth pads of the SMA connectors. So I think the ground plane is OK.  I will check that the vias are stitched to the ground plane and that I haven't done something silly like leaving the ground plane unconnected to the net.  I have kept the top ground plane 2mm away from the microstrip line.   Maybe that is insufficient.  It would definitely be suspect with a wider track.


I interpret your comments about the ripples as meaning the thing is way off.  I looked at the Smith chart and it was a shocker.  Looking at the Smith chart, the impedance is way too high so I think your thoughts about the track width being too small are on-the-mark.  I will do the Smith charts with the attenuators and post them.


I did try coplanar tracks, but they were worse!

The problem with coplanar with the ground is the ground plane has to be 10 to 20 times the track to channel distance so you have to mask out the ground layer because the FR4 4-layer boards only give you 0.2 mm.

The frustrating thing is the calculator calls for 0.34 mm track and that is exactly what Seeed did.  So I'm obviously doing something wrong.

I will try and post a px of the board.

Can you advise what microstrip calculator you use or do you do it from the formulae?  The 0.34 mm width I got from a couple of different calculators. 

Regards

Rob

[TheUnnamedNewbie]

I did try coplanar tracks, but they were worse!

The problem with coplanar with the ground is the ground plane has to be 10 to 20 times the track to channel distance so you have to mask out the ground layer because the FR4 4-layer boards only give you 0.2 mm.

I believe FW-CPW/FW-CPW-G are more sensitive to manufacturing error, often because the gap is smaller (if you have a 50 um error on a 200 um gap it's impact will be far worse than, say, a 50 um error on a 350 um wide micro strip conductor). What you mean with that last bit I don't know. If you go for FW-CPW-G, you can have your groundplane as close as you want, it will just impact your capacitance.

The frustrating thing is the calculator calls for 0.34 mm track and that is exactly what Seeed did.  So I'm obviously doing something wrong.

You are assuming there that the \$\epsilon_{R}\$ of your FR-4 is exactly known and precisely controlled - which it is not. Try shifting around the \$\epsilon_{R}\$ of your substrate a bit in your calculator - especially at a few GHz, this will impact your performance.

Show some more images: your connector, footprint, etc. Also, I think you made a error in your first post, and you just have SMA connectors. For this application, going for actual 3.5mm connectors would be silly and a waste of money. The performance of SMA will be fine, and already far better than what you can get out of a FR-4 substrate.

[hagster]

I used  the emtalk one http://www.emtalk.com/mscalc.php

What Er did you pick? I used Er=4

[jungle vegetable]

FR4 boards without impedance control will often have surprisingly different impedance compared to what could be calculated via published Er values and there will be additional variation between batches.

To make things worse, Er also depends on frequency:


The good news is none of this matters if your tracks are short and your design is tolerant to reasonable reflections

(Btw, if Seeed uses the same Shenzhen PCB shuttle run factory as everyone else, I found that ~0.3mm tracks get me within +-15% of 50 ohm for the same stackup)

[jungle vegetable]

Also, if your VNA has TDR mode (or you are able to convert S-params to time-domain waveforms via other means), it could be instructive to look at the impedance profile of your PCB and connectors. 6GHz bandwidth translates to ~3-4 mm spatial resolution on FR4

[rgarnett1923]

Hi All,

I re-did the VNA measurements and plotted Smith charts which are attached.  You can see from S11, S22  that the impedance seems low, not high as I said before.  I have attached screenshots of the board with some dimensions and the result dialog of the emTalkCalc and KiCad pcb calculators.

emTalk:  Width => 0.367 mm
KiCad:    Width => 0.35   mm

I fiddled around with the er value.  You need an er of 15 to get the impedance down around 30 ohms. I have attached the recalc done using e the em Talk calculator. Can the er be expected to change by this much from the expected value?

Just to note; I kept out the solder mask from above all of the microwave tracks on the test board.  A paper I read by Rogers said that solder mask has a big impact on filters and a bigger impact on T'Lines than ENIG does.

Maybe the ENIG for my board has a lot more nickel which has a relative permeability 100 to 200 times that of air.  Though I would have thought that this would push up the impedance - not down.

I will have another look at the Rogers paper.

The link for the Roger's paper is https://www.rogerscorp.com/documents/2341/acm/articles/Ambiguous-Influences-Affecting-Insertion-Loss-of-Microwave-Printed-Circuit-Boards.pdf


On the coplanar tracks: I had a look at the Keysight website as they have a lot of stuff on microwave boards and the recommendation for the coplanar transmission line with ground states that:

W + 2 × G ≤ 10 × H

Where W = track width, g = gap to top ground plane and H is the height above the lower ground.  For a 0.3 track with a total of 0.1 gaps this means H would have to be 10 x 0.5 = 5mm.  Seems a lot to me, but have a look at the web page http://edadocs.software.keysight.com/pages/viewpage.action?pageId=5928544.

I would appreciate any further thoughts you have.

[rgarnett1923]

Here is a photo of the board

[hagster]

Perhaps the pre-preg is being compressed down to less that 0.2mm.

[TheUnnamedNewbie]

The resolution of that board is quite low so it is hard to see anything clearly.

On the coplanar tracks: I had a look at the Keysight website as they have a lot of stuff on microwave boards and the recommendation for the coplanar transmission line with ground states that:

W + 2 × G ≤ 10 × H

Where W = track width, g = gap to top ground plane and H is the height above the lower ground.  For a 0.3 track with a total of 0.1 gaps this means H would have to be 10 x 0.5 = 5mm.  Seems a lot to me, but have a look at the web page http://edadocs.software.keysight.com/pages/viewpage.action?pageId=5928544.

I would appreciate any further thoughts you have.

This suggestion is just because they want to ensure your structure favors the CPW mode, instead of a microstrip mode. If you move the ground close, you will have a hybrid between the two. I have often designed with circuits where that condition is violated, without issue - you just have to ensure clean modes.

[ejeffrey]

What SMA connector are you using?  What footprint are you using for the connector?  I doubt your trace impedance is 30 ohm, but you could have a big parasitic capacitance or inductance at the launch if it isn't properly designed or you used the wrong connector.

TDR mode would be really useful here. If your VNA doesn't have that functionality you can calculate it yourself from the S11 data.  That would let you tell the difference between discontinuities at the connectors vs. an impedance mismatch on the microstrip.

[Mr. Scram]

Hi RJG! You may not be aware that using all capitals is considered shouting in current internet convention, as all your topics seem to have a title like that. I know using all capitals didn't always signify this before the dawn of the internet, so I thought I'd mention it.

[rgarnett1923]

I'm sorry Mr Scram,

I was not shouting.

I see the "Subject:" field as a heading at the start of the document and capitalize it so that the heading stands out.  It is normal to capitalize headings in documents. This makes the individual documents in a list easier to sort through when both the heading and part of the body of the document are listed.  You will note that I do not use capitals in the body of the document in this way - so I am not shouting at anyone.

We all have our own styles and that just happens to be mine.

I was well aware that using capitals could be interpreted as shouting, however when the body of the document is mixed case,  I would think that this is OK. I think that the internet can find a space for differing styles of writing. 

I saw some  obscene language on this website the other day with racial connotations which are more of a worry than someone who capitalizes the title of a topic.

I think the tone of a post should be indicated by, a certain humility, a politeness of approach, lack of judgemental slurs and comments and lack foul language; in other words, content and language rather than lettering.  I am not in any way accusing you of these things, but there are plenty of others who do this sort of stuff.  I find it appalling. 

Perhaps in future, I will just capitalize the start of each word of my subject, but I am not sure how this will be interpreted. My favourite style of heading is fully capitalized but with the starting character of each word 4 points or so larger than the other letters in the word.   I don't think you can't do this in this forum as you cannot apply styles to the heading. A pity I think.

e'g  MICRO STRIP TRANSMISSION LINE REVERSE LOSS

Best Regards

Rob

[rgarnett1923]

Hello,

I was thinking that the prepreg thickness could be the answer. The discrepancy  has to be due a massive increase in Er over the assumed Er or the prepreg thickness, as the track size is spot-on as I checked it with a microscope and measurement grid.

I have sent all the info off to Seeed studio so hopefully they may be able to help.

It's strange because I also made a quarter wave bandpass filter on the test board and it was pretty close to the design and quite usable.   

Regards

Rob

[rgarnett1923]

Hello,

Additional on the prepreg issue.

Using the KiCad design calculator if I reduce the prepreg from 0.2 mm to 0.15 mm the impedance drops to 42 ohm which would not be too bad, but if I increase the Er to 8 I get 33 ohm, so maybe it's a combination of things.  I would suspect that if the prepreg is thinner then the electric field strength per meter in the prepreg would be higher which could change the Er and also the tan Delta. The same sort of problem you get with low voltage cap nonlinearity.  Although the signal levels under the VNA test conditions are pretty small so I am doubtful of this theory.

Regards

Rob

[TheUnnamedNewbie]

Hello,

Additional on the prepreg issue.

Using the KiCad design calculator if I reduce the prepreg from 0.2 mm to 0.15 mm the impedance drops to 42 ohm which would not be too bad, but if I increase the Er to 8 I get 33 ohm, so maybe it's a combination of things.  I would suspect that if the prepreg is thinner then the electric field strength per meter in the prepreg would be higher which could change the Er and also the tan Delta. The same sort of problem you get with low voltage cap nonlinearity.  Although the signal levels under the VNA test conditions are pretty small so I am doubtful of this theory.

Regards

Rob

If you are changing the \$\epsilon_{R}\$ of your material that much you are on to something, people will want that material for stuff like modulators.

Currently, I suspect you might have some significant issue going on at your connector interfaces. Could you give us high-resolution images, nice and close-up to the connectors? In addition, PCB layouts could help - I could see if I can put them through ADS of HFSS...

[jungle vegetable]

Er going to 8 or more is very unlikely and if you're worried about the prepreg thickness, it's easy enough to check it yourself -- file or cut (sharp box cutter will work) a corner of the pcb where both the surface fill and ground plane is present and look at it through the microscope

[jungle vegetable]

Something like this (total thickness is 1.6mm)

[clockspectrum]

I can appreciate you not wanting to move away from your supplier. I have been using FR408 (Oshpark) as an alternative to the traditional 2 layer FR4 with pretty good luck. I created a TRL board and ran measurements with the VNA which seem to be in agreement with the published specs. I was seeing the calculated effective permittivity of ~2.8 all the way through 6 GHz. The S11 was around -30db through the upper half of the spectrum. Ive run 4 projects w FR408 and all have been pretty consistent.

Matt

[rgarnett1923]

Hi Mat,

Thank's for that.

I will polish up the edge of my pcb and have a squiz through the microscope.

Best regards

Rob

[xaxaxa]

Post a smith chart of S11 with the second port of the transmission line terminated with a 50ohm termination. Also how did you calibrate the VNA and what cal kit did you use?

[rgarnett1923]

Hi,

Tektronix TTR506A with Pico Technology VNA leads calibrated with a Pico Technology SOLT - SMA Male.

The S11 with a 50 ohm SMA terminator gives pretty much the same as the two port measurement.

I also tested the return loss with a Tektronix RSA807A with a tracking generator and return loss bridge and got identical results for S11 with a 50 ohm terminator.

I think I have worked out the problem with a lot of help from the forum of course.


I measured the board prepreg layer and got a thickness of 0.125 mm not the 2 mm specified by Seeed.  The top and bottom prepregs were pretty much the same.

See attached photo.  I used the board thickness as the reference using Mitutoyo digital calipers and got 1.59 mm all around the board (including solder mask).


If I plug this prepreg thickness into the calculators you end up with about 37 Ohms for an Er of 4.6.  If the Er is greater, say 6, you get down to 33 Ohms.  The other issue with such a thin prepreg is that any small deviations from the average will complicate matters even more.


I think the prepreg thickness is the main problem.

I still haven't heard back from Seeed studio. I will pass on this info and see what they say.  If they don't help I have to move suppliers.


Regards

Rob

[in3otd]

I think you got some good hints already:

What footprint are you using for the connector?  I doubt your trace impedance is 30 ohm, but you could have a big parasitic capacitance or inductance at the launch if it isn't properly designed or you used the wrong connector.

Currently, I suspect you might have some significant issue going on at your connector interfaces. Could you give us high-resolution images, nice and close-up to the connectors?

If I do a rough simulation of your line assuming you have some parasitic capacitance at the connector footprints I get the results below. While they do not really match your measurements they clearly show that these discontinuities can produce similar results.
I assume you have relatively wide pads for the SMA center pin and since you need a narrow line width to get an impedance of 50 ohm those large pads will appear as an excess capacitance. Did you design the connector launch to minimize discontinuities?

[rgarnett1923]

Hi All

I got a reply from Seeed and it seems they have changed their stackup for four layer boards, but they didn't change the specs on the website:  their stackup is now

Top Copper (1oz)
0.12mm Prepreg
Second Copper layer (0.5oz)
1.2mm Core
Third Copper layer (0.5oz)
0.12mm Prepreg
Bottom Copper (1oz)

This explains my problem as I worked on 0.2 mm.  I am sadder, but wiser now. But at least my method was sound. I'm also glad I made the test board.  If I had gone ahead with the radar board and mounted all the bits I would have been in for a big disappointment. My prepreg measurement was pretty close too so the money I spent on the microscope camera is justified.

Seeed said that customers can specify a non-standard stack for an additional $170 or specify impedance control and their engineers will do the calcs and I guess size the tracks.

I suppose all this trouble is part of the rich tapestry of rf design. I knew there was some reason I took it on.

Thanks for all your help. 

Best regards

Rob

[xaxaxa]

seems everybody is moving to 0.1mm prepreg these days to support the high density digital shit; not long ago there was a debate on the JLCPCB forums about switching to 0.1mm (from 0.2mm) and people couldn't come to an agreement; RF engineers wanted 0.2mm (including me) and everyone else wanted 0.1mm. now JLCPCB offers both thicknesses (selectable from the UI).

[xaxaxa]

the rule with >2 layer boards is that if you require a specific stackup, you must inquire about it via email prior to ordering even if it's listed on the website (unless the web UI specifically lets you select from a list of stackups)

[in3otd]

This explains my problem as I worked on 0.2 mm

IMHO not completely. If the mismatch seen in S11 came only from the wrong line impedance it should not rise with frequency and peak close to 0 dB as in your graphs; S11 should oscillate around the return loss corresponding to the actual line impedance (see first graph below).
OTOH, if you (also) had discontinuities at the line ends you will see S11 rising with frequency, as the reflection near the connector will become bigger and not be (much) attenuated with frequency (see second graph below).

[rgarnett1923]

Hi All

Just an update,

I got a test board made up at OSH Park with the correct 0.2 prepreg.  The results were better, but still not acceptable.

I then realised  I had done a silly thing.  I had extended the 0.2mm ground plane under the SMA connector center pin pad.  This area yields about 0.9 pf.  A capacitance this size at 3 GHz will certainly bring the impedance way down and be highly reactive.  I modeled the layout with and without the pads and voila, correct answer.  With the pads, I get a virtually identical S11 response as the OSH Park board. Without the pads, I get the impedance you would expect from the theory.

I modified the board design with keep-outs under the SMA center pin pad.

I am 99% certain that will fix it.

Just an aside I soldered two of the SMA connectors back-to-back and got a very good response.

What a knucklehead!!

That was God punishing me for not using the brain.

[rgarnett1923]

Hi All

The problem was I continued the ground plane under the SMA center pin pad which gives a capacitance of about 1 pf at bot ends of the TLine on my test board.

I have put some keep-outs for the copper pour around the center pin.

I am 99% sure this is the problem and the keep-outs will be the fix.

I have attached the plots for the OSH Park board with the 0.2 mm prepreg with no keep-outs. Better than the other board, but pretty horrible.

I also tested a couple of the SMA connectors back to back (no pc board) and found they have a very good response.  I have attached this.