SiGe 0.25um TXLine Calculations

[tec5c]

Hi all,

The final task for my degree consists of designing a passive MMIC marchand balun that operates in the frequency range of 20GHz-40GHz, with required specifications of:
phase balance < 2 degrees;
magnitude balance < 0.1dB;
S11 < 10.5dB.

The design is being done in AWR, using a 0.25um SiGe process (IHP PDK). I have zero experience in balun design and considering that the EM simulations take 20+ minutes to run, fiddling around with different microstrip configurations (broadside coupling, edge coupling etc) and running the simulation just seems futile and too time consuming.

I have tried using TX Line in AWR in order to get the microstrip characteristics though I am not too confident in the results, as the calculated width of the strip is absurdly large (in terms on MMIC design).

Does anyone have any experience in this field that might be able to offer me some advice with the design?

I can provide images of various attempts and measurements that I have so far if needed.

Any feedback is appreciated.



I am editing this thread for more updated/accurate questioning.

As mentioned in the original post, the process I am using is a 0.25um SiGe BiCMOS one. Looking at the substrate information that is provided within the PDK shows that the dielectric constant for the layers I will be using is 4.1, loss tangent is 0.01. It also provides the thickness for each dielectric layer and the material properties of the metal layers.

Using these within TXLine seems to give this warning:



Here are the dielectric layer properties, I am using layers 4 and 5:



Here are the metal layer properties, I am using ThickAluminum1 and ThickAluminum2:



Am I missing something here? Or can the warnings simply be ignored?
I am currently running an EM simulation while ignoring the warnings to see what the results are like...

[Marco]

I have no knowledge about ASIC design, but I presume the warning is there because photolithography is not perfect, especially at the edges. The larger T/H and/or T/W the greater impact that will have on the properties of the physical circuit.

In the opinion of the design software, you're doing it wrong because of that.

[rfeecs]

Those warnings are because TXLINE uses a closed form equation to do it's calculations and it is approximately valid over a range of thickness to width ratios.  You are out of that range.

The layer you have chosen is ridiculously thin.  This is going to result in line widths that are also too thin and probably high losses.

Can you try using a thicker layer?  Layers 2, 3, and 4 look better. 

You are going to have two coupled lines, probably broadside coupled, and look at the even and odd mode impedances.  They are going to be in the area of 50 ohms.  You can try starting with ideal coupled lines and design your balun.  Then look at how to realize the lines with the same even and odd mode impedances.

The lengths are going to be around a quarter wave length, so no getting around that.  You can play with the layout, say make a square or spiral, to try to make it more compact.

Do you have access to IEEE Xplore?  Or a library?  No need to re-invent the wheel.  There are tons of references on Marchand baluns.

[tec5c]

The layer you have chosen is ridiculously thin.  This is going to result in line widths that are also too thin and probably high losses.

Can you try using a thicker layer?  Layers 2, 3, and 4 look better. 

Yes, I was concerned with the thickness of layer 5, as it is absurdly thin. However this what corresponds to ThickAluminum1 and 2 (TopMetal 1 and 2), which is what we were told to use. I'll be speaking with my supervisor about this tomorrow so I will inform you once I find out more.

Do you have access to IEEE Xplore?  Or a library?  No need to re-invent the wheel.  There are tons of references on Marchand baluns.

I have access to Xplore when I'm on campus, so I need to do a bit more reading. I understand the overall design of the Marchand balun, there's just a few things within the PDK and the stackup that I need to clear up I think.

You are going to have two coupled lines, probably broadside coupled, and look at the even and odd mode impedances.  They are going to be in the area of 50 ohms.  You can try starting with ideal coupled lines and design your balun.  Then look at how to realize the lines with the same even and odd mode impedances.

The lengths are going to be around a quarter wave length, so no getting around that.  You can play with the layout, say make a square or spiral, to try to make it more compact.

When you say "ideal coupled lines", do you just mean the microstrip model that is provided in AWR library as opposed to drawing the path yourself?

Ports 2,3 are quarterwave and so input port is half wavelength, right?

Thanks again.

[rfeecs]

When you say "ideal coupled lines", do you just mean the microstrip model that is provided in AWR library as opposed to drawing the path yourself?

Ports 2,3 are quarterwave and so input port is half wavelength, right?

Thanks again.

By ideal coupled lines I meant the CLIN element, which is really ideal in that you just specify even and odd mode impedances and the phase at a given frequency.  I like to start by playing around with the ideal case to try to understand the basic principles, then go to the microstrip model, then the full EM.  But you may want to skip some of those steps.

If I recall, you have two sets of transmission lines or coupled lines that are a quarter wave length at some frequency, so the whole structure would be a half wave length.  I also seem to recall that you may end up with a small resonance or "suck-out" at that half wave frequency.

[KJDS]

TxLine uses Hammerstad and Jensen's equations for microstrip.

The structure you are specifying does fit within the boundaries that the microstrip equations are valid for as:-

a) you have metal that is very thick
b) you have Si0 on top of it.

The microstrip calculation will give a starting port, but the end result will be a narrower line, though probably only by about 25%.

[tec5c]

Thank you for the replies.

I understand where I was making my mistake. I was taking the height of the substrate of the single layer, rather than including the other layers that are beneath the appropriate layer of interest. Hence why such a thin layer of dielectric was inappropriate. I have no idea how I missed this, but that's just the way it goes some times! 

I should have also mentioned that, currently, there is no ground plane implemented. There is only a groundring, so TXLine calculations are not really appropriate for the sake of the design thus far.