Author Topic: EMC, layer stack and noise  (Read 1367 times)

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Offline fredboivinTopic starter

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EMC, layer stack and noise
« on: October 03, 2014, 01:51:22 pm »
Hi, this is my first post here!

I've been watching many electronics blog for the past few years and EEVBlog is one that never fails to entertain and teach me. Keep up the good work!

So I finished electronics engineering and landed my first job in the field and one of my projects include designing a circuit to pass tight regulatory tests. I've been reading a lot about it and there is so many details that need to be considered to reduce EMI, crosstalk, noise, etc... like layer stack, power plane stretch, via stitching, power decoupling, differential pair routing, line termination, filtering and so on.

I think it would be very interesting to do a more in depth follow-up to episode #548 with emphasis on conception.

Thanks!
 


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