BG7TBL phase noise comparator

[jhenderson0107]

I am interested in the NS-CMP product advertised on eBay at (https://www.ebay.com/itm/122376396168).   I have not been able to locate a theory of operation (or a manual) for this product, so have inquired with the designer. 

I am guessing that the circuit incorporates cascaded frequency multipliers (not a mixer) to increase the input frequency by a factor of 260, thus increasing the phase noise by 20 log (260) = 48 dB.  This would increase the phase noise my GPSDO by ~48 dB, raising it above the -117 dB/rHz @ 10 kHz noise floor of my Agilent 8562EC analyzer, permitting analysis. 

Do you think this is correct? 

[jpb]

It looks interesting. I would like to hear what you find out.
Frequency multipliers other than 2, if my understanding is correct, need tight band-pass filters to get rid of the unwanted harmonics. The frequency multiplication could be done in a PLL but then that would be difficult with the wide input frequency range of 1MHz to 100MHz.

EDIT: realise I read the thing too quickly - the factor is 260 not 48. This seems unlikely to be frequency multipliers as it contains the factor 13 - a 13 times multiplier would require filtering of the much higher content at 3, 5, 7, 9 and 11 times and I can't see this working over the range 1 - 100MHz.

For simply multiplying the phase noise (frequency deviation) then I would have thought that a PLL approach would be cleaner as in :
http://www.wriley.com/The%20PicoMult%20Frequency%20Error%20Multiplier.pdf
but that approach only works for a specific frequency input.

So I am puzzled and hope you can get some further information from the designer.

EDIT: my best guess is that a frequency synthesizer is used with a programmable PLL but a means of knowing the input frequency would be needed.