The output of Op-Amp U1B (being closed loop) will attempt to do whatever is necessary to make the voltage difference between the inputs zero. If you imagine the switches SW1 and SW2 to be in the CV positions then note the following: (1) That the negative input of the op-amp is being fed by a reference voltage formed by a voltage divider from the 12v supply rail. (2) The positive input of the op-amp is being fed by a scaled version of Vin.
The output of the op-amp is connected to the MOSFET Q1 whose channel resistance is adjusted based on the voltage present on its gate as dictated by the op-amp. If one assumes that the power source under test has a output current limit then it can be theorized that once you start shunting enough current, the voltage will drop as its current limit is approached. When that happens, the voltage being fed into the positive input of the op-amp drops and the voltage on the output of the op-amp decreases thereby decreasing the voltage present on the gate and increasing the channel resistance leading to less current being shunted.
There are a lot more details/exceptions than what I have mentioned above but that is the gist of it without going far into it.