heh, there are two "errors" in my schematics:
- FPGA sheet, U13 (Q. oscillator) have wrong value (QSMO_4200 - that's copy/paste error), should be 100MHz
- FPGA sheet, RA06_1 have no value, should be 4 x 1k
- many ferrite bead have no values, well go figure, from what i measured they Wuerth 742792038 could be good.
- on Front Panel sheet UF4 have no decoupling cap, should be 100nF
Someone asked my what are the LX1-LX7 on Power Distribution sheet - the answer is "nothing", that's just
the piece of wires between PSU and main PCB.
Can it be fixed booting bug in the CPLD with
self-calibration relay ?
we don't have CPLD design from hw0 (where this is working) nor hw1007 (where seems to be bug inside)
and i doubt Hantek/Tekway will provide us one (because then you/others can easy clone their DSO).
But even if we would have both designs, there is no warranty that hw0 design will work on hw1007 board,
this can be only fixed/answered by HanTekway - and i doubt they will even answer it. Not because they
don't know/wish (what) to answer, but because what's next ? Recall action ? Definitely not, a simple
answer is just don't connect any signal while booting and your fine.
And if you really have to boot with signal connected to DSO (for what? the only case might be to be proteced while
DSO crashed) and wish to fix it now, then an inverted RC combination on 595 (in each input channel) will help you.