HP Logic Analyzer Inverse Assemblers

[TimInCanada]

What is an Inverse Assembler (IA), and why would I want one?

If you are using a logic analyzer to watch the address and data buses of a microprocessor, values on the data bus represent the CPU's opcodes and operands which are the addresses and data moving to/from the CPU and I/O and memory.  An inverse assembler is a kind of disassembler that translates bus data into the CPU's assembly language.  It is a piece of software that has to be installed on the analyzer before use.

Modern microprocessors include features such as JTAG for debugging, but vintage microprocessors don't.  A logic analyzer with an IA makes it much easier to reverse engineer or debug an old microcomputer.  It doesn't give you the assembly language source of the program, but instead shows the stream of instructions that are executed and the data they operate on.

As part of the HP 64000 Logic Development System launched in 1979, an "inverse assembler language", IAL, was created and has been used by HP logic analyzers since. An IAL source file has a .S extension.  It is assembled into a .R relocatable file which is formatted for and installed on particular analyzers. 

Operation

A separate IA is required for each microprocessor.  They only operate in the Listing view of State analysis, and just decode the data on the current screen rather than all the acquired data.  The operating manual for each logic analyzer gives the details of how to install an IA.  To use it, the analyzer is connected to the address, data and status buses of the CPU and in the Format menu are given the labels ADDR, DATA, and STAT, respectively.  The IA needs to provide information on how the status lines are to be connected  This is usually in a configuration.txt file.

Once data is acquired, in the Listing view under the label DATA there is a base selector which normally defaults to Hex.   Select the field labeled "Invasm" and the inverse assembler will be activated.

Automatic/Manual Code Detection: Some processors, such as the 6502 and 8085, have status lines which indicate when a byte fetched from memory is code rather than data.  The IA reads the status lines and automatically determines which lines on the display are code.

For other processors, the IA needs to be manually synchronized.  When an IA  that needs manual syncing is loaded there should be a "Invasm" Field displayed on the Listing page.   Scroll the listing up or down until a known code instruction is in the top line,  then select the "Invasm" field.  The IA will start decoding that line as an opcode.  The listing can be scrolled down and the IA will stay in sync, but it will not stay synced when scrolling up.

Naming Conventions

Some of the software that deals with IA files require file names to be 10 characters or less, starting with an upper case letter, letters or numbers or underscore characters only.

The general convention is:

• First letter of "I" means it is the IA file.
• First letter of "C" means it is a configuration file.
• Last letter of "P" means the IA file is for use with general purpose probing (e.g., flying leads).
• Last letter of "I" means the IA file is for use with dedicated hardware interfaces (often called "preprocessors").

Inverse Assemblers by Processor:

• invasm_v3.zip contains inverse assemblers for the
  
  • 6800, 6809
  • 68000, 68008, 68010, 68020
  • 8085, 8086, 8088
  • 80186, 80188, 80286, 80386
  • NSC800
  • Z80 
  In addition to the configuration and IA files, there are relocatable *.R and Invasm Field Option *.info files. (Big thanks to MarkL  )
• INVASM_SRC.zip contains the decompiled source code for the above IAs.  (Big thanks to gslick  )
• Details on Z80 STAT bus connections
• 6502 (includes .S and .R files)
• 8008 (includes .S and .R files)
• 10342B_IA.zip contains IAs for the 10342B HPIB, RS-232, RS-449 bus decoder probe.  (Big thanks to gslick  )

Logic Analyzer Notes:

1611A
This is more for historic interest.  The 1611A Logic State Analyzer was described in the January 1977 HP Journal.  It used "personality modules" for each microprocessor that included an IA in ROM.

1630/31

• A discussion on using IAs on these analyzers.
• Formatted IAs for the 6809, 68000, HPIB, RS232 and RS422.
• Introducing the HP1631D
• Another discussion about getting IAs onto the 1630.

1650/16500/1660/1670

• IA files for each of these is compatible with the other models.
• Z80 (ImageMagic disk image for 1650)
• Some 1650 software utilities including some Pascal source code (may work with other analyzers too).
• HP1652B Inverse Assembler
• HP16500B Experiences

16600/16700

• Loading preformatted IA files:
• Copy the IA file into a temporary directory. (Don't forget to set public read permission on the file.)
• Use the File Manager to load the IA file you just put on the analyzer.
• The File Manager does necessary formatting and puts its IA file into the  /logic/ia directory.
• From the Listing screen, select Invasm then Load...
• If the above doesn't work,
  
  • Copy a IA relocatable .R version of the file onto the analyzer.
  • Use the  IA Format Utility to convert the file and load it into the /logic/ia directory.
  • From the Listing screen, select Invasm then Load...

1680/1690/16900

• The relocatable .R files don't work directly on these analyzers, and involves creating a .DLL wrapper around them.

Getting IAs onto an analyzer:

• Older analyzers with floppy drives often used the HP LIF format for the floppies.  The HPDir software can create LIF format floppies on a Windows PC.
• There are also LIF Utilities for linux.
• Some IA files turn up in ImageDisk .IMD format.
• The HPDrive software can emulate an external disk drive, but this requires a PC with a GPIB interface card.
• The IALDOWN utility in the IAL development package transmits IA files to an analyzer over RS232.  It must be run in DOSBOX with the serial port configured.

Symbol Names

In addition to the IA, a handy tool when working with microprocessors is to create a Symbol Table of known addresses, such as memory-mapped I/O units and variables.  See your analyzer operating manual for specific details of creating a symbol table.

In the Listing display under the label ADDR there is a selection for the base (format) to display addresses in.  The default is usually "Hex".  Change this to  "symbol" and any addresses that are in the symbol table will have their names substituted in the listing.  If a Symbol Table is loaded, the IA will also use these address names in its output.

Source Code Viewer

The 16700 analyzers have the B4620B Software Correlation Tool option.  The analyzer comes with the tool installed, but needs a license to use.  Fortunately, the license file is available for non-commercial use (along with licenses for the other options).

Normally, source code would be compiled with a debug option and after capturing data with the analyzer the source code could be stepped through in the Source viewer while the corresponding line is highlighted in the Listing viewer, and vice-versa.  When reverse engineering old uPs, it is unlikely the source code is available.  However, the Source viewer can still be useful if the uP's code is disassembled into a listing file that gives the addresses of each line of code.  (If a disassembler doesn't create such a listing file, an assembler can be used to re-assemble the disassembled code and generate the listing file.)

The 16700 Help Volume, page 197 gives the General-Purpose ASCII (GPA) Symbol File Format.  The symbol file is just a text file that is placed somewhere on the analyzer's drive and loaded from a Symbols tab. 

Here is an example.  Suppose a piece of assembly code in a listing file called test.lst is:

Code: [Select]

dc19 : b701d0            staa CmdTableIndex
dc1c : 86ee              ldaa #$EE
dc1e : b101d0            cmpa CmdTableIndex
dc21 : 2609              bne LDFAA ; branch if valid CmdChar
dc23 : bdd6c0            jsr subResetCmdFlags
dc26 : 7ee3a0            jmp LE768 ; set flagCmdParse bit6 and rts

The first column is the start address of each line of code.  The symbol file is given a [SOURCE LINES] section, e.g. for this piece of code:

Code: [Select]

[SOURCE LINES]
File: test.lst
...
9029 dc19
9030 dc1c
9031 dc1e
9032 dc21
9033 dc23
9034 dc26
...
The file test.lst is placed in the analyzer's /logic/source/ directory.  The first column is the decimal line number in the source file and the second column is the hexadecimal address.  (A spreadsheet can be used to manually extract the address values and add line numbers, for example.)  The symbol file is loaded in the normal way.   When run to this code, the Listing view will display (at address dc1e):


From the Listing view, on the menu bar at the top of the screen select Source/Open Source Viewer...  The viewer displays the source file and highlights the corresponding source line:


The program execution can be stepped forward and backward and the captured data can be searched to see if particular lines of source were executed.  The listing view shows data values that were passed, for instance, the CMPA (6800 Compare Accumulator A opcode) shows the value 07 was read from memory as the value of variable CmdTableIndex.  In addition, analyzer trigger points can be set at particular lines of the source, similar to breakpoints in emulators and debuggers.  The Listing Display Tool Help Volume pages 24-39 gives details.


Writing an Inverse Assembler

If you wish to write your own IA, the HP 10391B IAL Development Package includes sample source files for the 8085 and 68010 and an assembler to convert the .S source files into .R files for the analyzers.  This software needs to run on a DOS computer or in DOSBOX.  A hint on setting up this assembler.

If anyone has additional files, they can be posted as attachments and links can be added here, too.

Thanks!

Tim

[gslick]

Been looking for an inverse assembler for the MC6800.  Haven't found one yet, but thought it might be worthwhile to summarize what is available.

The file "invasm.zip" is available in the files section of the "HP/Agilent Test Equipment" Yahoo group if you search for it there in the files section. It is a restricted group and you have to join the group first to access the files section.

https://groups.yahoo.com/neo/groups/hp_agilent_equipment/info
https://groups.yahoo.com/neo/groups/hp_agilent_equipment/files

The file is small enough that I can attach it here. It contains the following set of configuration and inverse assembler files.

c68000_i
c68000_p
c68008_i
c68008_p
c6800_i
c6800_p
c68010_i
c68010_p
c68020_i.p
c6809e_p
c6809_i
c6809_p
c80186e_.i
c80186_i
c80188e_.i
c80188_i
c80286_i
c80386_8.7
c80386_i
c8085_i
c8085_p
c8086_i
c8088_i
cnsc800_.i
cz80_i

i68000_i
i68000_p
i68008_i
i68008_p
i6800_i
i6800_p
i68010_i
i68010_p
i68020_i.p
i6809e_p
i6809_i
i6809_p
i80186e_.i
i80186_i
i80188e_.i
i80188_i
i80286_i
i80386_8.7
i80386_i
i8085_ip
i8086_i
i8088_i
insc800_.i
iz80_i

In the particular case of the 6800 / 6802 CPU the 64672A 10307B preprocessor interface contains a non-trivial state machine that does some decoding of the instruction stream as it is executed to provide addition state information that is not available with the general purpose probe version of the configuration and inverse assembler.

[gslick]

When the c6800_p 6800 general purpose probe configuration file is loaded into a 16510A analyzer module the configuration is as shown in the attached screen captures.

[MarkL]

Great summary, Tim, thanks!

I'll add to the party with another zip archive.  gslick, in a different conversation, gave me enough information (thanks, gslick!) that I was able to write a text decoder for the configuration files he just posted in invasm.zip.  Attached here is invasm_configtxt.zip, which is the same as invasm.zip, but includes the text version of the config files (plus the C program that did the decoding).

In the zip file, for processor XXX:

  iXXXp - inverse assember for general (flying lead) probing
  cXXXp - 16510 configuration for general (flying lead) probing
  cXXXp.txt - text 16510 configuration for general (flying lead) probing

  iXXXi - inverse assember for pre-processors
  cXXXi - 16510 configuration for pre-processors
  cXXXi.txt - text 16510 configuration for pre-processors

The significance of having a readable form of the config files is that you now have a fighting chance to use the inverse assemblers on something other than a 16510 card.

For example, I have a 16702B with a 16752A card and I've been successful using it on a 6802 processor.  I can successfully load i6800_p, the inverse assembler for general purpose (flying lead) probes.  No problem there.  However, the IA wants to interpret the bits in the label STAT to determine what machine cycle to display.  The STAT signal assignments are contained in the companion configuration file, c6800_p.  If I had a 16510 it would be easy.

The decoded text of the configuration says:

  Title: 6800/02 CONFIG FOR GP PROBES 1_0
 
  Pod assigments (? = disabled)
  -----------------------------
  Label  0: ADDR     (16 bits):  A2: ******** ******** 
  Label  1: DATA     ( 8 bits):  A1: ........ ******** 
  Label  2: STAT     ( 3 bits):  A1: .....*** ........ 
 
  Symbols
  -------
  Label: STAT 
         INVALID MEM ACCE  00X
         MEMORY WRITE      010
         MEMORY READ       011
         DMA WRITE         1X0
         DMA READ          1X1

From this, and knowing what signals exist on the 6802, it's apparent that:

  STAT[2] = BA (bus available)
  STAT[1] = VMA (valid memory address)
  STAT[0] = R/W (read/not write)

Creating a STAT label and connecting the bits as defined above works, plus the obvious DATA and ADDR labels.  Screen capture attached.  There's other pins being monitored in the capture, but the IA only cares about DATA, ADDR, and STAT.

I haven't tried any of the other processors, but I've spot-checked the decoded configuration against a few processor datasheets and they at least make sense.  Any feedback welcome, success or not, and especially if I got something wrong with the any of the decoded configs.

Perhaps we should add known working STAT assignments to this post, like the 6802 above, for various processors as people figure them out.

The decoded configuration files for pre-processors is also included, although they're probably not very useful unless you have a pre-processor or looking to build one.


EDIT:  I should also add that in the example the clock is the falling edge of the E signal on the 6802 (or phase 2 clock on the 6800).  I haven't decoded the clocking assignments, but like the STAT assignments this could be figured out after a couple of minutes looking at the datasheet.

[gslick]

To add another note, if you have an IAL style .R relocatable file after the .S file has been run through the assembler, as far as I know there is no simple way to use the .R file with the 16900 series logic analyzer software (also including the 1680 and 1690 series).

However, if you install an older version of the Analysis AddIn Tool there is a wizard tool that lets you build a interpreter wrapper .DLL file around a .R file. It is non-trivial to get set up to do it. The old version of the wizard tool was set up at the time for Microsoft Visual Studio .NET 2003. I did manage to get it set up to build a .DLL file around an assembled .R file from the 8085 .S source from the 10391B tool. I should revisit that and write up some notes about it as I forget exactly what all was involved now.

If you don't have a .R file, or the .S source to build the .R file, I don't know if there is a way to use any of these old IAL style inverse assembler files with the 16900 series logic analyzer software. The files as they are normally distributed are after the IALDOWN tool has done some sort of undocumented transformation of the .R files. Maybe that transformation could be reverse engineered so that a tool could be written to do an inverse transformation back in .R files. Or maybe even disassemble the files back into functionally equivalent .S source files.

[TK]

The STAT bus for the Z80 inverse assembler was described by gslick here: https://www.eevblog.com/forum/testgear/older-logic-analyzer-question/msg1206485/#msg1206485 and it also requires 3 clock signals (missing on the text file).

[TimInCanada]

Man, you guys are amazing.    This is great info.

I just updated the first post.  Please point out any mistakes.  I'm afraid I've got to run.  More later.

Tim

[MarkL]

...
If you don't have a .R file, or the .S source to build the .R file, I don't know if there is a way to use any of these old IAL style inverse assembler files with the 16900 series logic analyzer software. The files as they are normally distributed are after the IALDOWN tool has done some sort of undocumented transformation of the .R files. Maybe that transformation could be reverse engineered so that a tool could be written to do an inverse transformation back in .R files. Or maybe even disassemble the files back into functionally equivalent .S source files.
...

I looked at IALDOWN a while ago hoping it would provide transformation clues for the 1631D:

  https://www.eevblog.com/forum/testgear/searching-for-a-hp-1630-hp-1631-inverse-assembler-files/msg1215139/#msg1215139

In short, all it did was copy the .R file verbatim out the serial port, along with a byte that reflected the user's answer to the number of IA sync states to allow.  This makes me think any transformation/linking happens inside the logic analyzer once the .R file is downloaded.


The .R files appear to have "82 03" for the file magic in the first two bytes.  You can find these bytes in all the iXXX files (at offset 0x227, which includes the 512-byte LIF header).  But unfortunately just extracting that chunk of the file does not seem to make a valid .R file.  The 16700 will happily run IA Format on the extracted piece, but it causes a seg fault when you try to load the result.

Further poking at this shows the IA Format utility only puts a wrapper around whatever file you give it, verbatim.  It also does a couple of sanity checks (maybe looking for 82 03), but it's not going deep enough into the data structures to validate the input.

I was hoping the .R file was still unchanged and sitting inside these iXXX package files, but given the above experiment, unfortunately it's not.  More de-transforming is needed.

Just putting this info out there if anyone wants to dig further.

[TimInCanada]

For example, I have a 16702B with a 16752A card and I've been successful using it on a 6802 processor.  I can successfully load i6800_p, the inverse assembler for general purpose (flying lead) probes. 

Hi Mark,

I've also got a 16702B, with 16712A and 16555A cards, but the i6800_p file isn't working for me.  When I try to use the INVASM function on the Listing screen, it says the file is for a 16500 analyzer and needs to be loaded through the File manager.  The file manager gives an error message about a possible filter problem.  The IA Format utility gives an error message that it's not an "IAL" file. 

I just saw your post mentioning the first two bytes being "82 03" and tried putting those in the file.  The IA Format utility now converts the file, but when trying to load the IA on the listing screen it gives an error about file manager handle not found.

Have you run into any problems like these?

The IA asm.exe file contains the text "@(mktid) 64851S006    USER DEFINABLE ASSEMBLER                 A.02.10 10Mar88 14:20:13" .  64851 happens to be HP-UX Hosted Cross Assembler/Linker User Definable, if that might help in figuring out what it does.

Tim

[MarkL]

Hi Tim,

It's true the IA needs to be loaded through the File Manager.  But you only need to do it once.  Once it's loaded, the analyzer creates a special version for itself in the /logic/ia directory with the same name.  You can then use the Lister "Invasm" pulldown to load the same IA next time around.

And when I say "File Manager", I mean the file manager utility, which is the little folder icon, and not the File pulldown.

Also, before you load it, you should define ADDR, DATA, and STAT fields in the pod Format tab.  If you don't, the IA will complain that those fields don't exist and refuse to load.  It's expecting the configuration to load first and take care of this, but the 16510 config files can't be loaded on this machine.  The IA only cares that the fields exist and have between 1 and 32 bits, so they don't have to be right to start; you can go back and fix them up before doing an actual capture.

I haven't seen any loading errors referring to a "filter", although it will tell you there's no compatible instruments if you try to load the 16510 configuration file (cXXX).  Which IA are you trying?  I haven't tried them all, but I can try the one that's giving you trouble.

I don't think it should matter what card you're using, but this works on 16752A and 16717A cards for me.  I'm running 2.90 which is the latest (and last available) version for the 16702B.


Interesting find on the 64851 User Definable Assembler.  I'm guessing it was used to generate the parsing table that asm.exe uses (in HP64700/TABLES/AIAL).  Maybe 64851 will provide some clues on the .R files.  I'll take a look.

[gslick]

I should spend some time looking at the 16900 series Analysis AddIn Tool. It might contain enough information to write a tool to decode a .R file back into something that could be assembled again with the IAL assembler.

For example it contains this instruction opcode table. The opcode bit field positions vary in the instruction word based on the values of high order bits in the instruction word.

Code: [Select]

  /* definitions for the different unique bit patterns for each instruction
   * in the different instruction groups -- used by the interpreter
   */

  /* instruction group 1 */
  const u_int16 IF_OP = 4;
  const u_int16 IF_BITS = 5;
  const u_int16 ICASE_OP = 6;
  const u_int16 ICASE_BITS = 7;

  /* instruction group 2 */
  const u_int16 IGO_TO = 4;
  const u_int16 ICALL = 5;
  const u_int16 ISTR_OUTPUT = 6;
  const u_int16 INUM_OUTPUT = 7;

  /* instruction group 3 */
  const u_int16 ILOAD_ACC = 8;
  const u_int16 IADD_ACC = 9;
  const u_int16 ISUB_ACC = 10;
  const u_int16 IAND_ACC = 11;
  const u_int16 IOR_ACC = 12;
  const u_int16 IXOR_ACC = 13;
  const u_int16 ITAG_WITH = 14;
  const u_int16 INP_ABS = 15;

  /* instruction group 4 */
  const u_int16 ISTORE_MEM = 4;
  const u_int16 INC_MEM = 5;
  const u_int16 IDEC_MEM = 6;
  const u_int16 INP_ABSQ = 7;

  /* instruction group 5 */
  const u_int16 INP_REL = 2;
  const u_int16 INP_RELQ = 3;

  /* instruction group 6 */
  const u_int16 IROT_LEFT = 8;
  const u_int16 IROT_RIGHT = 9;
  const u_int16 IEXT_BIT = 10;
  const u_int16 IPOS_ABS = 11;
  const u_int16 IPOS_REL = 12;

  /* instruction group 7 */
  const u_int16 INOP = 16;
  const u_int16 ICOMP_ACC = 17;
  const u_int16 ITWOCOMP_ACC = 18;
  const u_int16 IRETURN = 19;
  const u_int16 ION_TRACE = 20;
  const u_int16 IOFF_TRACE = 21;
  const u_int16 IABORT = 22;
  const u_int16 IFNOT_MAP = 23;
  const u_int16 IMARKLINE_O_NA = 24;
  const u_int16 IMARKLINE_S_NA = 25;
  const u_int16 IMARKLINE_O_A = 26;
  const u_int16 IMARKLINE_S_A = 27;
  const u_int16 IMARKSTATE_DISP = 28;
  const u_int16 IMARKSTATE_SUP = 29;
  const u_int16 INEWLINE = 30;
  const u_int16 IFETCH_POSITION = 31;

If I have this correct, the mapping from opcode words to instructions in .R files is the following:

Code: [Select]

/* instruction group 1 */
/* conditional instruction -- bit 15 is set */
/* instruction = (opcode >> 13) */

100x xxxx xxxx xxxx     IF_OP = 4
101x xxxx xxxx xxxx     IF_BITS = 5
110x xxxx xxxx xxxx     ICASE_OP = 6
111x xxxx xxxx xxxx     ICASE_BITS = 7

/* instruction group 2 */
/* transfer/output instruction -- bit 14 is set */
/* instruction = (opcode >> 12) */

0100 xxxx xxxx xxxx     IGO_TO = 4
0101 xxxx xxxx xxxx     ICALL = 5
0110 xxxx xxxx xxxx     ISTR_OUTPUT = 6
0111 xxxx xxxx xxxx     INUM_OUTPUT = 7

/* set immediate instruction -- bit 13 is on */

001x xxxx xxxx xxxx

/* instruction group 3 */
/* math instruction -- bit 12 is on */
/* instruction = (opcode >> 9) */

0001 000x xxxx xxxx     ILOAD_ACC = 8
0001 001x xxxx xxxx     IADD_ACC = 9
0001 010x xxxx xxxx     ISUB_ACC = 10
0001 011x xxxx xxxx     IAND_ACC = 11
0001 100x xxxx xxxx     IOR_ACC = 12
0001 101x xxxx xxxx     IXOR_ACC = 13
0001 110x xxxx xxxx     ITAG_WITH = 14
0001 111x xxxx xxxx     INP_ABS = 15

/* instruction group 4 */
/* single variable instruction -- bit 11 is on */
/* instruction = (opcode >> 9) */

0000 100x xxxx xxxx     ISTORE_MEM = 4
0000 101x xxxx xxxx     INC_MEM = 5
0000 110x xxxx xxxx     IDEC_MEM = 6
0000 111x xxxx xxxx     INP_ABSQ = 7

/* instruction group 5 */
/* input relative instruction -- bit 10 is on */
/* instruction = (opcode >> 9) */

0000 010x xxxx xxxx     INP_REL = 2
0000 011x xxxx xxxx     INP_RELQ = 3

/* instruction group 6 */
/* single operand instruction -- bit 9 is on */
/* instruction = (opcode >> 6) */

0000 0010 00xx xxxx     IROT_LEFT = 8
0000 0010 01xx xxxx     IROT_RIGHT = 9
0000 0010 10xx xxxx     IEXT_BIT = 10
0000 0010 11xx xxxx     IPOS_ABS = 11
0000 0011 00xx xxxx     IPOS_REL = 12

/* instruction group 7 */
/* implied operand instruction - bits 15-5 off, bit 4 on */

0000 0000 0001 0000     INOP = 16
0000 0000 0001 0001     ICOMP_ACC = 17
0000 0000 0001 0010     ITWOCOMP_ACC = 18
0000 0000 0001 0011     IRETURN = 19
0000 0000 0001 0100     ION_TRACE = 20
0000 0000 0001 0101     IOFF_TRACE = 21
0000 0000 0001 0110     IABORT = 22
0000 0000 0001 0111     IFNOT_MAP = 23
0000 0000 0001 1000     IMARKLINE_O_NA = 24
0000 0000 0001 1001     IMARKLINE_S_NA = 25
0000 0000 0001 1010     IMARKLINE_O_A = 26
0000 0000 0001 1011     IMARKLINE_S_A = 27
0000 0000 0001 1100     IMARKSTATE_DISP = 28
0000 0000 0001 1101     IMARKSTATE_SUP = 29
0000 0000 0001 1110     INEWLINE = 30
0000 0000 0001 1111     IFETCH_POSITION = 31


[MarkL]

I should spend some time looking at the 16900 series Analysis AddIn Tool. It might contain enough information to write a tool to decode a .R file back into something that could be assembled again with the IAL assembler.

I think we're starting to find enough pieces.

The link to the manual that Tim posted above on the HP-UX Hosted Cross Assembler/Linker describes the format for relocatable files in Appendix D.  I haven't sat down to write a parser for it (yet), but the IA .R files appear to use at least some of the described record types.

I'm also looking at agIalEngine.cpp from the Analysis AddIn Wizard (which I think is where you got that snippet), and it looks like the parser might already be in there.  If I'm reading it right, "CagIalEngine::read_hdr()" starts right off with validating the "82 03" I found before.

agIalEngine.cpp appears to be a complete implementation of the IA interpreter.

[gslick]

Yes, I extracted that opcode information from the agIalEngine.cpp file in the Analysis AddIn Wizard.

Comparing a listing file produced by running 10391B ASM.EXE on the sample I8085.S file against the a hex dump of the resulting I8085.R file I see some blocks that match between the two but also some extra bytes in the .R file between matching blocks that are not in the listing file. Maybe that has to do with the .R file being broken up into records, with a 128 word maximum per record, where the extra bytes in the .R file are part of the record structure wrapped around the raw instruction words.

I'll have to spend some time looking at the record structure documentation in 64851-97000_HP-UX_Cross-Assembler_Jun89.pdf and the record reading code in the agIalEngine.cpp file.

EDIT: Oh, I'm starting to see now that at least some of the extra bytes in the .R file that are not in the ASM.EXE output listing file are 0x5555 T-parameters before a set of 8 words in a double record, where the 0x5555 indicates that each of the following 8 words is two bytes absolute with no modifications.

[gslick]

Hmm, maybe I figured out what happens to a .R file during the IALDOWN transformation, which apparently occurs inside of the analyzer, not inside of the IALDOWN program itself.

It appears that first a 0x200-byte LIF header is inserted at the beginning of the file. Then a description header is inserted. I'm not sure if that is fixed or variable length. In the couple of files I looked at quickly it was 0x25 (37 decimal) bytes in length. Then the original .R file contents follow beginning with the 0x82 0x03 header bytes.

However, starting immediately after the initial 0x200-byte LIF header the remainder of the file is broken up into 0x00FE (254 decimal) byte length records, except for the final record of the file which may be shorter. Each record begins with the record length word inserted in MSB first order. After the final partial length record it appears that the file is padded out to a 0x100-byte boundary with essentially random data.

So it appears that an IA file that has gone through the IALDOWN transformation could be transformed back into an equivalent .R file by first deleting the 0x200-byte LIF header, then for each record delete the record length word at the beginning of the record, and for the final partial length record delete any extraneous data at the end of the record. Then go back and delete the description header at the beginning preceding the 0x82 0x03 header bytes.

I haven't verified that this is entirely correct yet. This is just from a quick look in a hex editor at a couple of IA files. I should try writing some code to do this reverse transformation process and run it on all of the IA files in the INVASM.ZIP collection, then run them through the IALDOWN process, and see if that results in identical IA files again.

[MarkL]

Ah, very interesting.  I found this same structure of a record length of 0x00fe in the 16510 config files, including a short one at the end, all after the LIF header.

The C program I wrote in invasm_configtxt.zip already parses the 0x00fe records for the config files.  I don't know why I didn't think of looking for it in the IA files also.  It should be simple to modify it to handle the IA files.

[gslick]

If we can successfully transform IA files back into equivalent .R files then we should be able to use the 16900-series Analysis AddIn wizard tool to build those into .R files .DLL files to use on that platform. That would be nice. I wonder why Agilent / Keysight never bothered to provide such tools. Maybe they just thought the old IAs were obsolete enough they didn't think anyone would be interested in using them.

It would also be cool if we can write tools to based on the agIalEngine.cpp interpreter engine to disassemble the .R files back into something that can be assembled again to understand how some of the IAs work, and modify them for various reasons if desired.

[MarkL]

Ok, attached is an extracted version of i6800_p as a test using a horribly hacked version of the configtxt tool.

It works for me.  I copied it onto my 16702B and used the IAL format utility on it.  It created the expected package in /logic/ia and I was able to load that into the Listing window, and this time *without* a segfault.  So, I think you figured it out!

Do you want to try it on your 16900?

I can polish up the extractor and convert the rest of them in the morning if you're successful.

And yes, I agree it would be great to be able to go all the way back to the .S so anyone can customize the IA as desired.

[gslick]

It might take me a while to get setup with the 16900 tools again. I think I had that on an 64-bit Windows 7 system where I installed an XP-mode VM so I could install Microsoft Visual Studio .NET 2003, which might not install or run correctly on Windows 7, or something like that. I might have pulled that drive out of that system. I'll have to see what I did with that. I'd rather not have to get all of the tools set up from scratch again.

OK, found the drive that I had set up with the 16900-series Analysis AddIn Tool wizard that I used to build a 16900-series version of the 10391B I8085 sample IA. I'll have to install that drive back in the system and see if I can get the tools running again and try building a 6800 IA.

[gslick]

One quick note about the 0x25 (37 decimal) byte IA file description header that follows the 0x200-byte LIF header at the beginning of an IA file. The IA file description header contains a 0x20 (32 decimal) length IA file description text field. The field is padded with space characters if necessary.

Immediately after the IA file description text field there is a single byte corresponding to the IALDOWN "Invasm" Field Options:
0xFF: A = No "Invasm" Field
0x00: B = "Invasm" Field with no pop-up
0x01: C = "Invasm" Field with pop-up. 2 choices in pop-up.
0x02: D = "Invasm" Field with pop-up. 8 choices in pop-up.

Field Option A means the IA should always have enough status information to be able to (re)synchronize which states are the beginning of instruction fetch cycles. The other Field Options mean the IA may need input from the user to indicate which states should be considered as the beginning of instruction fetch cycles. See Appendix B, Microprocessors with Incomplete Status, in the 10391B reference manual for more information.

For example in the case of the i6800_i IA the preprocessor interface has logic to provide extra status information and the Field Option is A, while the i6800_p IA for the general purpose probes does not have that status information and the Field Option is B.

For the IA files in the original INVASM.ZIP:

Code: [Select]

IA File: i68000_i
IA Description: "68000 IA FOR INTERFACE       1_0"
IA Field Option: B

IA File: i68000_p
IA Description: "68000 IA FOR GP PROBES       1_0"
IA Field Option: B

IA File: i68008_i
IA Description: "68008 IA FOR INTERFACE       1_0"
IA Field Option: B

IA File: i68008_p
IA Description: "68008 IA FOR GP PROBES       1_0"
IA Field Option: B

IA File: i6800_i
IA Description: "6800/02 IA FOR INTERFACE     1_0"
IA Field Option: A

IA File: i6800_p
IA Description: "6800/02 IA FOR GP PROBES     1_0"
IA Field Option: B

IA File: i68010_i
IA Description: "68010 IA FOR INTERFACE       1_0"
IA Field Option: B

IA File: i68010_p
IA Description: "68010 IA FOR GP PROBES       1_0"
IA Field Option: B

IA File: i68020_i.p
IA Description: "68020 INVERSE ASSEMBLER      1_0"
IA Field Option: C

IA File: i6809e_p
IA Description: "6809E IA FOR GP PROBES       1_0"
IA Field Option: B

IA File: i6809_i
IA Description: "6809/9E IA FOR INTERFACE     1_0"
IA Field Option: A

IA File: i6809_p
IA Description: "6809 IA FOR GP PROBES        1_0"
IA Field Option: B

IA File: i80186e_.i
IA Description: "80186 ENHANCED IA            1_0"
IA Field Option: B

IA File: i80186_i
IA Description: "80186 IA FOR INTERFACE       1_0"
IA Field Option: B

IA File: i80188e_.i
IA Description: "80188 ENHANCED IA            1_0"
IA Field Option: B

IA File: i80188_i
IA Description: "80188 IA FOR INTERFACE       1_0"
IA Field Option: B

IA File: i80286_i
IA Description: "80286 IA FOR INTERFACE       1_0"
IA Field Option: B

IA File: i80386_8.7
IA Description: "80386 IA WITH 80X87          1_0"
IA Field Option: D

IA File: i80386_i
IA Description: "80386 IA FOR INTERFACE       1_0"
IA Field Option: D

IA File: i8085_ip
IA Description: "8085 INVERSE ASSEMBLER       1_0"
IA Field Option: A

IA File: i8086_i
IA Description: "8086 IA FOR INTERFACE        1_0"
IA Field Option: B

IA File: i8088_i
IA Description: "8088 IA FOR INTERFACE        1_0"
IA Field Option: B

IA File: insc800_.i
IA Description: "NSC800 IA FOR INTERFACE      1_0"
IA Field Option: A

IA File: iz80_i
IA Description: "Z80 IA FOR INTERFACE         1_0"
IA Field Option: A


[MarkL]

I finished up the .R extractor and ran it on all the files in invasm.zip.  Attached is invasm_v3.zip which has the results as well as the previous output from configtxt.

As before, the source is included for reference.  (You can hate my pointer manipulation if it makes you feel better.  It is a one-time hack and not a good example.)

For each inverse assembler iXXX, there is now:

  iXXX.r - The extracted relocatable .R file.  Starts with .R magic 82 03.

  iXXX.info - The additional info in the header: The description and the Invasm Field Options (as per the previous post).

I'm posting this with the caveat that it's for testing since none of it, except for i6800_p.r, has been verified.

Any feedback welcome from anyone who wants to try loading the .r files via IALDOWN, IA Format, or any other utilities.

[gslick]

I finished up the .R extractor and ran it on all the files in invasm.zip.  Attached is invasm_v3.zip which has the results as well as the previous output from configtxt.

I also started writing a file manipulation tool to help improve my own understanding of the file format and did my own version of a .R file from downloaded to analyzer format IA file extractor. I downloaded your invasm_v3.zip files and verified that all of the .R files I extracted binary compare with what you did. So that is a good checkpoint that we are in agreement there.

For the configuration text, have you looked at trying to decode the Master and Slave clock specifications, and the Normal, Demultiplex, or Mixed Clocks modes for each pod?

For 16510 modules the five J, K, L, M, and N clocks are available. Each of those 5 clocks can be specified as either Off, Negative Edge, Positive Edge, Either Edge, Qualifier Low, or Qualifier High, in any combination in a clock specification. The clocks are combined by OR'ing and AND'ing them. Clock edges are ORed to clock edges, clock qualifier levels are ORed to clock qualifier levels, and clock edges are ANDed to clock qualifier levels.

For example you could have (J↓ + K↑) • (M=1 + N=0) as a clock specification.

If all of the pods are clocked in Normal mode then only the Master clock specification applies. If any pods are clocked in either Demultiplex or Mixed Clocks modes then the Slave clock specification also applies.

As far as I know the 16510 Demultiplex and Mixed Clocks modes which split a 16 channel pod into two 8 channel halves are not implemented in the same way in any of the state modules newer than the 16510. In any newer state modules an entire pod is either Master or Slave clocked, or in Demultiplex mode a pod is both Master and Slave clocked but then the other pod in the pod pair becomes unavailable. These differences are probably why a mainframe will not load 16510 configuration files in newer state modules when there is no direct mapping between the 16510 and newer state modules in some configurations.

For example, can you extract the clock specifications and pod clock modes from the c8085_i file?

Code: [Select]

Title: 8085 CONFIG FOR INTERFACE    1_0

Pod assigments (? = disabled)
-----------------------------
Label  0: ADDR     (16 bits):  A2: ******** ******** 
Label  1: DATA     ( 8 bits):  A1: ........ ******** 
Label  2: STAT     ( 4 bits):  A1: ....**** ........

[gslick]

I made some progress in trying to understand the implementation details of an assembled IAL .R binary file.

I hacked up some proof of concept Python code that can read a .R binary file and parse it into the three binary segments, the Program, Data, and Common segments. The segment names are misleading. The Program segment is where the IAL system variables and user defined variables are located. The Common segment is where strings and output format specifications are located, and the Data segment is where instruction opcodes are located.

Using only the I8085.S sample from the 10391B kit for testing so far it appears that the data that is being populated into the three segments from parsing the assembled I8085.R binary file matches the binary data that is shown in the listing file.

The next step would be to try to hack up some proof of concept code than can unassemble the instruction opcodes in the Data segment and try to produce a functionally equivalent .S source file, which would also include declarations of the variables in the Program segment and the strings in the Common segment, and corresponding references to those variables and strings as instruction operands.

It might take a bit more time working my way through the agIalEngine.cpp code to completely understand all of the details of instruction opcode decoding than it did to get my current understanding of the .R binary file segment and relocation data details. But it does look promising now that this is doable.

[MarkL]

...
For the configuration text, have you looked at trying to decode the Master and Slave clock specifications, and the Normal, Demultiplex, or Mixed Clocks modes for each pod?
...

I looked at this with your posting and the user manual in hand.  Unfortunately, it's not immediately obvious where the clocking information lies or how it's encoded in the configuration file.

I think the only way to accomplish this is to actually have a 16510, change one clocking choice at a time, and then observe the resulting change in the saved configuration file.

If we limit the set of relevant clocking configurations to only the ones that are in invasm.zip, it would probably be a lot faster to manually transcribe them by looking at the screen, or from a screen capture.

I think familiarity with a specific processor can also quickly lead a user to the correct clocking configuration to derive the DATA, ADDR, and STAT labels.

For the 8085 specifically, one glance at the datasheet shows that it requires demultiplexing to create the separate fields for DATA and ADDR.  ALE would be the slave clock for demultiplexing.  Looking at the timing diagram and the breakout of the STAT bits show that we need to be able to clock the master on RD, WR, and the special case of INTA.

Knowing the 16510 configuration can help, say if there's complicated qualifiers and OR'd clocks, but in some cases the configuration may not be directly translatable anyway due to the differences in the way the 16510 does it, as you point out.

I guess I'm not convinced that it's going to be worth the investment in time to figure out and write a generalized clocking decoder for the 16510.  I would, however, pony up time to manually transcribe the clock settings for all of the IA configurations in invasm.zip, if you or someone were to provide the screen captures from a 16510.

Or maybe skip the transcribing step completely, and provide complete captures of the configurations and be done with it.  (Which kind-of obviates the work I already did on the config decoder, but that's ok.)

[DIPLover]

Just wanted to point out that the IA files compatible with 1650/16500 are also compatible with 1660/1670 series, maybe the top post should reflect that.

[gslick]

I'm making some progress in being able to decode an IAL style inverse assembler back into equivalent source code that could be assembled with the 10391B ASM.EXE assembler.

Below is what I currently get from processing the "6800/02 IA FOR GP PROBES     1_0" inverse assembler file  i6800_p. I still need to handle declaring variables and constants with their initial values, and declaring strings and format strings instead of putting them inline.

Interesting that it turns out that the "6800/02 IA FOR GP PROBES     1_0" inverse assembler file  i6800_p is the same as the "6800/02 IA FOR INTERFACE     1_0" inverse assembler file  i6800_i file, except that the i6800_p version does this, which selects which status decoding is used (except in the TASK = 3 case):

Code: [Select]

LABEL_0015
    GOTO LABEL_0016


while the i6800_i version does this:

Code: [Select]

LABEL_0015
    GOTO LABEL_0026


Code: [Select]

"IAL"

    IF TASK = 3 THEN GOTO LABEL_0010
    IF TASK = 4 THEN GOTO LABEL_0015
    IF TASK = 5 THEN GOTO LABEL_0015
    OUTPUT "Illegal Task Request"
    ABORT
    OUTPUT "Data Error"
    ABORT

LABEL_000D
    POSITION ABS,1
    OUTPUT "Illegal Opcode"
    ABORT

LABEL_0010
    LOAD ID_CODE
    IF 7,0 = VAR_0048 THEN GOTO LABEL_0016
    GOTO LABEL_0026

LABEL_0015
    GOTO LABEL_0016

LABEL_0016
    LOAD INPUT_TAG
    IF 17,16 = 0 THEN GOTO LABEL_0043
    LOAD INPUT_STATUS
    IF 2,2 = 1 THEN GOTO LABEL_0043
    LOAD INPUT_TAG
    CASE_OF 1,0
        GOTO LABEL_01A2
        GOTO LABEL_0043
        GOTO LABEL_0054
        NOP
    CASE_END
    RETURN

LABEL_0026
    LOAD INPUT_STATUS
    IF 3,0 = 9 THEN GOTO LABEL_005B
    LOAD INPUT_DATA
    POSITION ABS,3
    OUTPUT ACCUMULATOR,FORMAT=8,HEX,2
    POSITION REL,1
    LOAD INPUT_STATUS
    CASE_OF 3,0
        OUTPUT "Illegal Opcode"
        OUTPUT "operand fetch"
        OUTPUT "stack read"
        OUTPUT "stack write"
        OUTPUT "stack read"
        OUTPUT "stack write"
        OUTPUT "halt"
        OUTPUT "vector"
        OUTPUT "unused"
        OUTPUT "opcode fetch"
        OUTPUT "DMA read"
        OUTPUT "DMA write"
        OUTPUT "memory write"
        OUTPUT "memory read"
        OUTPUT "out of synch"
        OUTPUT "interrupt ack"
    CASE_END
    SET RETURN_FLAGS,0
    RETURN

LABEL_0043
    LOAD INPUT_DATA
    POSITION ABS,3
    OUTPUT ACCUMULATOR,FORMAT=8,HEX,2
    POSITION REL,1
    LOAD INPUT_STATUS
    CASE_OF 2,0
        OUTPUT "non valid cycle"
        OUTPUT "non valid cycle"
        OUTPUT "memory write"
        OUTPUT "memory read"
        OUTPUT "dma or halt"
        OUTPUT "dma or halt"
        OUTPUT "dma or halt"
        OUTPUT "dma or halt"
    CASE_END
    SET RETURN_FLAGS,0
    RETURN

LABEL_0054
    LOAD INPUT_DATA
    POSITION ABS,3
    OUTPUT ACCUMULATOR,FORMAT=8,HEX,2
    POSITION REL,1
    OUTPUT "unused cycle"
    SET RETURN_FLAGS,0
    RETURN

LABEL_005B
    SET RETURN_FLAGS,1
    INPUT REL,0
    LOAD INITIAL_DATA
    CASE_OF 7,7
        GOTO LABEL_0062
        GOTO LABEL_0103
    CASE_END

LABEL_0062
    CASE_OF 7,4
        GOTO LABEL_006C
        GOTO LABEL_008C
        GOTO LABEL_009F
        GOTO LABEL_00C4
        GOTO LABEL_00E2
        GOTO LABEL_00E2
        GOTO LABEL_00E2
        GOTO LABEL_00E2
    CASE_END

LABEL_006C
    CASE_OF 3,0
        GOTO LABEL_000D
        OUTPUT "NOP"
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        OUTPUT "TAP"
        OUTPUT "TPA"
        OUTPUT "INX"
        OUTPUT "DEX"
        GOTO LABEL_007F
        GOTO LABEL_0081
        GOTO LABEL_007F
        GOTO LABEL_0081
        GOTO LABEL_007F
        GOTO LABEL_0081
    CASE_END
    RETURN

LABEL_007F
    OUTPUT "CL"
    GOTO LABEL_0082

LABEL_0081
    OUTPUT "SE"

LABEL_0082
    IF 2,1 = 1 THEN OUTPUT "V"
    IF 2,1 = 2 THEN OUTPUT "C"
    IF 2,1 = 3 THEN OUTPUT "I"
    RETURN

LABEL_008C
    CASE_OF 3,0
        OUTPUT "SBA"
        OUTPUT "CBA"
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        OUTPUT "TAB"
        OUTPUT "TBA"
        GOTO LABEL_000D
        OUTPUT "DAA"
        GOTO LABEL_000D
        OUTPUT "ABA"
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
    CASE_END
    RETURN

LABEL_009F
    OUTPUT "B"
    CASE_OF 3,0
        OUTPUT "RA"
        GOTO LABEL_000D
        OUTPUT "HI"
        OUTPUT "LS"
        OUTPUT "CC"
        OUTPUT "CS"
        OUTPUT "NE"
        OUTPUT "EQ"
        OUTPUT "VC"
        OUTPUT "VS"
        OUTPUT "PL"
        OUTPUT "MI"
        OUTPUT "GE"
        OUTPUT "LT"
        OUTPUT "GT"
        OUTPUT "LE"
    CASE_END

LABEL_00B2
    INCREMENT INPUT_ADDRESS
    LOAD INPUT_ADDRESS
    ADD 1
    STORE VAR_003E
    INPUT ABS,INPUT_ADDRESS
    IF INPUT_ERROR <> 0 THEN GOTO LABEL_017C
    LOAD INPUT_DATA
    POSITION ABS,6
    IF 7,7 = 1 THEN INCLUSIVE_OR VAR_0046
    ADD VAR_003E
    AND VAR_0042
    IF_NOT_MAPPED THEN OUTPUT ACCUMULATOR,FORMAT=16,HEX,4
    RETURN

LABEL_00C4
    CASE_OF 3,0
        OUTPUT "TSX"
        OUTPUT "INS"
        GOTO LABEL_00D7
        GOTO LABEL_00D7
        OUTPUT "DES"
        OUTPUT "TXS"
        GOTO LABEL_00D7
        GOTO LABEL_00D7
        GOTO LABEL_000D
        OUTPUT "RTS"
        GOTO LABEL_000D
        OUTPUT "RTI"
        GOTO LABEL_000D
        GOTO LABEL_000D
        OUTPUT "WAI"
        OUTPUT "SWI"
    CASE_END
    RETURN

LABEL_00D7
    IF 2,2 = 0 THEN OUTPUT "PUL"
    IF 2,2 = 1 THEN OUTPUT "PSH"
    CASE_OF 0,0
        GOTO LABEL_00FF
        GOTO LABEL_0101
    CASE_END
    RETURN

LABEL_00E2
    CASE_OF 3,0
        OUTPUT "NEG"
        GOTO LABEL_000D
        GOTO LABEL_000D
        OUTPUT "COM"
        OUTPUT "LSR"
        GOTO LABEL_000D
        OUTPUT "ROR"
        OUTPUT "ASR"
        OUTPUT "ASL"
        OUTPUT "ROL"
        OUTPUT "DEC"
        GOTO LABEL_000D
        OUTPUT "INC"
        OUTPUT "TST"
        GOTO LABEL_00F5
        OUTPUT "CLR"
    CASE_END
    GOTO LABEL_00F9

LABEL_00F5
    CASE_OF 5,5
        GOTO LABEL_000D
        OUTPUT "JMP"
    CASE_END

LABEL_00F9
    CASE_OF 5,4
        GOTO LABEL_00FF
        GOTO LABEL_0101
        GOTO LABEL_016B
        GOTO LABEL_0170
    CASE_END

LABEL_00FF
    OUTPUT "A"
    RETURN

LABEL_0101
    OUTPUT "B"
    RETURN

LABEL_0103
    CASE_OF 3,0
        OUTPUT "SUB"
        OUTPUT "CMP"
        OUTPUT "SBC"
        GOTO LABEL_000D
        OUTPUT "AND"
        OUTPUT "BIT"
        OUTPUT "LDA"
        GOTO LABEL_0116
        OUTPUT "EOR"
        OUTPUT "ADC"
        OUTPUT "ORA"
        OUTPUT "ADD"
        GOTO LABEL_011E
        GOTO LABEL_0126
        GOTO LABEL_0138
        GOTO LABEL_0141
    CASE_END
    GOTO LABEL_0150

LABEL_0116
    IF 7,4 = 8 THEN GOTO LABEL_000D
    IF 7,4 = 12 THEN GOTO LABEL_000D
    OUTPUT "STA"
    GOTO LABEL_0150

LABEL_011E
    IF 7,4 >= 12 THEN GOTO LABEL_000D
    OUTPUT "CPX"
    IF 5,4 = 0 THEN GOTO LABEL_0161
    GOTO LABEL_0156

LABEL_0126
    IF 7,4 = 9 THEN GOTO LABEL_000D
    IF 7,4 >= 12 THEN GOTO LABEL_000D
    IF 5,4 = 0 THEN GOTO LABEL_0136
    OUTPUT "JSR"
    IF 5,4 = 2 THEN GOTO LABEL_016B
    IF 5,4 = 3 THEN GOTO LABEL_0170

LABEL_0136
    OUTPUT "BSR"
    GOTO LABEL_00B2

LABEL_0138
    OUTPUT "LD"
    CASE_OF 6,6
        OUTPUT "S"
        OUTPUT "X"
    CASE_END
    IF 5,4 = 0 THEN GOTO LABEL_0161
    GOTO LABEL_0156

LABEL_0141
    IF 7,4 = 8 THEN GOTO LABEL_000D
    IF 7,4 = 12 THEN GOTO LABEL_000D
    OUTPUT "ST"
    CASE_OF 6,6
        OUTPUT "S"
        OUTPUT "X"
    CASE_END
    IF 5,4 = 0 THEN GOTO LABEL_0161
    GOTO LABEL_0156

LABEL_0150
    IF 6,6 = 0 THEN CALL LABEL_00FF
    IF 6,6 = 1 THEN CALL LABEL_0101

LABEL_0156
    CASE_OF 5,4
        GOTO LABEL_015C
        GOTO LABEL_0166
        GOTO LABEL_016B
        GOTO LABEL_0170
    CASE_END

LABEL_015C
    POSITION ABS,6
    OUTPUT "#"
    CALL LABEL_0175
    OUTPUT ACCUMULATOR,FORMAT=8,HEX,2
    RETURN

LABEL_0161
    POSITION ABS,6
    OUTPUT "#"
    CALL LABEL_017E
    OUTPUT ACCUMULATOR,FORMAT=16,HEX,4
    RETURN

LABEL_0166
    POSITION ABS,6
    CALL LABEL_0175
    IF_NOT_MAPPED THEN OUTPUT ACCUMULATOR,FORMAT=16,HEX,4
    RETURN

LABEL_016B
    POSITION ABS,6
    CALL LABEL_0175
    OUTPUT ACCUMULATOR,FORMAT=8,HEX,2
    OUTPUT ",X"
    RETURN

LABEL_0170
    POSITION ABS,6
    CALL LABEL_017E
    IF_NOT_MAPPED THEN OUTPUT ACCUMULATOR,FORMAT=16,HEX,4
    RETURN

LABEL_0175
    INCREMENT INPUT_ADDRESS
    INPUT ABS,INPUT_ADDRESS
    IF INPUT_ERROR <> 0 THEN GOTO LABEL_017C
    LOAD INPUT_DATA
    RETURN

LABEL_017C
    OUTPUT "**"
    ABORT

LABEL_017E
    INCREMENT INPUT_ADDRESS
    LOAD INPUT_ADDRESS
    STORE VAR_003C
    INPUT ABS,INPUT_ADDRESS
    IF INPUT_ERROR <> 0 THEN GOTO LABEL_0192
    LOAD INPUT_DATA
    ROTATE LEFT,8
    AND VAR_0044
    STORE VAR_0034
    INCREMENT INPUT_ADDRESS
    INPUT ABS,INPUT_ADDRESS
    IF INPUT_ERROR <> 0 THEN GOTO LABEL_019D
    LOAD INPUT_DATA
    AND VAR_004A
    INCLUSIVE_OR VAR_0034
    RETURN

LABEL_0192
    OUTPUT "**"
    LOAD VAR_003C
    STORE INPUT_ADDRESS
    INCREMENT INPUT_ADDRESS
    INPUT ABS,INPUT_ADDRESS
    IF INPUT_ERROR <> 0 THEN GOTO LABEL_01A0
    LOAD INPUT_DATA
    OUTPUT ACCUMULATOR,FORMAT=8,HEX,2
    ABORT

LABEL_019D
    LOAD VAR_0034
    ROTATE RIGHT,8
    OUTPUT ACCUMULATOR,FORMAT=8,HEX,2

LABEL_01A0
    OUTPUT "**"
    ABORT

LABEL_01A2
    SET VAR_0040,0

LABEL_01A3
    LOAD INPUT_STATUS
    IF 1,0 = 3 THEN GOTO LABEL_01AE
    TAG_WITH 2
    INCREMENT VAR_0040
    INPUT REL,VAR_0040
    IF INPUT_ERROR <> 0 THEN GOTO LABEL_005B
    GOTO LABEL_01A3

LABEL_01AE
    LOAD INPUT_DATA
    CASE_OF 7,0
        GOTO LABEL_000D
        LOAD 56
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD 56
        LOAD 56
        LOAD VAR_004C
        LOAD VAR_004E
        LOAD 56
        LOAD 56
        LOAD 56
        LOAD 56
        LOAD 56
        LOAD 56
        LOAD 56
        LOAD 56
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD 56
        LOAD 56
        GOTO LABEL_000D
        LOAD 56
        GOTO LABEL_000D
        LOAD 56
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD VAR_0050
        GOTO LABEL_000D
        LOAD VAR_0052
        LOAD VAR_0054
        LOAD VAR_0056
        LOAD VAR_0058
        LOAD VAR_005A
        LOAD VAR_005C
        LOAD VAR_005E
        LOAD VAR_0060
        LOAD VAR_0062
        LOAD VAR_0064
        LOAD VAR_0066
        LOAD VAR_0068
        LOAD VAR_006A
        LOAD VAR_006C
        LOAD VAR_006E
        LOAD VAR_0070
        LOAD VAR_0072
        LOAD VAR_0074
        LOAD VAR_0076
        LOAD VAR_0078
        LOAD VAR_007A
        LOAD VAR_007C
        GOTO LABEL_000D
        LOAD VAR_007E
        GOTO LABEL_000D
        LOAD VAR_0080
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD VAR_0082
        LOAD VAR_0084
        LOAD 56
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD 56
        LOAD 56
        GOTO LABEL_000D
        LOAD 56
        LOAD 56
        LOAD 56
        LOAD 56
        LOAD 56
        GOTO LABEL_000D
        LOAD 56
        LOAD 56
        GOTO LABEL_000D
        LOAD 56
        LOAD 56
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD 56
        LOAD 56
        GOTO LABEL_000D
        LOAD 56
        LOAD 56
        LOAD 56
        LOAD 56
        LOAD 56
        GOTO LABEL_000D
        LOAD 56
        LOAD 56
        GOTO LABEL_000D
        LOAD 56
        LOAD VAR_0086
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD VAR_0088
        LOAD VAR_008A
        GOTO LABEL_000D
        LOAD VAR_008C
        LOAD VAR_008E
        LOAD VAR_0090
        LOAD VAR_0092
        LOAD VAR_0094
        GOTO LABEL_000D
        LOAD VAR_0096
        LOAD VAR_0098
        LOAD VAR_009A
        LOAD VAR_009C
        LOAD VAR_009E
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD VAR_00A0
        LOAD VAR_00A2
        GOTO LABEL_000D
        LOAD VAR_00A4
        LOAD VAR_00A6
        LOAD VAR_00A8
        LOAD VAR_00AA
        LOAD VAR_00AC
        GOTO LABEL_000D
        LOAD VAR_00AE
        LOAD VAR_00B0
        LOAD VAR_00B2
        LOAD VAR_00B4
        LOAD 52
        LOAD 52
        LOAD 52
        GOTO LABEL_000D
        LOAD 52
        LOAD 52
        LOAD 52
        GOTO LABEL_000D
        LOAD 52
        LOAD 52
        LOAD 52
        LOAD 52
        LOAD VAR_00B6
        LOAD VAR_00B8
        LOAD VAR_00BA
        GOTO LABEL_000D
        LOAD VAR_00BC
        LOAD VAR_00BE
        LOAD VAR_00C0
        GOTO LABEL_000D
        LOAD VAR_00C2
        LOAD VAR_00C4
        LOAD VAR_00C6
        LOAD VAR_00C8
        LOAD VAR_00CA
        LOAD VAR_00CC
        LOAD VAR_00CE
        LOAD VAR_00D0
        LOAD VAR_00D2
        GOTO LABEL_000D
        LOAD VAR_00D4
        LOAD VAR_00D6
        LOAD VAR_00D8
        LOAD VAR_00DA
        LOAD VAR_00DC
        GOTO LABEL_000D
        LOAD VAR_00DE
        LOAD VAR_00E0
        LOAD VAR_00E2
        LOAD VAR_00E4
        LOAD VAR_00E6
        LOAD VAR_00E8
        LOAD VAR_00EA
        LOAD VAR_00EC
        LOAD VAR_00EE
        LOAD VAR_00F0
        LOAD VAR_00F2
        LOAD VAR_00F4
        LOAD VAR_00F6
        LOAD VAR_00F8
        LOAD VAR_00FA
        GOTO LABEL_000D
        LOAD VAR_00FC
        LOAD VAR_00FE
        LOAD VAR_0100
        LOAD VAR_0102
        LOAD VAR_0104
        LOAD VAR_0106
        LOAD VAR_0108
        LOAD VAR_010A
        LOAD VAR_010C
        LOAD VAR_010E
        LOAD VAR_0110
        LOAD VAR_0112
        LOAD 52
        LOAD 52
        LOAD 52
        GOTO LABEL_000D
        LOAD 52
        LOAD 52
        LOAD 52
        GOTO LABEL_000D
        LOAD 52
        LOAD 52
        LOAD 52
        LOAD 52
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD VAR_0114
        GOTO LABEL_000D
        LOAD VAR_0116
        LOAD VAR_0118
        LOAD VAR_011A
        GOTO LABEL_000D
        LOAD VAR_011C
        LOAD VAR_011E
        LOAD VAR_0120
        LOAD VAR_0122
        LOAD VAR_0124
        LOAD VAR_0126
        LOAD VAR_0128
        LOAD VAR_012A
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD VAR_012C
        LOAD VAR_012E
        LOAD VAR_0130
        LOAD VAR_0132
        LOAD VAR_0134
        GOTO LABEL_000D
        LOAD VAR_0136
        LOAD VAR_0138
        LOAD VAR_013A
        LOAD VAR_013C
        LOAD VAR_013E
        LOAD VAR_0140
        LOAD VAR_0142
        LOAD VAR_0144
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD VAR_0146
        LOAD VAR_0148
        LOAD VAR_014A
        LOAD VAR_014C
        LOAD VAR_014E
        GOTO LABEL_000D
        LOAD VAR_0150
        LOAD VAR_0152
        LOAD VAR_0154
        LOAD VAR_0156
        LOAD VAR_0158
        LOAD VAR_015A
        LOAD VAR_015C
        LOAD VAR_015E
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD VAR_0160
        LOAD VAR_0162
    CASE_END

LABEL_02B1
    STORE VAR_0036
    AND 3
    STORE VAR_003A
    IF 1,0 = 3 THEN GOTO LABEL_005B
    TAG_WITH VAR_003A

LABEL_02B8
    INCREMENT VAR_0040
    INPUT REL,VAR_0040
    IF INPUT_ERROR <> 0 THEN GOTO LABEL_005B
    LOAD INPUT_STATUS
    IF 2,2 = 1 THEN GOTO LABEL_02B8
    LOAD VAR_0036
    ROTATE RIGHT,2
    GOTO LABEL_02B1


[MarkL]

That's some great progress, gslick!

Interesting that TASK==3 (for the HP 64620) could dynamically select which STAT decoding to use.  It seems like that functionality would be easy to carry forward to newer models instead of having to load separate IAs.  It's not like they were saving any IA interpreter code space.

[gslick]

Below is what I now get from processing the "6800/02 IA FOR GP PROBES     1_0" inverse assembler file i6800_p after adding some logic to handle declaring variables and constants with their initial values, and declaring strings and format strings instead of putting them inline.

If you assemble this with the 10391B ASM.EXE assembler it should produce an i6800_p.r relocatable file that binary compares with the one extracted from the INVASM.ZIP collection, with the exception of the Name Record at the beginning of the file which includes the complete source file name and path. If the file name path length differs the whole remainder of the .R file will shift. There is also some other descriptive information in the Name Record which might get populated differently between the 10391B ASM.EXE assembler and HP tools that might have been used on different hosts.

The .R decoding code I wrote to do this is rather ugly. I just wanted to try to figure out exactly what it needed to do. I should make sure it works correctly on the other IA .R files, and then try to clean up the code.

Code: [Select]

"IAL"

*
* Original Source File Name: d:\ial\procs\i6800_p.s
*

        LABEL_TITLE      " 6800/6802 Mnemonic"
        BASE_TITLE       "        hex"
        SEARCH_LIMIT     12
        DEFAULT_WIDTH    21
        MAPPED_WIDTH     21
VAR_0034        VARIABLE 000000000H
VAR_0036        VARIABLE 000000000H
VAR_0038        VARIABLE 000000000H    * unreferenced
VAR_003A        VARIABLE 000000000H
VAR_003C        VARIABLE 000000000H
VAR_003E        VARIABLE 000000000H
VAR_0040        VARIABLE 000000000H
FMT_0010        FORMAT 16,HEX,4
FMT_0012        FORMAT 8,HEX,2
STR_0014        ASCII "A"
STR_0015        ASCII "B"
STR_0016        ASCII "C"
STR_0017        ASCII "H"    * unreferenced
STR_0018        ASCII "I"
STR_0019        ASCII "S"
STR_001A        ASCII "V"
STR_001B        ASCII "X"
STR_001C        ASCII "PUL"
STR_001E        ASCII "PSH"
STR_0020        ASCII ","    * unreferenced
STR_0021        ASCII "-"    * unreferenced
STR_0022        ASCII ",X"
STR_0024        ASCII "operand fetch"
STR_002B        ASCII "stack read"
STR_0031        ASCII "stack write"
STR_0037        ASCII "halt"
STR_003A        ASCII "vector"
STR_003E        ASCII "unused"
STR_0042        ASCII "opcode fetch"
STR_0049        ASCII "DMA read"
STR_004E        ASCII "DMA write"
STR_0053        ASCII "memory read"
STR_0059        ASCII "memory write"
STR_0060        ASCII "out of synch"
STR_0067        ASCII "interrupt ack"
STR_006E        ASCII "Illegal Opcode"
STR_0076        ASCII "unused cycle"
STR_007D        ASCII "dma or halt"
STR_0083        ASCII "non valid cycle"
CONST_0042      CONSTANT 00000FFFFH
CONST_0044      CONSTANT 00000FF00H
CONST_0046      CONSTANT 0FFFFFF00H

ENTRY_POINT
    IF TASK = 3 THEN GOTO LABEL_0010
    IF TASK = 4 THEN GOTO LABEL_0015
    IF TASK = 5 THEN GOTO LABEL_0015
    OUTPUT "Illegal Task Request"
    ABORT
    OUTPUT "Data Error"
    ABORT

LABEL_000D
    POSITION ABS,1
    OUTPUT STR_006E    * "Illegal Opcode"
    ABORT

LABEL_0010
    LOAD ID_CODE
    IF 7,0 = 0000000F0H THEN GOTO LABEL_0016
    GOTO LABEL_0026

LABEL_0015
    GOTO LABEL_0016

LABEL_0016
    LOAD INPUT_TAG
    IF 17,16 = 0 THEN GOTO LABEL_0043
    LOAD INPUT_STATUS
    IF 2,2 = 1 THEN GOTO LABEL_0043
    LOAD INPUT_TAG
    CASE_OF 1,0
        GOTO LABEL_01A2
        GOTO LABEL_0043
        GOTO LABEL_0054
        NOP
    CASE_END
    RETURN

LABEL_0026
    LOAD INPUT_STATUS
    IF 3,0 = 9 THEN GOTO LABEL_005B
    LOAD INPUT_DATA
    POSITION ABS,3
    OUTPUT ACCUMULATOR,FMT_0012
    POSITION REL,1
    LOAD INPUT_STATUS
    CASE_OF 3,0
        OUTPUT STR_006E    * "Illegal Opcode"
        OUTPUT STR_0024    * "operand fetch"
        OUTPUT STR_002B    * "stack read"
        OUTPUT STR_0031    * "stack write"
        OUTPUT STR_002B    * "stack read"
        OUTPUT STR_0031    * "stack write"
        OUTPUT STR_0037    * "halt"
        OUTPUT STR_003A    * "vector"
        OUTPUT STR_003E    * "unused"
        OUTPUT STR_0042    * "opcode fetch"
        OUTPUT STR_0049    * "DMA read"
        OUTPUT STR_004E    * "DMA write"
        OUTPUT STR_0059    * "memory write"
        OUTPUT STR_0053    * "memory read"
        OUTPUT STR_0060    * "out of synch"
        OUTPUT STR_0067    * "interrupt ack"
    CASE_END
    SET RETURN_FLAGS,0
    RETURN

LABEL_0043
    LOAD INPUT_DATA
    POSITION ABS,3
    OUTPUT ACCUMULATOR,FMT_0012
    POSITION REL,1
    LOAD INPUT_STATUS
    CASE_OF 2,0
        OUTPUT STR_0083    * "non valid cycle"
        OUTPUT STR_0083    * "non valid cycle"
        OUTPUT STR_0059    * "memory write"
        OUTPUT STR_0053    * "memory read"
        OUTPUT STR_007D    * "dma or halt"
        OUTPUT STR_007D    * "dma or halt"
        OUTPUT STR_007D    * "dma or halt"
        OUTPUT STR_007D    * "dma or halt"
    CASE_END
    SET RETURN_FLAGS,0
    RETURN

LABEL_0054
    LOAD INPUT_DATA
    POSITION ABS,3
    OUTPUT ACCUMULATOR,FMT_0012
    POSITION REL,1
    OUTPUT STR_0076    * "unused cycle"
    SET RETURN_FLAGS,0
    RETURN

LABEL_005B
    SET RETURN_FLAGS,1
    INPUT REL,0
    LOAD INITIAL_DATA
    CASE_OF 7,7
        GOTO LABEL_0062
        GOTO LABEL_0103
    CASE_END

LABEL_0062
    CASE_OF 7,4
        GOTO LABEL_006C
        GOTO LABEL_008C
        GOTO LABEL_009F
        GOTO LABEL_00C4
        GOTO LABEL_00E2
        GOTO LABEL_00E2
        GOTO LABEL_00E2
        GOTO LABEL_00E2
    CASE_END

LABEL_006C
    CASE_OF 3,0
        GOTO LABEL_000D
        OUTPUT "NOP"
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        OUTPUT "TAP"
        OUTPUT "TPA"
        OUTPUT "INX"
        OUTPUT "DEX"
        GOTO LABEL_007F
        GOTO LABEL_0081
        GOTO LABEL_007F
        GOTO LABEL_0081
        GOTO LABEL_007F
        GOTO LABEL_0081
    CASE_END
    RETURN

LABEL_007F
    OUTPUT "CL"
    GOTO LABEL_0082

LABEL_0081
    OUTPUT "SE"

LABEL_0082
    IF 2,1 = 1 THEN OUTPUT STR_001A    * "V"
    IF 2,1 = 2 THEN OUTPUT STR_0016    * "C"
    IF 2,1 = 3 THEN OUTPUT STR_0018    * "I"
    RETURN

LABEL_008C
    CASE_OF 3,0
        OUTPUT "SBA"
        OUTPUT "CBA"
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        OUTPUT "TAB"
        OUTPUT "TBA"
        GOTO LABEL_000D
        OUTPUT "DAA"
        GOTO LABEL_000D
        OUTPUT "ABA"
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
    CASE_END
    RETURN

LABEL_009F
    OUTPUT STR_0015    * "B"
    CASE_OF 3,0
        OUTPUT "RA"
        GOTO LABEL_000D
        OUTPUT "HI"
        OUTPUT "LS"
        OUTPUT "CC"
        OUTPUT "CS"
        OUTPUT "NE"
        OUTPUT "EQ"
        OUTPUT "VC"
        OUTPUT "VS"
        OUTPUT "PL"
        OUTPUT "MI"
        OUTPUT "GE"
        OUTPUT "LT"
        OUTPUT "GT"
        OUTPUT "LE"
    CASE_END

LABEL_00B2
    INCREMENT INPUT_ADDRESS
    LOAD INPUT_ADDRESS
    ADD 1
    STORE VAR_003E
    INPUT ABS,INPUT_ADDRESS
    IF INPUT_ERROR <> 0 THEN GOTO LABEL_017C
    LOAD INPUT_DATA
    POSITION ABS,6
    IF 7,7 = 1 THEN INCLUSIVE_OR CONST_0046
    ADD VAR_003E
    AND CONST_0042
    IF_NOT_MAPPED THEN OUTPUT ACCUMULATOR,FMT_0010
    RETURN

LABEL_00C4
    CASE_OF 3,0
        OUTPUT "TSX"
        OUTPUT "INS"
        GOTO LABEL_00D7
        GOTO LABEL_00D7
        OUTPUT "DES"
        OUTPUT "TXS"
        GOTO LABEL_00D7
        GOTO LABEL_00D7
        GOTO LABEL_000D
        OUTPUT "RTS"
        GOTO LABEL_000D
        OUTPUT "RTI"
        GOTO LABEL_000D
        GOTO LABEL_000D
        OUTPUT "WAI"
        OUTPUT "SWI"
    CASE_END
    RETURN

LABEL_00D7
    IF 2,2 = 0 THEN OUTPUT STR_001C    * "PUL"
    IF 2,2 = 1 THEN OUTPUT STR_001E    * "PSH"
    CASE_OF 0,0
        GOTO LABEL_00FF
        GOTO LABEL_0101
    CASE_END
    RETURN

LABEL_00E2
    CASE_OF 3,0
        OUTPUT "NEG"
        GOTO LABEL_000D
        GOTO LABEL_000D
        OUTPUT "COM"
        OUTPUT "LSR"
        GOTO LABEL_000D
        OUTPUT "ROR"
        OUTPUT "ASR"
        OUTPUT "ASL"
        OUTPUT "ROL"
        OUTPUT "DEC"
        GOTO LABEL_000D
        OUTPUT "INC"
        OUTPUT "TST"
        GOTO LABEL_00F5
        OUTPUT "CLR"
    CASE_END
    GOTO LABEL_00F9

LABEL_00F5
    CASE_OF 5,5
        GOTO LABEL_000D
        OUTPUT "JMP"
    CASE_END

LABEL_00F9
    CASE_OF 5,4
        GOTO LABEL_00FF
        GOTO LABEL_0101
        GOTO LABEL_016B
        GOTO LABEL_0170
    CASE_END

LABEL_00FF
    OUTPUT STR_0014    * "A"
    RETURN

LABEL_0101
    OUTPUT STR_0015    * "B"
    RETURN

LABEL_0103
    CASE_OF 3,0
        OUTPUT "SUB"
        OUTPUT "CMP"
        OUTPUT "SBC"
        GOTO LABEL_000D
        OUTPUT "AND"
        OUTPUT "BIT"
        OUTPUT "LDA"
        GOTO LABEL_0116
        OUTPUT "EOR"
        OUTPUT "ADC"
        OUTPUT "ORA"
        OUTPUT "ADD"
        GOTO LABEL_011E
        GOTO LABEL_0126
        GOTO LABEL_0138
        GOTO LABEL_0141
    CASE_END
    GOTO LABEL_0150

LABEL_0116
    IF 7,4 = 8 THEN GOTO LABEL_000D
    IF 7,4 = 12 THEN GOTO LABEL_000D
    OUTPUT "STA"
    GOTO LABEL_0150

LABEL_011E
    IF 7,4 >= 12 THEN GOTO LABEL_000D
    OUTPUT "CPX"
    IF 5,4 = 0 THEN GOTO LABEL_0161
    GOTO LABEL_0156

LABEL_0126
    IF 7,4 = 9 THEN GOTO LABEL_000D
    IF 7,4 >= 12 THEN GOTO LABEL_000D
    IF 5,4 = 0 THEN GOTO LABEL_0136
    OUTPUT "JSR"
    IF 5,4 = 2 THEN GOTO LABEL_016B
    IF 5,4 = 3 THEN GOTO LABEL_0170

LABEL_0136
    OUTPUT "BSR"
    GOTO LABEL_00B2

LABEL_0138
    OUTPUT "LD"
    CASE_OF 6,6
        OUTPUT STR_0019    * "S"
        OUTPUT STR_001B    * "X"
    CASE_END
    IF 5,4 = 0 THEN GOTO LABEL_0161
    GOTO LABEL_0156

LABEL_0141
    IF 7,4 = 8 THEN GOTO LABEL_000D
    IF 7,4 = 12 THEN GOTO LABEL_000D
    OUTPUT "ST"
    CASE_OF 6,6
        OUTPUT STR_0019    * "S"
        OUTPUT STR_001B    * "X"
    CASE_END
    IF 5,4 = 0 THEN GOTO LABEL_0161
    GOTO LABEL_0156

LABEL_0150
    IF 6,6 = 0 THEN CALL LABEL_00FF
    IF 6,6 = 1 THEN CALL LABEL_0101

LABEL_0156
    CASE_OF 5,4
        GOTO LABEL_015C
        GOTO LABEL_0166
        GOTO LABEL_016B
        GOTO LABEL_0170
    CASE_END

LABEL_015C
    POSITION ABS,6
    OUTPUT "#"
    CALL LABEL_0175
    OUTPUT ACCUMULATOR,FMT_0012
    RETURN

LABEL_0161
    POSITION ABS,6
    OUTPUT "#"
    CALL LABEL_017E
    OUTPUT ACCUMULATOR,FMT_0010
    RETURN

LABEL_0166
    POSITION ABS,6
    CALL LABEL_0175
    IF_NOT_MAPPED THEN OUTPUT ACCUMULATOR,FMT_0010
    RETURN

LABEL_016B
    POSITION ABS,6
    CALL LABEL_0175
    OUTPUT ACCUMULATOR,FMT_0012
    OUTPUT STR_0022    * ",X"
    RETURN

LABEL_0170
    POSITION ABS,6
    CALL LABEL_017E
    IF_NOT_MAPPED THEN OUTPUT ACCUMULATOR,FMT_0010
    RETURN

LABEL_0175
    INCREMENT INPUT_ADDRESS
    INPUT ABS,INPUT_ADDRESS
    IF INPUT_ERROR <> 0 THEN GOTO LABEL_017C
    LOAD INPUT_DATA
    RETURN

LABEL_017C
    OUTPUT "**"
    ABORT

LABEL_017E
    INCREMENT INPUT_ADDRESS
    LOAD INPUT_ADDRESS
    STORE VAR_003C
    INPUT ABS,INPUT_ADDRESS
    IF INPUT_ERROR <> 0 THEN GOTO LABEL_0192
    LOAD INPUT_DATA
    ROTATE LEFT,8
    AND CONST_0044
    STORE VAR_0034
    INCREMENT INPUT_ADDRESS
    INPUT ABS,INPUT_ADDRESS
    IF INPUT_ERROR <> 0 THEN GOTO LABEL_019D
    LOAD INPUT_DATA
    AND 0000000FFH
    INCLUSIVE_OR VAR_0034
    RETURN

LABEL_0192
    OUTPUT "**"
    LOAD VAR_003C
    STORE INPUT_ADDRESS
    INCREMENT INPUT_ADDRESS
    INPUT ABS,INPUT_ADDRESS
    IF INPUT_ERROR <> 0 THEN GOTO LABEL_01A0
    LOAD INPUT_DATA
    OUTPUT ACCUMULATOR,FMT_0012
    ABORT

LABEL_019D
    LOAD VAR_0034
    ROTATE RIGHT,8
    OUTPUT ACCUMULATOR,FMT_0012

LABEL_01A0
    OUTPUT "**"
    ABORT

LABEL_01A2
    SET VAR_0040,0

LABEL_01A3
    LOAD INPUT_STATUS
    IF 1,0 = 3 THEN GOTO LABEL_01AE
    TAG_WITH 2
    INCREMENT VAR_0040
    INPUT REL,VAR_0040
    IF INPUT_ERROR <> 0 THEN GOTO LABEL_005B
    GOTO LABEL_01A3

LABEL_01AE
    LOAD INPUT_DATA
    CASE_OF 7,0
        GOTO LABEL_000D
        LOAD 56
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD 56
        LOAD 56
        LOAD 0000003A8H
        LOAD 0000003A8H
        LOAD 56
        LOAD 56
        LOAD 56
        LOAD 56
        LOAD 56
        LOAD 56
        LOAD 56
        LOAD 56
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD 56
        LOAD 56
        GOTO LABEL_000D
        LOAD 56
        GOTO LABEL_000D
        LOAD 56
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD 0000003A4H
        GOTO LABEL_000D
        LOAD 0000003A4H
        LOAD 0000003A4H
        LOAD 0000003A4H
        LOAD 0000003A4H
        LOAD 0000003A4H
        LOAD 0000003A4H
        LOAD 0000003A4H
        LOAD 0000003A4H
        LOAD 0000003A4H
        LOAD 0000003A4H
        LOAD 0000003A4H
        LOAD 0000003A4H
        LOAD 0000003A4H
        LOAD 0000003A4H
        LOAD 0000003A8H
        LOAD 0000003A8H
        LOAD 000000368H
        LOAD 000000368H
        LOAD 0000003A8H
        LOAD 0000003A8H
        LOAD 000000398H
        LOAD 000000398H
        GOTO LABEL_000D
        LOAD 000000D68H
        GOTO LABEL_000D
        LOAD 000355568H
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD 00D695558H
        LOAD 003595558H
        LOAD 56
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD 56
        LOAD 56
        GOTO LABEL_000D
        LOAD 56
        LOAD 56
        LOAD 56
        LOAD 56
        LOAD 56
        GOTO LABEL_000D
        LOAD 56
        LOAD 56
        GOTO LABEL_000D
        LOAD 56
        LOAD 56
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD 56
        LOAD 56
        GOTO LABEL_000D
        LOAD 56
        LOAD 56
        LOAD 56
        LOAD 56
        LOAD 56
        GOTO LABEL_000D
        LOAD 56
        LOAD 56
        GOTO LABEL_000D
        LOAD 56
        LOAD 00000D9A4H
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD 00000D9A4H
        LOAD 00000D9A4H
        GOTO LABEL_000D
        LOAD 00000D9A4H
        LOAD 00000D9A4H
        LOAD 00000D9A4H
        LOAD 00000D9A4H
        LOAD 00000D9A4H
        GOTO LABEL_000D
        LOAD 00000D9A4H
        LOAD 00000EAA4H
        LOAD 0000003A4H
        LOAD 00000D9A4H
        LOAD 000003654H
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD 000003654H
        LOAD 000003654H
        GOTO LABEL_000D
        LOAD 000003654H
        LOAD 000003654H
        LOAD 000003654H
        LOAD 000003654H
        LOAD 000003654H
        GOTO LABEL_000D
        LOAD 000003654H
        LOAD 000003A54H
        LOAD 0000000D4H
        LOAD 000003654H
        LOAD 52
        LOAD 52
        LOAD 52
        GOTO LABEL_000D
        LOAD 52
        LOAD 52
        LOAD 52
        GOTO LABEL_000D
        LOAD 52
        LOAD 52
        LOAD 52
        LOAD 52
        LOAD 0000000D4H
        LOAD 00003A964H
        LOAD 0000000D4H
        GOTO LABEL_000D
        LOAD 0000000D4H
        LOAD 0000000D4H
        LOAD 0000000D4H
        GOTO LABEL_000D
        LOAD 0000000D4H
        LOAD 0000000D4H
        LOAD 0000000D4H
        LOAD 000000364H
        LOAD 0000000D4H
        LOAD 0000000D4H
        LOAD 0000000D4H
        LOAD 0000000D4H
        LOAD 000000354H
        GOTO LABEL_000D
        LOAD 000000354H
        LOAD 000000D64H
        LOAD 000000DA4H
        LOAD 000000DA4H
        LOAD 000000DA4H
        GOTO LABEL_000D
        LOAD 000000DA4H
        LOAD 000000DA4H
        LOAD 000000DA4H
        LOAD 0000036A4H
        LOAD 000000DA4H
        LOAD 000000DA4H
        LOAD 000000DA4H
        LOAD 000000DA4H
        LOAD 0000035A4H
        LOAD 00003A964H
        LOAD 0000035A4H
        LOAD 00000D6A4H
        LOAD 000000354H
        LOAD 000000354H
        LOAD 000000354H
        GOTO LABEL_000D
        LOAD 000000354H
        LOAD 000000354H
        LOAD 000000354H
        LOAD 000000D94H
        LOAD 000000354H
        LOAD 000000354H
        LOAD 000000354H
        LOAD 000000354H
        LOAD 000000D54H
        LOAD 0000EA594H
        LOAD 000000D54H
        LOAD 000003594H
        LOAD 52
        LOAD 52
        LOAD 52
        GOTO LABEL_000D
        LOAD 52
        LOAD 52
        LOAD 52
        GOTO LABEL_000D
        LOAD 52
        LOAD 52
        LOAD 52
        LOAD 52
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD 0000000D4H
        GOTO LABEL_000D
        LOAD 0000000D4H
        LOAD 0000000D4H
        LOAD 0000000D4H
        GOTO LABEL_000D
        LOAD 0000000D4H
        LOAD 0000000D4H
        LOAD 0000000D4H
        LOAD 000000364H
        LOAD 0000000D4H
        LOAD 0000000D4H
        LOAD 0000000D4H
        LOAD 0000000D4H
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD 000000354H
        LOAD 000000D64H
        LOAD 000000DA4H
        LOAD 000000DA4H
        LOAD 000000DA4H
        GOTO LABEL_000D
        LOAD 000000DA4H
        LOAD 000000DA4H
        LOAD 000000DA4H
        LOAD 0000036A4H
        LOAD 000000DA4H
        LOAD 000000DA4H
        LOAD 000000DA4H
        LOAD 000000DA4H
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD 0000035A4H
        LOAD 00000D6A4H
        LOAD 000000354H
        LOAD 000000354H
        LOAD 000000354H
        GOTO LABEL_000D
        LOAD 000000354H
        LOAD 000000354H
        LOAD 000000354H
        LOAD 000000D94H
        LOAD 000000354H
        LOAD 000000354H
        LOAD 000000354H
        LOAD 000000354H
        GOTO LABEL_000D
        GOTO LABEL_000D
        LOAD 000000D54H
        LOAD 000003594H
    CASE_END

LABEL_02B1
    STORE VAR_0036
    AND 3
    STORE VAR_003A
    IF 1,0 = 3 THEN GOTO LABEL_005B
    TAG_WITH VAR_003A

LABEL_02B8
    INCREMENT VAR_0040
    INPUT REL,VAR_0040
    IF INPUT_ERROR <> 0 THEN GOTO LABEL_005B
    LOAD INPUT_STATUS
    IF 2,2 = 1 THEN GOTO LABEL_02B8
    LOAD VAR_0036
    ROTATE RIGHT,2
    GOTO LABEL_02B1


[MarkL]

Wow, this is great!

As a double check I changed some of the state decode text slightly, recompiled with ASM.EXE, and loaded the new version with the IA Format Utility on a 16702B.  Works perfectly on a 6802 processor I have connected.

I like your automatic comments for "unreferenced" and carrying the text values back to the line(s) that references it.  Your "unreferenced" works better than the -x (cross-reference) option in ASM.EXE.  The -x option misses references inside IF statements.

One thing I wanted to do with the 6800 IA is remove the dependency for displaying VMA=0 (unused) memory cycles.  When looking at code flow, I don't really care about internal processor cycles that only clutter up the screen and waste capture memory.  Some of the other display states not currently available via general probing can also be added.  Now it's all possible without starting from scratch.

[gslick]

I went through all 24 of the .R files extracted from the Inverse Assembler files in the original INVASM.ZIP and decoded them back into .S source files for use with the 10391B ASM.EXE assembler.

When the exception of the differences in original source file name information in the initial Name Record the resulting .R files produced by assembling the .S source files for use with the 10391B ASM.EXE assembler should binary compare with the originally extracted .R files.

The only other exception is that both the i80386_i.R and i80386_8.7.R files contains records for what appears to be a format string with the value 0x4401FFFF, which might mean "FORMAT 32,HEX,LEFT_JUSTIFIED", which should normally have a value 0x240883E0 without any of the extra bits set. Maybe the value 0x4401FFFF means something else. In both cases they appears to be unreferenced.

EDIT: I figured this out. The special format value 0x4401FFFF means "FORMAT ASCII". I missed that FORMAT option in the 10391B manual. I'll have to go back later and update the generated .S files where that was decoded as "FORMAT 32,HEX,LEFT_JUSTIFIED".

One of the last things that I had to figure out was the correct syntax for these opcodes. They are not listed in the 10391B manual, but are present in the AIAL table file. Three of the files in the INVASM collection use MARK_LINE opcodes.

Code: [Select]

                        1 "IAL"
                        2
    0000                3 ENTRY_POINT
    0000 00000000       4     NOP
    0001 0014           5     TRACE_ON                    * ION_TRACE = 20
    0002 0015           6     TRACE_OFF                   * IOFF_TRACE = 21
    0003 0018           7     MARK_LINE OTHER,NO_ADDRESS  * IMARKLINE_O_NA = 24
    0004 0019           8     MARK_LINE SOURCE,NO_ADDRESS * IMARKLINE_S_NA = 25
    0005 001A           9     MARK_LINE OTHER             * IMARKLINE_O_A = 26
    0006 001B          10     MARK_LINE SOURCE            * IMARKLINE_S_A = 27
    0007 001C          11     MARK_STATE DISPLAYED        * IMARKSTATE_DISP = 28
    0008 001D          12     MARK_STATE SUPPRESSED       * IMARKSTATE_SUP = 29
    0009 0013          13     RETURN

I haven't taken a real close look at these generated .S source files to make sure everything looks reasonable in all of them. I was more focused on just making sure they all assemble correctly and regenerate matching .R files for now. I'll go ahead and share what I have so far, for the handful of people that might actually be interested in this stuff.

[gslick]

Attached are decoded Inverse Assembler .S source code files for the 10342B HPIB, RS-232, RS-449 interface.

Code: [Select]

IA File: IHPIB_I
IA Description: "HPIB IA FOR INTERFACE        1_0"
IA Field Option: A

IA File: IRS232_I
IA Description: "RS232 IA FOR INTERFACE       1_0"
IA Field Option: A

IA File: IRS449_I
IA Description: "RS449 IA FOR INTERFACE       1_0"
IA Field Option: A

[TimInCanada]

Wow!  I am in absolute awe of you guys.  Well Done! 

Mark: I still can't get my 16702B/16712A to load the formatted 6800 IA, but the IA Format utility is happy with the .R file you came up with.  Thank you.

Tim

[sleary78]

I am using my HP1661CS with the ethernet option so i knocked up a python script to replace IALDOWN

https://pastebin.com/BfLZfBmj

Probably buggy but it works just like the original.

[jackrubin]

Wow! Just stumbled across this post on a topic that I haven't thought much about for the last few years. Great to see the current work and gslick still going at it! Thanks to Glenn, Mark and all the other contributors.

Best to all and a HP New Year!
Jack

*************
BTW, I'm not sure the license file - "The 16700 analyzers have the B4620B Software Correlation Tool option.  The analyzer comes with the tool installed, but needs a license to use.  Fortunately, the license file is available for non-commercial use (along with licenses for the other options)." - mentioned above made the transition from Yahoo groups to groups.io.

Can anyone point to a copy of it? I'll be happy to add it to Groups.io Agilent group

Thanks -

[MarkL]

BTW, I'm not sure the license file - "The 16700 analyzers have the B4620B Software Correlation Tool option.  The analyzer comes with the tool installed, but needs a license to use.  Fortunately, the license file is available for non-commercial use (along with licenses for the other options)." - mentioned above made the transition from Yahoo groups to groups.io.

Can anyone point to a copy of it? I'll be happy to add it to Groups.io Agilent group

The license file is text.  The content of the file is embedded in a post, so it got moved from yahoo and it's still there.

In the HP-Agilent-Keysight group, search for "16700 software tool sets" for a post from Apr 17 24, 2015.  Then search for "HP/Agilent 16702 Software Tools License Keys" for a followup spelling correction to the InfiniBand key.

EDIT: Correction on the date - it was Apr 24, not the 17th.

[MarkL]

I did some experimenting with the network protocol inverse assembler (aka. protocol decoder) on a 16702B logic analyzer and mikeselectricstuff's new etherdecode board.  I'm dropping a link in this thread since some of you IA fans may want to know how to set up and use the INETWRKE inverse assembler:

  https://www.eevblog.com/forum/testgear/ethernet-trigger-an-protocol-decoding-for-mso-or-logic-analyser/msg2088775/#msg2088775

It doesn't have to be used with Mike's board, but I thought it would be a fun way to learn more about the 16700 series capabilities and make Mike's board easier to use.

If you have questions specifically about the analyzer setup, it might be better to post them here so we don't throw Mike's thread too far off-topic.

[nemike]

I'm trying to load an inverse assembler for 68010 from invasm_v3 on my 1670d (latest firmware), I only recently got it and am trying to learn to use it but haven't had much success in understanding how to load an inverse assembler.  I downloaded invadm_v3 and while I can select "load analyzer from i68010_p" (shows file type: inverse_assem) it says "No state machines for this module", if I configure it as follows:

Label  0: ADDR     (24 bits):  A3: ******** ........  A2: ******** ********
Label  1: DATA     (16 bits):  A1: ******** ********
Label  2: STAT     ( 8 bits):  A3: ........ ********
Label  3: SIZE     ( 2 bits):  A3: ........ .....**.
Label  4: VMA      ( 1 bits):  A3: ........ ....*...
Label  5: FC       ( 3 bits):  A3: ........ .***....

And then "load analyzer from i68010_p" it flashes the asterisk in the top right but nothing seems to happen and when I go to config or waveform or listing I don't see anything...  What am I missing?

Thanks, Mike

[MarkL]

...
And then "load analyzer from i68010_p" it flashes the asterisk in the top right but nothing seems to happen and when I go to config or waveform or listing I don't see anything...  What am I missing?

Thanks, Mike

I don't have a 1670 series to directly help with the issue you're seeing, but you might try loading the configuration file c68010_p instead.  In my reading of the manual, I think loading the configuration file should automatically load the associated inverse assembler after it has processed the configuration.  Maybe there's some other setup it needs to perform first.

The configuration files in that zip file are for a 16510 analyzer, but the manual says the 1670G should be able to read them.

Perhaps someone with a 1670 (or 16510) could help out more.

[nemike]

I don't have a 1670 series to directly help with the issue you're seeing, but you might try loading the configuration file c68010_p instead.  In my reading of the manual, I think loading the configuration file should automatically load the associated inverse assembler after it has processed the configuration.  Maybe there's some other setup it needs to perform first.

The configuration files in that zip file are for a 16510 analyzer, but the manual says the 1670G should be able to read them.

Perhaps someone with a 1670 (or 16510) could help out more.

Thanks this helped, I was able to load the c68010_p and indeed the inverse assembler showed up in the listing section, but I did get some messages when it loaded:



This gave me the following format views:




I had setup my own configuration and format that looked like the c68010_p.txt file:



That is when I had tried to load the i68010_p file without error but it didn't seem to appear available in the listing view.

So I can use that 68010 as is but I can't use the invasm in my own configuration which might include other signals from elsewhere...

Thanks, Mike

[gslick]

I loaded c68010_p from invasm_v3 on a 16510 module in a 16500C and captured these resulting configuration screens.

Configuration:



Format:



Symbols:















Listing:

[gslick]

If you connect your 1670D to a network so that you can do FTP transfers to the analyzer from another machine on the network, you can send the program file below to the 1670D to recreate the c68010_p configuration on the 1670D.

On the 1670D System - External I/O screen make sure the Controller is Connected To: Ethernet (instead of HPIB or RS-232C). Then on the 1670D System - External I/O screen make sure the LAN Settings - Analyzer IP Address is appropriate for your network.

Then you can open an FTP connection to the 1670D from another system on your network and login as user "control". Then "cd /system", then "put program", assuming that the program below is saved to a file named "program" on system on which you are running FTP.

This program assumes that the invasm file "I68010_P" has been copied to the directory "\INVASMV3" on the hard drive of the 1670D.

I verified that this works on my 1670D.

Code: [Select]

:SELECT 1
:MACHINE1:NAME '68010'
:MACHINE1:ASSIGN 1,2,3,4
:MACHINE1:TYPE STATE
:MACHINE2:TYPE OFF
:MACHINE1:SFORMAT:MASTER J, RISING
:MACHINE1:SFORMAT:REMOVE ALL
:MACHINE1:SFORMAT:LABEL 'ADDR', POSITIVE, #H0, #H0000, #HFF00, #HFFFF, #H0000
:MACHINE1:SFORMAT:LABEL 'DATA', POSITIVE, #H0, #H0000, #H0000, #H0000, #HFFFF
:MACHINE1:SFORMAT:LABEL 'STAT', POSITIVE, #H0, #H0000, #H00FF, #H0000, #H0000
:MACHINE1:SFORMAT:LABEL 'SIZE', POSITIVE, #H0, #H0000, #H0006, #H0000, #H0000
:MACHINE1:SFORMAT:LABEL 'VMA',  POSITIVE, #H0, #H0000, #H0008, #H0000, #H0000
:MACHINE1:SFORMAT:LABEL 'FC',   POSITIVE, #H0, #H0000, #H0070, #H0000, #H0000
:MMEMORY:CD '\INVASMV3', INTERNAL0
:MMEMORY:LOAD:IASSEMBLER 'I68010_P', INTERNAL0, 1, 1
:MMEMORY:CD '\', INTERNAL0
:MACHINE1:SYMBOL:REMOVE
:MACHINE1:SYMBOL:WIDTH 'STAT', 15
:MACHINE1:SYMBOL:BASE  'STAT', BINARY
:MACHINE1:SYMBOL:PATTERN 'STAT', 'DMA',             '#B0XXXXXXX'
:MACHINE1:SYMBOL:PATTERN 'STAT', 'USER DATA WRITE', '#B1001XXX0'
:MACHINE1:SYMBOL:PATTERN 'STAT', 'USER DATA READ',  '#B1001XXX1'
:MACHINE1:SYMBOL:PATTERN 'STAT', 'USER PGRM READ',  '#B1010XXX1'
:MACHINE1:SYMBOL:PATTERN 'STAT', 'SUPR DATA WRITE', '#B1101XXX0'
:MACHINE1:SYMBOL:PATTERN 'STAT', 'SUPR DATA READ',  '#B1101XXX1'
:MACHINE1:SYMBOL:PATTERN 'STAT', 'SUPR PGRM READ',  '#B1110XXX1'
:MACHINE1:SYMBOL:PATTERN 'STAT', 'INTERRUPT ACK',   '#B1111XXXX'
:MACHINE1:SYMBOL:PATTERN 'STAT', 'OPCODE FETCH',    '#B1X10XXX1'
:MACHINE1:SYMBOL:PATTERN 'STAT', 'READ',            '#BXXXXXXX1'
:MACHINE1:SYMBOL:PATTERN 'STAT', 'WRITE',           '#BXXXXXXX0'
:MACHINE1:SYMBOL:WIDTH 'SIZE', 9
:MACHINE1:SYMBOL:BASE  'SIZE', BINARY
:MACHINE1:SYMBOL:PATTERN 'SIZE', 'LOW BYTE',  '#B10'
:MACHINE1:SYMBOL:PATTERN 'SIZE', 'HIGH BYTE', '#B01'
:MACHINE1:SYMBOL:PATTERN 'SIZE', 'WORD',      '#B00'
:MACHINE1:SYMBOL:WIDTH 'VMA', 10
:MACHINE1:SYMBOL:BASE  'VMA', BINARY
:MACHINE1:SYMBOL:PATTERN 'VMA', '6800 CYCLE', '#B1'
:MACHINE1:SYMBOL:PATTERN 'VMA', '',           '#B0'
:MACHINE1:SYMBOL:WIDTH 'FC', 9
:MACHINE1:SYMBOL:BASE  'FC', BINARY
:MACHINE1:SYMBOL:PATTERN 'FC', 'USER DATA', '#B001'
:MACHINE1:SYMBOL:PATTERN 'FC', 'USER PROG', '#B010'
:MACHINE1:SYMBOL:PATTERN 'FC', 'SUPR DATA', '#B101'
:MACHINE1:SYMBOL:PATTERN 'FC', 'SUPR PROG', '#B110'
:MACHINE1:SYMBOL:PATTERN 'FC', 'INTR ACK',  '#B111'
:MACHINE1:SYMBOL:PATTERN 'FC', 'USER',      '#B0XX'
:MACHINE1:SYMBOL:PATTERN 'FC', 'SUPR',      '#B1XX'
:MACHINE1:SYMBOL:PATTERN 'FC', '     DATA', '#BX01'
:MACHINE1:SYMBOL:PATTERN 'FC', '     PROG', '#BX10'
:MACHINE1:STRIGGER:CLEAR ALL
:MACHINE1:SLIST:REMOVE
:MACHINE1:SLIST:COLUMN 1, 'ADDR', HEXADECIMAL
:MACHINE1:SLIST:COLUMN 2, 'DATA', IASSEMBLER
:MACHINE1:SLIST:COLUMN 3, 'STAT', SYMBOL
:MACHINE1:SLIST:COLUMN 4, 'SIZE', SYMBOL
:MACHINE1:SLIST:COLUMN 5, 'VMA',  SYMBOL
:MACHINE1:SLIST:COLUMN 6, 'FC',   SYMBOL
:MACHINE1:SWAVEFORM:REMOVE
:MACHINE1:SWAVEFORM:INSERT 'ADDR', OVERLAY
:MACHINE1:SWAVEFORM:INSERT 'DATA', OVERLAY
:MACHINE1:SWAVEFORM:INSERT 'STAT', OVERLAY
:MENU 1,7


[Tom Swift]

I don't get it.  I've tried them all and they all say the same thing.  What am I doing wrong?

Nevermind, gotta change it to 'Load' 'Analyzer' from file '<file>'

The c6809e_p.txt file says:

Title: 6809E CONFIG FOR GP PROBES   1_0

Pod assigments (? = disabled)
-----------------------------
Label  0: ADDR     (16 bits):  A2: ******** ********  
Label  1: DATA     ( 8 bits):  A1: ........ ********  
Label  2: STAT     ( 3 bits):  A1: .....*** ........  

Symbols
-------
Label: STAT  
       INTR/RESET VECTR  01X
       SYNC ACKNOWLEDGE  10X
       HALT/BUS GRANT    11X
       WRITE             000
       READ              001

This is directly from the Motorola 6809 datasheet Page 6.

I'm guessing...
Pod A1: Channel 8 is to pin 32 of 6809E  (R//W)
Pod A1: Channel 9 is to pin 37 of 6809E (/RESET)
Pod A1: Channel 10 is to pin 40 of 6809E (/HALT)
Pod A1: Clk is to pin 34 of 6809E (E)

Is this correct?

Pod A1: Channel 8 is to pin 32 of 6809E  (R//W)
Pod A1: Channel 9 is to pin 5 of 6809E (BS)
Pod A1: Channel 10 is to pin 6 of 6809E (BA)
Pod A1: Clk is to pin 34 of 6809E (E)  (Still unsure about this one...)  (EDIT: This is correct)

Is this correct? (EDIT: This is correct)

So after all this I get:



Why isn't the address advancing?  It goes all the way to 4095 in the list.  RESET isn't LOW.

[gslick]

Title: 6809E CONFIG FOR GP PROBES   1_0

Pod assigments (? = disabled)
-----------------------------
Label  0: ADDR     (16 bits):  A2: ******** ********  
Label  1: DATA     ( 8 bits):  A1: ........ ********  
Label  2: STAT     ( 3 bits):  A1: .....*** ........  

Symbols
-------
Label: STAT  
       INTR/RESET VECTR  01X
       SYNC ACKNOWLEDGE  10X
       HALT/BUS GRANT    11X
       WRITE             000
       READ              001

Pod A1: Channel 8 is to pin 32 of 6809E  (R//W)
Pod A1: Channel 9 is to pin 5 of 6809E (BS)
Pod A1: Channel 10 is to pin 6 of 6809E (BA)
Pod A1: Clk is to pin 34 of 6809E (E)  (Still unsure about this one...)

Is this correct?

Why isn't the address advancing?  It goes all the way to 4095 in the list.  RESET isn't LOW.

I think you would want to clock on the falling edge of E. From the timing diagram it appears that both the address bus and the data bus should have stable and valid values at that point.

It does appear that using BA, BS, and R/W for the STAT signals would match the meaning of the MPU state definition according to those signals.

What happens if you trigger on address FFFF? There might be a lot of FFFE cycles when the reset condition first occurs.

[Tom Swift]

LOL!  I checked the wrong thread and wanted to reply.  Good call triggering on $FFFF.  So after going through all this, I have realized the data coming back after the initial vector read from $FFFE & $FFFF is getting corrupted.  I'll keep digging.  Thanks everyone!

[mmcgraw74]

I should spend some time looking at the 16900 series Analysis AddIn Tool. It might contain enough information to write a tool to decode a .R file back into something that could be assembled again with the IAL assembler.

For example it contains this instruction opcode table. The opcode bit field positions vary in the instruction word based on the values of high order bits in the instruction word.

Code: [Select]

  /* definitions for the different unique bit patterns for each instruction
   * in the different instruction groups -- used by the interpreter
   */


I had a similar problem loading the C6800/02.I file on my HP 16500.

I solved it by manually creating the 6800 mapping from gslick's screenshots in this thread, including the User Symbols, making sure the machine name was 6800/02, then saving to the C6800/02 IA file.  Another file was created with that same name but newer timestamp - it was bigger, and also created a new config.txt file with that name.  Then I could power cycle my HP16500B and load the C6800/02.I file successfully.  I only had to change the User Symbol table back to Binary to see the symbols I had entered.
  /* instruction group 1 */
  const u_int16 IF_OP = 4;
  const u_int16 IF_BITS = 5;
  const u_int16 ICASE_OP = 6;
  const u_int16 ICASE_BITS = 7;

  /* instruction group 2 */
  const u_int16 IGO_TO = 4;
  const u_int16 ICALL = 5;
  const u_int16 ISTR_OUTPUT = 6;
  const u_int16 INUM_OUTPUT = 7;

  /* instruction group 3 */
  const u_int16 ILOAD_ACC = 8;
  const u_int16 IADD_ACC = 9;
  const u_int16 ISUB_ACC = 10;
  const u_int16 IAND_ACC = 11;
  const u_int16 IOR_ACC = 12;
  const u_int16 IXOR_ACC = 13;
  const u_int16 ITAG_WITH = 14;
  const u_int16 INP_ABS = 15;

  /* instruction group 4 */
  const u_int16 ISTORE_MEM = 4;
  const u_int16 INC_MEM = 5;
  const u_int16 IDEC_MEM = 6;
  const u_int16 INP_ABSQ = 7;

  /* instruction group 5 */
  const u_int16 INP_REL = 2;
  const u_int16 INP_RELQ = 3;

  /* instruction group 6 */
  const u_int16 IROT_LEFT = 8;
  const u_int16 IROT_RIGHT = 9;
  const u_int16 IEXT_BIT = 10;
  const u_int16 IPOS_ABS = 11;
  const u_int16 IPOS_REL = 12;

  /* instruction group 7 */
  const u_int16 INOP = 16;
  const u_int16 ICOMP_ACC = 17;
  const u_int16 ITWOCOMP_ACC = 18;
  const u_int16 IRETURN = 19;
  const u_int16 ION_TRACE = 20;
  const u_int16 IOFF_TRACE = 21;
  const u_int16 IABORT = 22;
  const u_int16 IFNOT_MAP = 23;
  const u_int16 IMARKLINE_O_NA = 24;
  const u_int16 IMARKLINE_S_NA = 25;
  const u_int16 IMARKLINE_O_A = 26;
  const u_int16 IMARKLINE_S_A = 27;
  const u_int16 IMARKSTATE_DISP = 28;
  const u_int16 IMARKSTATE_SUP = 29;
  const u_int16 INEWLINE = 30;
  const u_int16 IFETCH_POSITION = 31;

If I have this correct, the mapping from opcode words to instructions in .R files is the following:

Code: [Select]

/* instruction group 1 */
/* conditional instruction -- bit 15 is set */
/* instruction = (opcode >> 13) */

100x xxxx xxxx xxxx     IF_OP = 4
101x xxxx xxxx xxxx     IF_BITS = 5
110x xxxx xxxx xxxx     ICASE_OP = 6
111x xxxx xxxx xxxx     ICASE_BITS = 7

/* instruction group 2 */
/* transfer/output instruction -- bit 14 is set */
/* instruction = (opcode >> 12) */

0100 xxxx xxxx xxxx     IGO_TO = 4
0101 xxxx xxxx xxxx     ICALL = 5
0110 xxxx xxxx xxxx     ISTR_OUTPUT = 6
0111 xxxx xxxx xxxx     INUM_OUTPUT = 7

/* set immediate instruction -- bit 13 is on */

001x xxxx xxxx xxxx

/* instruction group 3 */
/* math instruction -- bit 12 is on */
/* instruction = (opcode >> 9) */

0001 000x xxxx xxxx     ILOAD_ACC = 8
0001 001x xxxx xxxx     IADD_ACC = 9
0001 010x xxxx xxxx     ISUB_ACC = 10
0001 011x xxxx xxxx     IAND_ACC = 11
0001 100x xxxx xxxx     IOR_ACC = 12
0001 101x xxxx xxxx     IXOR_ACC = 13
0001 110x xxxx xxxx     ITAG_WITH = 14
0001 111x xxxx xxxx     INP_ABS = 15

/* instruction group 4 */
/* single variable instruction -- bit 11 is on */
/* instruction = (opcode >> 9) */

0000 100x xxxx xxxx     ISTORE_MEM = 4
0000 101x xxxx xxxx     INC_MEM = 5
0000 110x xxxx xxxx     IDEC_MEM = 6
0000 111x xxxx xxxx     INP_ABSQ = 7

/* instruction group 5 */
/* input relative instruction -- bit 10 is on */
/* instruction = (opcode >> 9) */

0000 010x xxxx xxxx     INP_REL = 2
0000 011x xxxx xxxx     INP_RELQ = 3

/* instruction group 6 */
/* single operand instruction -- bit 9 is on */
/* instruction = (opcode >> 6) */

0000 0010 00xx xxxx     IROT_LEFT = 8
0000 0010 01xx xxxx     IROT_RIGHT = 9
0000 0010 10xx xxxx     IEXT_BIT = 10
0000 0010 11xx xxxx     IPOS_ABS = 11
0000 0011 00xx xxxx     IPOS_REL = 12

/* instruction group 7 */
/* implied operand instruction - bits 15-5 off, bit 4 on */

0000 0000 0001 0000     INOP = 16
0000 0000 0001 0001     ICOMP_ACC = 17
0000 0000 0001 0010     ITWOCOMP_ACC = 18
0000 0000 0001 0011     IRETURN = 19
0000 0000 0001 0100     ION_TRACE = 20
0000 0000 0001 0101     IOFF_TRACE = 21
0000 0000 0001 0110     IABORT = 22
0000 0000 0001 0111     IFNOT_MAP = 23
0000 0000 0001 1000     IMARKLINE_O_NA = 24
0000 0000 0001 1001     IMARKLINE_S_NA = 25
0000 0000 0001 1010     IMARKLINE_O_A = 26
0000 0000 0001 1011     IMARKLINE_S_A = 27
0000 0000 0001 1100     IMARKSTATE_DISP = 28
0000 0000 0001 1101     IMARKSTATE_SUP = 29
0000 0000 0001 1110     INEWLINE = 30
0000 0000 0001 1111     IFETCH_POSITION = 31


[deanclaxton]

Fascinating thread - very good info. I was given a HP 16602A logic analyser which has a SCSI-SD card setup inside - I believe the previous owner has reinstalled the OS etc.

I now have to work out how to get it up and running, and am very interested in the inverse assemblers - especially for 6502, Z80, and 68000. I've seen some adapter boards that someone has done (http://pcbjunkie.net/index.php/2017/04/29/hp-agilent-logic-analyzer-adapters/) to make the whole setup easier - plug the 40 pin cables direct into the adapters. I've sent the fellow an email to see whether boards or gerbers are available.

A quick question for anyone who has one of these logic analysers - what is the best way to access the display? It doesnt have an inbuilt one so either external monitor or via some remote protocol - I guess external monitor is easier.

I'm not sure what optional licenses it has installed (if any) - are these still available? The link in the thread goes to Yahoo Groups which is on the way out.

Anyways - very keen to find out if this HP16602A that I have will be useful for debugging vintage computers (assuming I can work out how to get it all up and running!). Also keen to look at any upgrades for it - a scope module might be handy for example.

[TK]

Fascinating thread - very good info. I was given a HP 16602A logic analyser which has a SCSI-SD card setup inside - I believe the previous owner has reinstalled the OS etc.

I now have to work out how to get it up and running, and am very interested in the inverse assemblers - especially for 6502, Z80, and 68000. I've seen some adapter boards that someone has done (http://pcbjunkie.net/index.php/2017/04/29/hp-agilent-logic-analyzer-adapters/) to make the whole setup easier - plug the 40 pin cables direct into the adapters. I've sent the fellow an email to see whether boards or gerbers are available.

A quick question for anyone who has one of these logic analysers - what is the best way to access the display? It doesnt have an inbuilt one so either external monitor or via some remote protocol - I guess external monitor is easier.

I'm not sure what optional licenses it has installed (if any) - are these still available? The link in the thread goes to Yahoo Groups which is on the way out.

Anyways - very keen to find out if this HP16602A that I have will be useful for debugging vintage computers (assuming I can work out how to get it all up and running!). Also keen to look at any upgrades for it - a scope module might be handy for example.

The adapters look nice but I think they are not designed to match the wiring the inverse assembler expects.  i.e. the original HP 6502 Z80 adapter requires some logic circuitry to simulate delays and also the inverse assembler configuration file expects specific signals in certain pins.  The analyzer operates in state mode and needs to use the clock inputs in the PODs.

EDIT: Z80, not 6502

[TK]

Fascinating thread - very good info. I was given a HP 16602A logic analyser which has a SCSI-SD card setup inside - I believe the previous owner has reinstalled the OS etc.

I now have to work out how to get it up and running, and am very interested in the inverse assemblers - especially for 6502, Z80, and 68000. I've seen some adapter boards that someone has done (http://pcbjunkie.net/index.php/2017/04/29/hp-agilent-logic-analyzer-adapters/) to make the whole setup easier - plug the 40 pin cables direct into the adapters. I've sent the fellow an email to see whether boards or gerbers are available.

A quick question for anyone who has one of these logic analysers - what is the best way to access the display? It doesnt have an inbuilt one so either external monitor or via some remote protocol - I guess external monitor is easier.

I'm not sure what optional licenses it has installed (if any) - are these still available? The link in the thread goes to Yahoo Groups which is on the way out.

Anyways - very keen to find out if this HP16602A that I have will be useful for debugging vintage computers (assuming I can work out how to get it all up and running!). Also keen to look at any upgrades for it - a scope module might be handy for example.

Installation guide: https://www.keysight.com/upload/cmc_upload/All/16700710.pdf

It appears to be the HP-UX based analyzer.  You should be able to connect a monitor, keyboard and mouse and connect through X-Windows

[deanclaxton]

Ok thanks - from memory I had trouble finding a PS2 mouse that would work with it. Is there anything special about the mouse that would have shipped with the unit originally?

Oh - in regard to the 6502 adapter - is there a schematic available? Or does anyone have one that can be reverse engineered? I'm happy to throw a board together once I know what logic is required. I'll check the config files that have been generated for the pin info.

Trying to find an original 6502 adapter would be pretty tough going I expect.

EDIT : It appears that there is no 6502 inverse assembler within the uploaded files - is it still available somewhere?

[TK]

Ok thanks - from memory I had trouble finding a PS2 mouse that would work with it. Is there anything special about the mouse that would have shipped with the unit originally?

Oh - in regard to the 6502 adapter - is there a schematic available? Or does anyone have one that can be reverse engineered? I'm happy to throw a board together once I know what logic is required. I'll check the config files that have been generated for the pin info.

Trying to find an original 6502 adapter would be pretty tough going I expect.

EDIT : It appears that there is no 6502 inverse assembler within the uploaded files - is it still available somewhere?

Sorry, the adapter information was for the Z80: https://www.eevblog.com/forum/testgear/older-logic-analyzer-question/msg1206485/#msg1206485

The 6502 inverse assembler was written by someone else and it was made available through download.  Source files:https://stardot.org.uk/forums/viewtopic.php?t=11043

[MarkL]

Ok thanks - from memory I had trouble finding a PS2 mouse that would work with it. Is there anything special about the mouse that would have shipped with the unit originally?
...

It sounds like you might have the "missing pullup resistor" problem, the same as the 167xx series:

  https://www.eevblog.com/forum/testgear/hp-16702a-mouse/msg374967/#msg374967

Sometimes non-Agilent keyboards and mice work, sometimes they don't.

[deanclaxton]

Ok thanks - from memory I had trouble finding a PS2 mouse that would work with it. Is there anything special about the mouse that would have shipped with the unit originally?
...

It sounds like you might have the "missing pullup resistor" problem, the same as the 167xx series:

  https://www.eevblog.com/forum/testgear/hp-16702a-mouse/msg374967/#msg374967

Sometimes non-Agilent keyboards and mice work, sometimes they don't.

Interesting - I have a bunch of cheap PS2 mice I purchased a while ago (like 10 for $10 or something silly) that were to be used on the analyser (well, one of them anyway!) but didnt work - hopefully this might fix it Will fire up the old girl at the weekend and try get it up and running - I'm very keen to get the 6502 setup working - I'll aim to make an adapter PCB to make it fast to set it up, else its too much of a hassle to connect all the probes. The adapter I linked to earlier seems to have the termination network (2 resistors and a capacitor) per signal but no logic - I guess something along the lines of the Z80 one would be a starting point but it would be nice to find someone who has one and replicate it.

Are the 40 pin pod connector pinouts fairly standard across the HP 16xx(x) range? Initial board will be for the HP 16xxx as that is what I have on hand.

[TK]

The 40-pin pod connector is fairly standard.  If you want to play with inverse assemblers, make sure to create the adapter following the configuration file pinout for the ADDR, DATA and STAT signals as defined in the inverse assembler configuration file.  Connecting the POD pins to a 6502 or Z80 is not that difficult, just 16 address lines, 8 data lines and around 4 stat lines including correct clock combinations.

[deanclaxton]

The 40-pin pod connector is fairly standard.  If you want to play with inverse assemblers, make sure to create the adapter following the configuration file pinout for the ADDR, DATA and STAT signals as defined in the inverse assembler configuration file.  Connecting the POD pins to a 6502 or Z80 is not that difficult, just 16 address lines, 8 data lines and around 4 stat lines including correct clock combinations.

Will do. I have a 6502 IA here : https://www.dropbox.com/s/bjot0hxo9695s35/ia6502.zip?dl=0

Its not clear from the .S file which pod pins go where but it does list the input status bits and clocking on the falling edge of phi 2 :

************************************************************************
* Inverse assembler for the Western Design Center W65C02S
*
* INPUT_STATUS bits:
*             _
*   7       R/W
*           ___
*   6       RST
*           ___
*   5       NMI
*           ___
*   4       INT
*
*   3       SYNC
*
* Logic states must be clocked in on the falling edge of the 6502's
* PHI2o (phase-2-out) clock.
*

I'll have to read back through this thread to understand how to pull the required info from the other files.

[MarkL]

In 6502.S, the CASE_OF statement on line 101 says that it only cares about bits 4 through 1 of the STAT column.

So, the STAT column needs 5 signals assigned to it (MSB to LSB): R/W, RST, NMI, INT, and <anything>.  You can assign SYNC to bit 0 if you want.

The bit numbers shown in the beginning of 6502.S are probably just the assignments for those signals coming in from a probe pod.  You don't have to use those exact assignments, as long as the bits in your STAT column are defined in the order above.

That should work, but caveat that I don't have a 6502 to verify it.

[deanclaxton]

Ah ok. Do these files lock in particular pods and pod signals that it expects to be connected to data and address busses?

Ie pod 3, signal 0 = address 0?

I suppose this will all become clear once I get my unit up and running

[MarkL]

The signal mapping is completely flexible.

Connect up the pods as you like.  But to keep things sane, you should probably assign one pod to the ADDR lines, and one pod to STAT and DATA signals.  Preserve the ordering of MSB to LSB for the data and address lines.

The physical to logical mapping for each incoming probe signal is done in the pod assignment tab.  The field (column) names ADDR, DATA, and STAT are significant to the IA.  The IA expects to find the address signals from A15 to A0 assigned to ADDR, D7 to D0 to DATA, and the control signals to STAT as previously noted.

If you haven't used one of these LAs before, take a stroll through the help when you get your system running.  It's context sensitive, and it's the main source of documentation for all HW and SW operations.

The help files are also available on keysight.com in PDF under the various 167xx product home pages, but they're a bit scattered.  You have to look at each product home pages to really find everything.

[deanclaxton]

Thanks Mark - thats excellent. I've got it up and running - turns out the previous owner had done a complete rebuild before passing it on. I found a mouse (MS Intellimouse 1.1A USB with PS2 adapter) and keyboard (IBM KB-0225 PS2 keyboard) that work and am currently using the VGA output. I believe all the optional licenses are installed already as well. It has some IA's installed as well so I loaded up a 68000 one to take a look. I can see the pod assignment and under the fomat tab it shows all the various mapping (lots of signals mapped in).

Question for now would be whether the 6502 signals would need any timing adjustment as per the Z80 example where each signal is buffered plus a few are slightly delayed via additional gates etc. I'll throw together an initial adapter board and give it a go. If the logic analyser is set to sample the data on the falling edge of the phi2 clock (in the case of the 6502 example), would a delay ensure that the signals are valid when the analyser samples them - ie is it possible that it would otherwise sample the signals before they are valid - by delaying the phi2 clock signal a few ns perhaps ensures the bus data is valid when sampled? I guess I need to look at the 6502 datasheet for that info, and to actually start playing around with it to work it all out. In general I wonder if cpu adapters sold by vendors would buffer all the bus signals (as per the Z80 one), and why that might be required.

EDIT : Ah - reading back in the thread here (https://www.eevblog.com/forum/testgear/older-logic-analyzer-question/msg1206485/#msg1206485) it seems that the Z80 timing is more complex - seems that TK was using the 6502 inverse assembler directly, so perhaps I wont need anything on my adapter other than the termination. Will give it a go!

[TK]

It is correct, 6502 does not need any additional circuitry.  Just the correct pins for STAT, in addition to ADDR and DATA

[deanclaxton]

It is correct, 6502 does not need any additional circuitry.  Just the correct pins for STAT, in addition to ADDR and DATA

Thanks TK - is is possible to see your configuration as to which pod pins you used to interface to the 6502? Also did you use the IA from Phil Pemberton or another one?

[MarkL]

I said:

The signal mapping is completely flexible.

Connect up the pods as you like.  But to keep things sane, you should probably assign one pod to the ADDR lines, and one pod to STAT and DATA signals.  Preserve the ordering of MSB to LSB for the data and address lines.
...

It dawned on me today that you said you have a 16602A.  I don't have one to verify, but I don't believe arbitrary bit ordering is supported on it.  That feature seems to have been added in an early 2.xx release, and a recent post in the HPAK groups.io says that the 16600 series doesn't run version 2.xx.

So... What I said about ADDR, DATA, and STAT is still true, expect you DO have to connect the signals in the right physical order of MSB to LSB (consecutively) so that the logical bits are also in the same order when you define those labels.  A minor detail, but I didn't want to leave you with incorrect info, wondering what I was talking about.

On the setup and hold question, the spec sheet says that the 16602A has an adjustable setup and hold time of 0 to 4.5ns, if you run into trouble with delay.

[gslick]

It is correct, 6502 does not need any additional circuitry.  Just the correct pins for STAT, in addition to ADDR and DATA

Thanks TK - is is possible to see your configuration as to which pod pins you used to interface to the 6502? Also did you use the IA from Phil Pemberton or another one?

This is how I configured a 1670 series analyzer to use the 6502 inverse assembler:

[philpem]

Its not clear from the .S file which pod pins go where but it does list the input status bits and clocking on the falling edge of phi 2 :

************************************************************************
* Inverse assembler for the Western Design Center W65C02S
*
* INPUT_STATUS bits:
*             _
*   7       R/W
*           ___
*   6       RST
*           ___
*   5       NMI
*           ___
*   4       INT
*
*   3       SYNC
*
* Logic states must be clocked in on the falling edge of the 6502's
* PHI2o (phase-2-out) clock.
*

That's the inverse assembler I wrote back while I was in my late teens... I was building a 6502 SBC and wrote an IA to help debug it.

To get it working, you hook the CPU address bus up to one pod (16 bits) and declare it as ADDR in the IA. Hook the data bus up to the low half of the other probe and declare it as DATA. Hook up the STAT lines as above. The bits refer to the bit assignments in the STAT word -- from memory, I assigned the whole top byte to STAT then declared separate labels for the individual pins.

Connect PHI2-Out from the 6502 to the J-clock or K-clock. Set that as your storage clock, triggered on a H->L edge.

The IA's written for the Western Design Center W65C02S, so it supports the extended instructions (at least the ones supported by that particular chip).

There was never a test adapter. I shoved a DIN41612 connector into the backplane and wired up pods to the back of it. These days if I was planning to use the rig more than once, I'd use the 20way IDC, Samtec or Mictor transition adapters and spin a PCB...

Glad to see this crusty old code is still useful nearly 20 years later! Shame I forgot to stick my name on it, though I didn't expect it to spread far!
It came with a version of IALDOWN I wrote in Borland Delphi because the DOS one didn't work under Windows.

My notes on IAL are probably still floating around, I ripped apart the IAL .R format and instruction set during a break at university.

Cheers,
Phil.

[deanclaxton]

Wow - thats awesome - thanks Phil! I'm going to lay out a PCB for this - probably with a jumper to select which clock (phi0, 1, or 2) wires to the pod, and also include a couple of clip points for +5V and GND which would give me a handy location to safely connect a logic probe, scope ground lead, etc (for additional troubleshooting on a board).

There are a few leftover pod signal lines that could pick up the remaining signals on a 6502 (SO, RDY) for timing analysis/general troubleshooting, however the 65C02 has a few more again (MLB, BE, VPB). VPB (pin 1) is another GND on a 6502. Rather than use another pod connector, I might have to decide which of these signals are must - haves. Will check out some of the boards I'd be troubleshooting to determine which were used commonly.

[xadhoom76]

hi to all and thanks for this epic thread !
I'm new owner of HP 16500A, I have timing/state modules the one with ID 31
When I try to load any invasm ( would like to use it for z80 ) i got SOFTWARE ERROR - Please record these number  0010 0000006E 2000
My unit is with 1MB ram and Operating System v.6.
Thanks

[gslick]

hi to all and thanks for this epic thread !
I'm new owner of HP 16500A, I have timing/state modules the one with ID 31
When I try to load any invasm ( would like to use it for z80 ) i got SOFTWARE ERROR - Please record these number  0010 0000006E 2000
My unit is with 1MB ram and Operating System v.6.
Thanks

I just tried loading some of the INVASM files on a 16510A analyzer module installed in a 16500A mainframe with a 1MB CPU running Version 6.00 of the system software and they seemed to load fine for me without any error.

Maybe something went wrong with the method you used to create the floppy disks you are using. Do you have a PC with a 3.5-inch floppy drive that you can use to boot into real mode MS-DOS? If you can download and run ImageDisk 1.18 on a PC in real mode MS-DOS I have attached an ImageDisk image of a 720-KB LIF format floppy disk (not a 1.44MB HD floppy disk) that contains the 16500A Version 6.00 SYSTEM_ and SYSTEM_031 files plus some Config and IA files that I was able to load without errors.

ImageDisk 1.18 download link here:
http://www.classiccmp.org/dunfield/img/index.htm

Code: [Select]

DISK DIRECTORY                                                                 

DOS Filename  Date    Time     Bytes   Description
____________  _______ ________ _______ ________________________________

C68000_P       2Jun20 13:05:19   18944 68000 CONFIG FOR GP PROBES   1_0
C68008_P       2Jun20 13:05:50   18944 68008 CONFIG FOR GP PROBES   1_0
C6800_P        2Jun20 13:06:11   18432 6800/02 CONFIG FOR GP PROBES 1_0
C68010_P       2Jun20 13:06:32   18944 68010 CONFIG FOR GP PROBES   1_0
C6809E_P       2Jun20 13:06:52   18432 6809E CONFIG FOR GP PROBES   1_0
C6809_P        2Jun20 13:07:08   18432 6809 CONFIG FOR GP PROBES    1_0
C8085_P        2Jun20 13:07:29   18432 8085 CONFIG FOR GP PROBES    1_0
I68000_P       2Jun20 13:07:50    9216 68000 IA FOR GP PROBES       1_0
I68008_P       2Jun20 13:08:05    9728 68008 IA FOR GP PROBES       1_0
I6800_P        2Jun20 13:08:21    9216 6800/02 IA FOR GP PROBES     1_0
I68010_P       2Jun20 13:08:37    9984 68010 IA FOR GP PROBES       1_0
I6809E_P       2Jun20 13:08:54   10240 6809E IA FOR GP PROBES       1_0
I6809_P        2Jun20 13:09:09   10240 6809 IA FOR GP PROBES        1_0
I8085_IP       2Jun20 13:09:39    5120 8085 INVERSE ASSEMBLER       1_0
SYSTEM_       31Oct89  0:02:00  233728 HP16500A System Software  V06.00
SYSTEM_031    31Oct89  0:02:00  252160 35MHz State/100MHz Timing V06.00


[xadhoom76]

Great it WORKS !!! Thanks Master !

[xadhoom76]

In my test I use lifutil but the files listed on HP16500A seems to miss some
Your listing
DISK DIRECTORY                                                                 

DOS Filename  Date    Time     Bytes   Description
____________  _______ ________ _______ ________________________________

C68000_P       2Jun20 13:05:19   18944 68000 CONFIG FOR GP PROBES   1_0
C68008_P       2Jun20 13:05:50   18944 68008 CONFIG FOR GP PROBES   1_0
C6800_P        2Jun20 13:06:11   18432 6800/02 CONFIG FOR GP PROBES 1_0
C68010_P       2Jun20 13:06:32   18944 68010 CONFIG FOR GP PROBES   1_0
C6809E_P       2Jun20 13:06:52   18432 6809E CONFIG FOR GP PROBES   1_0
C6809_P        2Jun20 13:07:08   18432 6809 CONFIG FOR GP PROBES    1_0
C8085_P        2Jun20 13:07:29   18432 8085 CONFIG FOR GP PROBES    1_0
I68000_P       2Jun20 13:07:50    9216 68000 IA FOR GP PROBES       1_0
I68008_P       2Jun20 13:08:05    9728 68008 IA FOR GP PROBES       1_0
I6800_P        2Jun20 13:08:21    9216 6800/02 IA FOR GP PROBES     1_0
I68010_P       2Jun20 13:08:37    9984 68010 IA FOR GP PROBES       1_0

If I add cz80_P and iz80_i it doesn't work and i notice the file is missing the description.

My add using lifutil could be wrong ?
I work in dos directly booting from a floppy on my old pc. then lifutil and I choos dos to lif .
I try different format of files ( DFS or other ) but no way to make it working.
Sorry to bored you but really do not understand why.
I would like to use 16500A with z80 and 6502
Best regards and thanks. I will try again , your floppy works great.

[mmcgraw74]

Attached are decoded Inverse Assembler .S source code files for the 10342B HPIB, RS-232, RS-449 interface.

Code: [Select]

IA File: IHPIB_I
IA Description: "HPIB IA FOR INTERFACE        1_0"
IA Field Option: A

IA File: IRS232_I
IA Description: "RS232 IA FOR INTERFACE       1_0"
IA Field Option: A

IA File: IRS449_I
IA Description: "RS449 IA FOR INTERFACE       1_0"
IA Field Option: A

I'm trying to hook up my HP 10342B HPIB preprocessor to my 16500 logic analyzer.

I loaded the IHPIB_I file onto the SSD replacement for the hard disk.

Now I'm looking for the CHPIB_I configuration file listed in the 10342B manual.

Does anyone have the config file? 

I see a couple of logic analyzer menus in the doc, if I need to construct the config file manually.

This thread is an amazing source of information for the HP Inverse Assembler.

[gslick]

I'm trying to hook up my HP 10342B HPIB preprocessor to my 16500 logic analyzer.

I loaded the IHPIB_I file onto the SSD replacement for the hard disk.

Now I'm looking for the CHPIB_I configuration file listed in the 10342B manual.

Does anyone have the config file? 

Rather than trying to find another copy of these files posted somewhere else it's quicker to just attach another copy of the 10342B files here:

Code: [Select]

19,712 CHPIB_51
19,712 CHPIB_I
19,712 CRS232_51
19,712 CRS232_I
19,712 CRS449_51
19,712 CRS449_I
 3,584 IHPIB_I
13,056 IRS232_I
13,056 IRS449_I

[mmcgraw74]

I'm trying to hook up my HP 10342B HPIB preprocessor to my 16500 logic analyzer.

I loaded the IHPIB_I file onto the SSD replacement for the hard disk.

Now I'm looking for the CHPIB_I configuration file listed in the 10342B manual.

Does anyone have the config file? 

Rather than trying to find another copy of these files posted somewhere else it's quicker to just attach another copy of the 10342B files here:

Code: [Select]

19,712 CHPIB_51
19,712 CHPIB_I
19,712 CRS232_51
19,712 CRS232_I
19,712 CRS449_51
19,712 CRS449_I
 3,584 IHPIB_I
13,056 IRS232_I
13,056 IRS449_I

Outstanding!  Thank you!

[deanclaxton]

I used ALLPCB's free service to do a little board for the 65C02. The free boards are a little limited so the signal return path isnt ideal, but can't be too much worse than using the single ground on the pods. Has the termination network on the underside. Will be interesting to give this a go. It should make it very fast to set up the analyser!

[gslick]

I used ALLPCB's free service to do a little board for the 65C02. The free boards are a little limited so the signal return path isnt ideal, but can't be too much worse than using the single ground on the pods. Has the termination network on the underside. Will be interesting to give this a go. It should make it very fast to set up the analyser!

Would it be any easier to layout and build the PCB if it was designed to use a couple of 01650-63203 termination adapters? Then it wouldn't need the termination network on the PCB.

I suppose that wouldn't do any good for anyone that doesn't have any of the 01650-63203 termination adapters. I happen to have a whole box full of them.

[deanclaxton]

I used ALLPCB's free service to do a little board for the 65C02. The free boards are a little limited so the signal return path isnt ideal, but can't be too much worse than using the single ground on the pods. Has the termination network on the underside. Will be interesting to give this a go. It should make it very fast to set up the analyser!

Would it be any easier to layout and build the PCB if it was designed to use a couple of 01650-63203 termination adapters? Then it wouldn't need the termination network on the PCB.

I suppose that wouldn't do any good for anyone that doesn't have any of the 01650-63203 termination adapters. I happen to have a whole box full of them.

Quite possibly - yes - it would make it a bit neater and smaller also. Ideally you'd want a ground plane just under the signal layer - this one is done in 1.6mm and whilst there is a flood fill ground on the top layer its not the best. But I'm hoping it will be fine for what I want I wouldnt mind some of those adapters if you are wanting to sell a few?

EDIT : meant to say the boards arrived yesterday and I built one up this morning. Didnt take too long to install the termination network even without a stencil (hand soldered). Just need to get a 40 pin ZIF and I can give it a go.

Thanks to ALLPCB though - the boards were totally free including shipping!

[mmcgraw74]

While searching the Keysight Technologies website this morning for more Inverse Assembler information, I found the answer to the problem of loading an inverse assembler into my HP16500B logic analyzer.

I kept getting an error message: "No Configuration Loaded"

The answer was on the Keysight site in a document - here is the text with my red text for the solution:

"If a user were to save configuration/data files to disk, the mainframe would write the mainframe slot
location of the instrument module into the saved file. Then, when a user reloads the file into the
module and does not specify a destination slot, the mainframe will assume that the module is in the
same slot it was in when the configuration file was originally saved and will attempt to load the
configuration file in the instrument module in that particular mainframe slot.

However, configuration files that come with preprocessors do not have the source location (card
slot) written into them. Hence, if the destination field in the Disk menu says "All" when customers
try to load the file, they will see the message "no configuration loaded". They should change "All" to
the intended destination - "State/Timing E", for instance. Only then will the file be successfully
loaded."

Here is a screenshot from trying that on my 16500B with the CHPIB_I file.  I used paint to add back the popup messages that disappeared when I pressed the PRINT button.

[mmcgraw74]

I found two HP 10342B Bus Preprocessor Operating Manuals on the web - an Aug85 version which describes using the Bus Preprocessor with the HP 10269 A/B General Purpose Probe interface for use with the HP 1630 A/D/G or 1631 A/D probes and the Nov87 version which describes use with the 10269C General Purpose Probe Interface for use with the 1650A, 1651A logic analyzers, or the 16500 series logic analyzers with the 16510A logic analyzer module.

My HP 10342B Bus Preprocessor for HP-IB (GPIB), RS-232 and RS-449 did not come with the ribbon cable to connect to GPIB.

Since I couldn't find a schematic, nor service manual - I ohmed out the 10342B GPIB ribbon connector pins to the internal GPIB labeled header. 

Here is the 10342B front panel GPIB ribbon connector pinout:

Code: [Select]

10342B HP-IB HEADER conn pinout
  10342B      GPIB    10342B
  Header      pin#    Header
Name   Pin#  _____  Pin# Name
            |     |
ATN     1   |11 7 | 13  NFRD
SRQ     2   |10 6 | 14  DAV
IFC     3   |9  17| 15  REN
NDAC    4   |8  5 | 16  EOI
DIO8    5   |16 15| 17  DIO7
DIO6    6   |14 18| 18  GND
DIO5    7   |13 19| 19  GND
DIO4    8   |4  20| 20  GND
DIO3    9   |3  21| 21  GND
DIO2    10  |2  22| 22  GND
DIO1    11  |1  23| 23  GND
N/C     12  |12 24| 24  GND
            |_____|


This pinout is substantially different than the pinout arrangement of a GPIB connector (rectangle in center of my diagram), so possibly the proper HP cable used a PCB mount GPIB connector, see attached image of a GPIB connector (cable end):



I used a ribbon cable GPIB connector - but had to shred the end of the ribbon cable and rewired it to the proper GPIB connector (cable end) pinout.

[gslick]

This pinout is substantially different than the pinout arrangement of a GPIB connector (rectangle in center of my diagram), so possibly the proper HP cable used a PCB mount GPIB connector, see attached image of a GPIB connector (cable end):

The original HP-IB (IEEE488) cable provided by HP for the 10342B is just a straight through 24-pin ribbon cable to an IDC ribbon cable connector such as a 3M 3548. Nothing unusual going on.

Code: [Select]

10342B Internal Timing POD Header J9
D1  ATN
D2  SRQ
D3  IFC
D4  NDAC
D5  NRFD
D6  DAV
D7  REN
D8  EOI

10342B Front Panel HP-IB Header Connections to Internal Header J9
D1    D5
D2    D6
D3    D7
D4    D8
EOI   REN
DAV   GND
NRFD  GND
NDAC  GND
IFC   GND
SRC   GND
ATN   GND
N/C   GND
*     *    (Pins not populated on the 26-pin header)


[deanclaxton]

I've been using the adapter I made along with the 65C02 inverse assembler - works great!

I did however discover a bug in the inverse assembler branch calculation. I wonder if source is still available to be able to fix this?

-159            D010      00
-158            0000      00   memory read
-157            D011      F0   BEQ $D01D  (+$05)
-156            D012      05
-155            D013      5D   memory read
-154            D018      9D   STA $0100, x

see above - the BEQ calculation that calculates the branch to $D01D - should be $D018 which is where the cpu actually branches to as can be seen as the next executed address.

[gslick]

I've been using the adapter I made along with the 65C02 inverse assembler - works great!

I did however discover a bug in the inverse assembler branch calculation. I wonder if source is still available to be able to fix this?

-159            D010      00
-158            0000      00   memory read
-157            D011      F0   BEQ $D01D  (+$05)
-156            D012      05
-155            D013      5D   memory read
-154            D018      9D   STA $0100, x

see above - the BEQ calculation that calculates the branch to $D01D - should be $D018 which is where the cpu actually branches to as can be seen as the next executed address.

If philpem is here, and if he can remember anything about this code, maybe he can comment on this.

Perhaps the line after the label RELA_POSITIVE should either be "LOAD INPUT_ADDRESS" instead of "ADD INPUT_ADDRESS", or the following "ADD RELTEMP" line should be removed. If I understand what is happening here the error is that the "RELTEMP" displacement is effectively being added in twice instead of just once.

Code: [Select]

*** Output a relative address
OUTPUT_REL_ADDR
    CALL        READ_OPERAND
    STORE       RELTEMP
    STORE       RELTEMP2

    IF 7,7 = 1  THEN GOTO RELA_NEGATIVE
RELA_POSITIVE
* relative addr is positive
    ADD         INPUT_ADDRESS
    ADD         01h
    ADD         RELTEMP
    GOTO        RELA_DONE
    AND         0FFFFh
RELA_NEGATIVE
* relative addr is negative
    TWOS_COMPLEMENT
    AND         07Fh
    STORE       RELTEMP
    LOAD        INPUT_ADDRESS
    SUBTRACT    RELTEMP
    ADD         01h
    AND         0FFFFh
RELA_DONE
    CALL        ADDR_MAP            * display either the address or a symbol
RELA_ADR
    LOAD    RELTEMP2
    IF 7,7 = 0  THEN OUTPUT "  (+$"
    IF 7,7 = 1  THEN OUTPUT "  (-$"
    IF 7,7 = 1  THEN TWOS_COMPLEMENT
    OUTPUT      ACCUMULATOR,HEX7_FMT
    OUTPUT      ")"
    RETURN


[deanclaxton]

Of course - the .S file is there in the fileset! Excellent. Do I need to compile it to a .R file? I cant recall which file I selected on the analyzer to actually load it - .R? Maybe the IA6502 file?

Would be cool to work that out though so I can play around a little and try fix the branch calculation.

some more examples below :
 

Code: [Select]

 
-157            D011      F0   BEQ $D01D  (+$05)            D011       -154.544 us    F0      11111     1         
-156            D012      05                                D012       -153.560 us    05      11110     1         
-155            D013      5D   memory read                  D013       -152.576 us    5D      11110     1         
-154            D018      9D   STA $0100, x                 D018       -151.592 us    9D      11111     1         
...     
-145            D01E      F0   BEQ $D02A  (+$05)            D01E       -142.752 us    F0      11111     1         
-144            D01F      05                                D01F       -141.768 us    05      11110     1         
-143            D020      5D   memory read                  D020       -140.784 us    5D      11110     1         
-142            D025      9D   STA $0200, x                 D025       -139.800 us    9D      11111     1         
...
-133            D02B      F0   BEQ $D037  (+$05)            D02B       -130.960 us    F0      11111     1         
-132            D02C      05                                D02C       -129.976 us    05      11110     1         
-131            D02D      5D   memory read                  D02D       -128.992 us    5D      11110     1         
-130            D032      9D   STA $0100, x                 D032       -128.008 us    9D      11111     1         
...
-121            D038      F0   BEQ $D044  (+$05)            D038       -119.168 us    F0      11111     1         
-120            D039      05                                D039       -118.048 us    05      11110     1         
-119            D03A      5D   memory read                  D03A       -117.064 us    5D      11110     1         
-118            D03F      9D   STA $0400, x                 D03F       -116.080 us    9D      11111     1         

I think you are right - it seems to be doubling the offset.

[gslick]

If you modify the .S source file you need to run it through the 10391B ASM.EXE assembler to produce an updated .R file. Then you need to use the IALDOWN.EXE utility to download the .R file to a disk in the analyzer floppy drive through the analyzer serial port from a serial port on a PC.

If you haven't done that before, it can be a hassle to set up. On a 64-bit system you need to run ASM.EXE in a 32-bit VM since it is a 16-bit executable. Then running IALDOWN.EXE on anything except a real hardware slow system might not work correctly. If you do have an updated .R file there are alternatives to using IALDOWN.EXE than can work more reliable from a modern PC.

[gslick]

Try this attached version of a modified 6502 inverse assembler. I just did a quick binary patch to the original inverse assembler file. That was quicker for me to do than to set up an analyzer so I could do the equivalent of running IALDOWN to download an updated .R file.

The first two byte change replaces the "ADD RELTEMP" with a NOP. The second two byte change is a change to the checksum of the record containing the previous two bytes which were changed.

Code: [Select]

Comparing files I6502 and I6502X
0000232D: 12 00
0000232E: 1F 10
00002331: B6 A4
00002332: 8D 7E

Code: [Select]

LABEL_02C7
    CALL LABEL_0328
    STORE VAR_003E
    STORE VAR_0040
    IF 7,7 = 1 THEN GOTO LABEL_02D2
    ADD INPUT_ADDRESS
    ADD 1
    NOP
    GOTO LABEL_02D9
    AND 00000FFFFH


[deanclaxton]

Awesome - thank you! I will give that a go asap and let you know - hopefully tonight depending whats happening at home

[deanclaxton]

Sorry for the delay but I finally got to test this tonight - it works! Great job

A code snippet using the updated ia :

Code: [Select]

State Number    ADDR    6502 mnemonic                       ADDR       Time           DATA    STAT      RW        RST       NMI       INT       SYNC      RDY       VP        ML       
Decimal         Hex     Hex                                 Hex        Absolute       Hex     Binary    Binary    Binary    Binary    Binary    Binary    Binary    Binary    Binary   
____________    ____    ________________________________    _______    ___________    ____    ______    ______    ______    ______    ______    ______    ______    ______    ______   

 
21              D00E      DD   CMP $0000, x                 D00E        20.632 us     DD      11111     1         1         1         1         1         1         0         1         
22              D00F      00                                D00F        21.616 us     00      11110     1         1         1         1         0         1         0         1         
23              D010      00                                D010        22.600 us     00      11110     1         1         1         1         0         1         0         1         
24              0000      00   memory read                  0000        23.576 us     00      11110     1         1         1         1         0         1         0         1         
25              D011      F0   BEQ $D018  (+$05)            D011        24.560 us     F0      11111     1         1         1         1         1         1         0         1         
26              D012      05                                D012        25.544 us     05      11110     1         1         1         1         0         1         0         1         
27              D013      5D   memory read                  D013        26.528 us     5D      11110     1         1         1         1         0         1         0         1         
28              D018      9D   STA $0100, x                 D018        27.512 us     9D      11111     1         1         1         1         1         1         0         1         
29              D019      00                                D019        28.496 us     00      11110     1         1         1         1         0         1         0         1         
30              D01A      01                                D01A        29.472 us     01      11110     1         1         1         1         0         1         0         1         
31              0100      34   memory read                  0100        30.456 us     34      11110     1         1         1         1         0         1         0         1         
32              0100      00   memory write                 0100        31.440 us     00      01110     0         1         1         1         0         1         0         1         
33              D01B      DD   CMP $0100, x                 D01B        32.424 us     DD      11111     1         1         1         1         1         1         0         1         
34              D01C      00                                D01C        33.408 us     00      11110     1         1         1         1         0         1         0         1         
35              D01D      01                                D01D        34.384 us     01      11110     1         1         1         1         0         1         0         1         
36              0100      00   memory read                  0100        35.368 us     00      11110     1         1         1         1         0         1         0         1         
37              D01E      F0   BEQ $D025  (+$05)            D01E        36.352 us     F0      11111     1         1         1         1         1         1         0         1         
38              D01F      05                                D01F        37.336 us     05      11110     1         1         1         1         0         1         0         1         
39              D020      5D   memory read                  D020        38.320 us     5D      11110     1         1         1         1         0         1         0         1         
40              D025      9D   STA $0200, x                 D025        39.304 us     9D      11111     1         1         1         1         1         1         0         1         
41              D026      00                                D026        40.280 us     00      11110     1         1         1         1         0         1         0         1         
42              D027      02                                D027        41.264 us     02      11110     1         1         1         1         0         1         0         1         
43              0200      00   memory read                  0200        42.248 us     00      11110     1         1         1         1         0         1         0         1         
44              0200      00   memory write                 0200        43.232 us     00      01110     0         1         1         1         0         1         0         1         
45              D028      DD   CMP $0200, x                 D028        44.208 us     DD      11111     1         1         1         1         1         1         0         1         
46              D029      00                                D029        45.192 us     00      11110     1         1         1         1         0         1         0         1         
47              D02A      02                                D02A        46.176 us     02      11110     1         1         1         1         0         1         0         1         
48              0200      00   memory read                  0200        47.160 us     00      11110     1         1         1         1         0         1         0         1         
49              D02B      F0   BEQ $D032  (+$05)            D02B        48.144 us     F0      11111     1         1         1         1         1         1         0         1         
50              D02C      05                                D02C        49.128 us     05      11110     1         1         1         1         0         1         0         1         
51              D02D      5D   memory read                  D02D        50.104 us     5D      11110     1         1         1         1         0         1         0         1         
52              D032      9D   STA $0100, x                 D032        51.088 us     9D      11111     1         1         1         1         1         1         0         1         
53              D033      00                                D033        52.072 us     00      11110     1         1         1         1         0         1         0         1         
54              D034      01                                D034        53.056 us     01      11110     1         1         1         1         0         1         0         1         
55              0100      00   memory read                  0100        54.040 us     00      11110     1         1         1         1         0         1         0         1         
56              0100      00   memory write                 0100        55.024 us     00      01110     0         1         1         1         0         1         0         1         
57              D035      DD   CMP $0300, x                 D035        56.000 us     DD      11111     1         1         1         1         1         1         0         1         
58              D036      00                                D036        56.984 us     00      11110     1         1         1         1         0         1         0         1         
59              D037      03                                D037        57.968 us     03      11110     1         1         1         1         0         1         0         1         
60              0300      00   memory read                  0300        58.952 us     00      11110     1         1         1         1         0         1         0         1         
61              D038      F0   BEQ $D03F  (+$05)            D038        59.936 us     F0      11111     1         1         1         1         1         1         0         1         
62              D039      05                                D039        61.056 us     05      11110     1         1         1         1         0         1         0         1         
63              D03A      5D   memory read                  D03A        62.040 us     5D      11110     1         1         1         1         0         1         0         1         
64              D03F      9D   STA $0400, x                 D03F        63.024 us     9D      11111     1         1         1         1         1         1         0         1         
65              D040      00                                D040        64.000 us     00      11110     1         1         1         1         0         1         0         1         
66              D041      04                                D041        64.984 us     04      11110     1         1         1         1         0         1         0         1         
67              0400      00   memory read                  0400        65.968 us     00      11110     1         1         1         1         0         1         0         1         
68              0400      00   memory write                 0400        66.952 us     00      01110     0         1         1         1         0         1         0         1         
69              D042      DD   CMP $0400, x                 D042        67.936 us     DD      11111     1         1         1         1         1         1         0         1         
70              D043      00                                D043        68.912 us     00      11110     1         1         1         1         0         1         0         1         
71              D044      04                                D044        69.896 us     04      11110     1         1         1         1         0         1         0         1         
72              0400      00   memory read                  0400        70.880 us     00      11110     1         1         1         1         0         1         0         1         
73              D045      F0   BEQ $D04C  (+$05)            D045        71.864 us     F0      11111     1         1         1         1         1         1         0         1         
74              D046      05                                D046        72.848 us     05      11110     1         1         1         1         0         1         0         1         
75              D047      5D   memory read                  D047        73.832 us     5D      11110     1         1         1         1         0         1         0         1         
76              D04C      9D   STA $0500, x                 D04C        74.808 us     9D      11111     1         1         1         1         1         1         0         1         
77              D04D      00                                D04D        75.792 us     00      11110     1         1         1         1         0         1         0         1         
78              D04E      05                                D04E        76.776 us     05      11110     1         1         1         1         0         1         0         1         
79              0500      00   memory read                  0500        77.760 us     00      11110     1         1         1         1         0         1         0         1         
80              0500      00   memory write                 0500        78.744 us     00      01110     0         1         1         1         0         1         0         1         
81              D04F      DD   CMP $0500, x                 D04F        79.720 us     DD      11111     1         1         1         1         1         1         0         1         
82              D050      00                                D050        80.704 us     00      11110     1         1         1         1         0         1         0         1         
83              D051      05                                D051        81.688 us     05      11110     1         1         1         1         0         1         0         1         
84              0500      00   memory read                  0500        82.672 us     00      11110     1         1         1         1         0         1         0         1         
85              D052      F0   BEQ $D059  (+$05)            D052        83.656 us     F0      11111     1         1         1         1         1         1         0         1         
86              D053      05                                D053        84.640 us     05      11110     1         1         1         1         0         1         0         1         
87              D054      5D   memory read                  D054        85.616 us     5D      11110     1         1         1         1         0         1         0         1         
88              D059      9D   STA $0600, x                 D059        86.600 us     9D      11111     1         1         1         1         1         1         0         1         
89              D05A      00                                D05A        87.584 us     00      11110     1         1         1         1         0         1         0         1         
90              D05B      06                                D05B        88.568 us     06      11110     1         1         1         1         0         1         0         1         
91              0600      00   memory read                  0600        89.552 us     00      11110     1         1         1         1         0         1         0         1         
92              0600      00   memory write                 0600        90.528 us     00      01110     0         1         1         1         0         1         0         1         
93              D05C      DD   CMP $0600, x                 D05C        91.512 us     DD      11111     1         1         1         1         1         1         0         1         
94              D05D      00                                D05D        92.496 us     00      11110     1         1         1         1         0         1         0         1         
95              D05E      06                                D05E        93.480 us     06      11110     1         1         1         1         0         1         0         1         
96              0600      00   memory read                  0600        94.464 us     00      11110     1         1         1         1         0         1         0         1         
97              D05F      F0   BEQ $D066  (+$05)            D05F        95.440 us     F0      11111     1         1         1         1         1         1         0         1         
98              D060      05                                D060        96.424 us     05      11110     1         1         1         1         0         1         0         1         
99              D061      5D   memory read                  D061        97.408 us     5D      11110     1         1         1         1         0         1         0         1         
100             D066      9D   STA $0700, x                 D066        98.392 us     9D      11111     1         1         1         1         1         1         0         1         
101             D067      00                                D067        99.376 us     00      11110     1         1         1         1         0         1         0         1         
102             D068      07                                D068       100.360 us     07      11110     1         1         1         1         0         1         0         1         
103             0700      00   memory read                  0700       101.336 us     00      11110     1         1         1         1         0         1         0         1         
104             0700      00   memory write                 0700       102.320 us     00      01110     0         1         1         1         0         1         0         1         
105             D069      DD   CMP $0700, x                 D069       103.304 us     DD      11111     1         1         1         1         1         1         0         1         
106             D06A      00                                D06A       104.288 us     00      11110     1         1         1         1         0         1         0         1         
107             D06B      07                                D06B       105.272 us     07      11110     1         1         1         1         0         1         0         1         
108             0700      00   memory read                  0700       106.256 us     00      11110     1         1         1         1         0         1         0         1         
109             D06C      F0   BEQ $D073  (+$05)            D06C       107.232 us     F0      11111     1         1         1         1         1         1         0         1         
110             D06D      05                                D06D       108.216 us     05      11110     1         1         1         1         0         1         0         1         
111             D06E      5D   memory read                  D06E       109.200 us     5D      11110     1         1         1         1         0         1         0         1         
112             D073      E8   INX                          D073       110.184 us     E8      11111     1         1         1         1         1         1         0         1         
113             D074      D0   memory read                  D074       111.168 us     D0      11110     1         1         1         1         0         1         0         1         
114             D074      D0   BNE $D00B  (-$6B)            D074       112.144 us     D0      11111     1         1         1         1         1         1         0         1         
115             D075      95                                D075       113.128 us     95      11110     1         1         1         1         0         1         0         1         


The read from address following the branch instruction is interesting (eg line 27 above) - does the 6502 always read 3 bytes per instruction regardless or is this an IA artifact? I'll have a read of the datasheet plus the source.

Thanks again for fixing this though - makes it easier to follow the source

[Kean]

The read from address following the branch instruction is interesting (eg line 27 above) - does the 6502 always read 3 bytes per instruction regardless or is this an IA artifact? I'll have a read of the datasheet plus the source.

That would be instruction pre-fetch.  You should see it on all the branches.

[coppercone2]

I might try something on the 1660

[philpem]

... I can't believe that bug got out, but then again, I wrote this when I was in university ... at least ten years ago, probably more like fifteen.

Thanks for the fix. When I have a spare moment I'm going to try and get this into a Github repository... it looks like I may have lost my copy of the code, it's probably buried on a backup tape somewhere.

[MarkMLl]

I'm pleasantly surprised to see that this thread's still going :-)

I've got an HP1630G which I use when I need /lots/ of pins or decent speed.

I've written an HPIB printer simulator which works nicely, details at https://github.com/MarkMLl/hp2671 (and I make no apology for my choice of development tool).

I've also written a program, so far unpublished, which queries the analyser and generates a .vcd file.

Would anybody be interested if I continued by writing a general-purpose disassembler which took a .vcd as input?

I definitely don't promise a timescale, and users with other 1630 variants or other HPIB interfaces might need to tweak my .vcd generator... which shouldn't be too difficult, the code's intentionally naive.

MarkMLl

[deanclaxton]

I've just had my offer accepted on an Agilent 16902A selling here in Australia on eBay. I haven't received it yet, but it appears to be in excellent condition and includes 2 x 16750A's 16950A's and 3 E3582A Flying Lead sets.

I know these aren't the fastest (with a Pentium III etc), but there are a couple of upgrade paths available and to be honest I'll likely use it via remote desktop versus the local touch screen so hopefully it runs ok that way.

It's an upgrade to the HP 16602A I've been using to date, which I run via X11.

My plan is to try source some termination kits to suit these leads (90 pin?) and then build a new 65C02 adapter that will use the terminated connections rather than me having to go down the route of including the termination on the adapter like I did the last time.

Would anyone have any suitable termination adapters for the 16750A 16950A? 34 Channel?

Of course I need to check out the logic analyser first up and run self test on each of the 16750A's 16950A's and see what the boards are like - seems that corrosion under the stiffeners is very common.

Once it all checks out though, I'll be trying to get Phils 65C02 inverse assembler running on it to help with a new Apple ][ product I'm working on

EDIT : I just too another look at the listing and they are actually 16950A modules (not the 16750A's I thought) - bonus!

[MarkL]

I think you meant E5382A.  It was nice of the seller to include those with the unit.  A used E5382A can fetch a princely sum since they are still sold by Keysight for use with their current line of logic analyzers.  And because the 90-pin probing system is current, it unfortunately keeps all the 90-pin accessories significantly more expensive than the older 40-pin system.  (So, getting 90-pin cards was not necessarily a bonus!)

For 90-pin termination adapters, I would try looking for E5378A/E5378B (Samtec single-ended) or E5380A/E5380B (Mictor single-ended).  Both handle 32 channels of data and 2 clocks.  The Samtec adapter, for some reason, can be less expensive on the used market.  I have seen them for as low as US$25 ea., but not recently within the last year or so.

Good luck powering up the new unit!  Before you declare victory, I'd suggest testing each input to the probe tip.  I've experienced several bad E5382A probe sets where the center conductor on some of the data lines were severed, likely because someone pulled too hard on the cable.  This wouldn't show up on the self-test.  The 90-pin sets are a lot more delicate and more difficult to repair than the older 40-pin sets.

[deanclaxton]

 Ah yes- E5382A - 3 sets in the pouches. The one shown open in the eBay listing looks new/unused.

I guess the good thing is that I have slots available so if I see some 40 pin modules cheap, then I can slot them in

Current plan is to find 90 pin adapters though - probably just need one for now.

[deanclaxton]

So yeah - it looks like I need the E5378A probe set which mates to a Samtec ASP-65067-01 connector. Probing solutions datasheet here : https://www.keysight.com/gb/en/assets/7018-06707/data-sheets/5968-4632.pdf

[deanclaxton]

Ok so I've designed a 65C02 adapter for the Agilent E5378A probe set (Samtec).

I noted however that on these 90 pin analyzers, there are differential clock signals on each pod - CLKp and CLKn.

If I'm connecting to a single ended clock source, do I just use CLKp? And leave CLKn unconnected, or connect it to ground? On the 40 pin pods there was just the one CLK signal.

I should add that I havent actually received my analyzer yet, else I'd have tested this!


EDIT : Found this on page 53 of this manual https://www.artisantg.com/info/Agilent_E5378A_Manual.pdf :

Clock input
The clock input to the E5378A probe is differential. If you supply a differential clock, you should select the "differential" option in the clock threshold user interface.

If your system uses a single-ended clock signal, the CLKn input should be either grounded or connected to a dc power supply.

You may:

• Ground the CLKn input and adjust the clock threshold from the user interface to between -3V dc and +5V dc.
Or
• Supply a threshold reference voltage between -3V dc and +5V dc to the CLKn input. In this case, the clock threshold in the user interface should be set to zero.

If your circuit uses a resistive divider to provide a threshold reference, be sure to consider the equivalent circuit consisting of the 20k resistor connected to +0.75V
as shown on page 34 and 35.

The threshold for the clock input has a separate adjustment in the user interface, independent of the data inputs.

[MarkL]

Nice adapter!

You might need some mechanical support for the connector and/or analyzer cable.  The Samtec has a good friction fit, but it may not sufficiently resist the sideways force from the weight of the cable.  HPAK sold a "shroud" to help with this problem.

BTW, the analyzer side of the 90-pin cable uses the same 100-pin Samtec connector, if you want to get an idea for the tightness of the fit.

[deanclaxton]

Ok cool - I will check that out. I do have the mounting holes on the board for the shroud, but no idea where I'd get one. Perhaps eBay? I'll have a look.

[MarkL]

Keysight has them for sale on their Find-A-Part page for US$8.94, plus no doubt additional fees and shipping:

  https://www.keysight.com/us/en/ecom/parts/parts-number.html/16760-02302

Rather pricey for a piece of sheet metal, but not surprising for them.  Plus, they've been increasingly difficult to deal with if you're not a business.

I would try to buy it from them, and if unsuccessful, maybe a Keysight reseller will order it for you.  Or, if you're good with mechanical design, a 3-D printed shroud could be done.

[deanclaxton]

Gerbers attached for the 65C02 adapter, but I havent built/tested this yet. I'll update this post once I know its working ok - I'll slip in a few of these boards with my next order. This can be used with Phils inverse assembler (I'll have to get that running on the 16902).

The order of the STAT signals is correct for his inverse assembler. I designed and built a similar adapter for the 40 pin probes with all the termination parts on the adapter. This will be much faster to assemble!

[deanclaxton]

16902A arrived in one piece, which was pretty amazing given how it was packed  One small crack in the bezel unfortunately, but minor.

Otherwise the unit is in mint condition and the 3 x E5382A probe sets look unused.

I've ordered a E5378A from ebay so that I'll be able to build/use my adapter.

The analyzer was joined to a domain and the seller had no idea of the password, but I was able to use a recovery tool to reset it and log in.

I ran the self test on the 2 x 16950A cards and they both passed with no issues. I guess I should remove the glue under the stiffeners - assuming these cards would have used the same awful corrosive stuff - preventative maintenance?

TO DO :

• Upgrade the 16950A's to 64M aquisition memory (a software unlock) DONE
• Build the 65C02 adapter
• Get Phil's 6502 Inverse Assembler running on it

[MarkL]

Sounds like everything is in great shape!  I found the ebay listing and even the E5382A's look like they're perfect.  It's even more rare to find them with all the accessories.

I don't have any 169xx series chassis or cards, so I don't know if the corrosion issue was recognized and/or fixed at that point.  Maybe someone who has them can comment.

Failing that, you could look closely with a microscope around each runner for any signs of green fuzz.  If you see anything, pull them all off.  Here's a good page that Keith put together:

  https://www.techtravels.org/2019/12/corrosion-near-underneath-hp-logic-analyzer-module-plastic-runners/

I'll emphasize what's already on that page that heat is your friend.

I usually discourage knee-jerk prophylactic maintenance (like re-capping everything in sight), but in this case if it was me I'd pull all the runners off anyway.  Why wait to discover the hard way that HPAK didn't really address the problem yet.

Unlike Keith, I did not put the runners back on.

[deanclaxton]

Awesome - thanks I'll be sure to check the boards over this weekend. The E5382A's appear to be unused - all 3. Manuals are still shrinkwrapped, both for the analyzer and the probe kits. I found an additional cable inside the pouch which appears to be something to do with the Agilient N4220B PCI Express Packet Analysis Probe. I think it goes from the PCI Express slot to the N4220B unit. Seems the eBay seller is selling one. EDIT: Made an offer on it - probably never use it but who knows.

[deanclaxton]

Thanks to a very helpful forum member, the 2 x 16950A's are now upgraded to 64M! 

[ahakman]

A question probably mostly for gslick:

Could you compile all of the available inverse assemblers with the DLL wrapper for the 169xx series analyzers if you still have the environment setup to do so? It sounds like setting up that environment is quite the chore.

I'm working on getting my 16903A up and going, and would really appreciate the dll wrapped inverse assemblers for it.
I've repaired the 2 cards I have that are compatible with the 169xx series analyzers, and I'm just waiting on the appropriate probe cables to arrive for those cards.

I'm especially interested in an IA for 68020

[gslick]

I've been meaning to build all of the common INVASM.ZIP collection of 10391B inverse assemblers into DLL versions which can be used with the 1680/1690/16800/16900 series of Windows 2000/XP/WES7 based analyzers. I should be able to get around to doing that soon.

I also need to write up notes with all of the details on how to get set up to do that yourself. I already have a good set of notes, just need to polish them up. It's not too difficult, just a bit of a chore and time consuming, as you suggest.

[ahakman]

Yes, the instructions on how to compile them wrapped in a DLL would be handy too. I read back in the thread and you mentioned you need a specific version of VisualStudio, and that probably has to run on 32 bit WindowsXP.

I happen to have a clean virtual box image of a fresh install of 32 bit WindowsXP, and I could certainly start from there.

[deanclaxton]

With enormous thanks to gslick, I was able to set up the build environment, compile the 6502.S to 6502.R and then build the .dll and installation files for it.

I've installed it, but havent actually given it a proper test yet. I'll test it out then share the installation files for anyone else who may wish to use the 65C02 IA on a 169xx logic analyzer 

[gslick]

Yes, the instructions on how to compile them wrapped in a DLL would be handy too. I read back in the thread and you mentioned you need a specific version of VisualStudio, and that probably has to run on 32 bit WindowsXP.

I happen to have a clean virtual box image of a fresh install of 32 bit WindowsXP, and I could certainly start from there.

If you already have a Windows 2000 or Windows XP VM set up, you can download iso images of the tools you need to install from here:

Microsoft Visual Studio .NET 2003 Enterprise Architect, Disc 1
https://archive.org/details/X09-46214

Microsoft Visual Studio .NET 2003 Enterprise Architect, Disc 2
https://archive.org/details/X09-46216

Microsoft Visual Studio .NET 2003 Enterprise Architect Enterprise Developer Windows Prerequisites
https://archive.org/details/X09-46245

Logic and Protocol Analyzer Software (32-bit)
https://www.keysight.com/us/en/lib/software-detail/instrument-firmware-software/logic-and-protocol-analyzer-software-32bit-2222812.html
Previous Versions
Release Date    Version     Version Description
2007-09-21      03.67.1008   16900, 16800, and 1680/90 Series Application Software (Version 03.67.1008)
Application Software CD (.iso Image, Version 03.67)
Operating System
Windows XP SP2
Windows 2000


The logic analyzer application software after Version 03.67 dropped support for building 10391B style inverse assemblers into dlls using the Analysis Add In Wizard, maybe partially because as-is it was not compatible with versions of Visual Studio after 2003, and they might not have wanted to put the effort into updating the Analysis Add In Wizard for newer versions of Visual Studio.

Only the C++ compiler component of Visual Studio 2003 needs to be installed. All of the other components can be unselected during installation.

[ahakman]

Thank you gslick!

I've downloaded the isos - I will work on getting that stuff installed into my XP VM soon and see if i can get the 68020 IA built

[ahakman]

Ok, so in my XP VM, I installed visual studio and the 3.67.1008 version of the LA software. I also installed SetupIAAnalysisAddInWizard from the LA CD, and followed the instructions in the readme in the docs folder where that installed to and copied the 3 files into the visual studio folder, but now I'm a bit stumped... what to do from here?

I don't see the Analysis Add In Wizard showing up in the LA software anywhere? Normally I'd just keep playing with this and reading the manuals to figure it out, but I really need to go to bed!

Oh, I see, you use it through visual studio, and you load in a .R file (which I have to figure out how to make). Definitely need to look more at this tomorrow after work

Also, daaaaamn, windows XP runs incredibly fast in a VM on modern hardware! Definitely something to be said for old windows before they were full of useless cruft and spyware!

[gslick]

Ok, so in my XP VM, I installed visual studio and the 3.67.1008 version of the LA software. I also installed SetupIAAnalysisAddInWizard from the LA CD, and followed the instructions in the readme in the docs folder where that installed to and copied the 3 files into the visual studio folder, but now I'm a bit stumped... what to do from here?

I don't see the Analysis Add In Wizard showing up in the LA software anywhere? Normally I'd just keep playing with this and reading the manuals to figure it out, but I really need to go to bed!

Oh, I see, you use it through visual studio, and you load in a .R file (which I have to figure out how to make). Definitely need to look more at this tomorrow after work

Yes, after installing Visual Studio 2003, then installing version 3.67.1008 of the LA software, and then separately installing version 3.60.0002 of the Analysis AddIn IA Wizard from the 3.67.1008 CD, you need to manually do this step, as you already discovered:

C:\Program Files\Agilent Technologies\Logic Development\Analysis AddIn Wizard\docs\Readme.txt:

To complete the installation of the wizard please copy the three files listed below from:
C:\Program Files\Agilent Technologies\Logic Development\Analysis AddIn Wizard

AgilentAnalysisWizard.ico
AgilentAnalysisWizard.vsdir
AgilentAnalysisWizard.vsz

to:
C:\Program Files\Microsoft Visual Studio .NET 2003\Vc7\vcprojects\

And then after doing that, the next time you start Visual Studio and create a new project, when you select Visual C++ Projects as the Project Type, one of the Template choices should now include Agilent Analysis Tool.




For the common INVASM set of inverse assemblers, there is a set of those with the .R files extracted from the inverse assemblers. See invasm_v3.zip attached to reply #19 of this thread.

[gslick]

If you have an .S source file for a 10391B style inverse assembler and you want to assemble that into an .R file, you need to install the 10391B assembler. This tool runs in a 16-bit DOS environment. You can't run it in the command prompt windows of newer versions of Windows, which lack a 16-bit environment. You should be able to run it fine in a command prompt windows of a Windows 2000 or Windows XP VM.

You can currently download the 10391B assembler here:

https://www.keysight.com/us/en/lib/software-detail/instrument-firmware-software/10391b-inverse-assembler-development-package-version-0200-sw575.html

https://www.keysight.com/us/en/assets/9018-01037/reference-guides/9018-01037.pdf

Here are some detailed notes below on how it can be installed. In the example below the X: drive is a shared network folder mapped from the the guest VM to a directory on the host VM, where the IA_Development_Disk directory was extracted from the downloaded 10391B zip file.

The INSTALL.BAT file was originally set up to install from the A: floppy drive. Instead of running INSTALL.BAT the files can be manually copied. Note that the AIAL.txt files should not have the .txt extension. Those files must be renamed to remove the .txt extension. Also note that the AIAL file must either be copied to the default location of C:\HP64700\TABLES\AIAL, or the HPTABLES environment variable must be set to the directory containing the AIAL file. If you don't do that, you will get the error "asm: Termination, Unimplemented or invalid processor name (line     0)"

Code: [Select]

C:\>md 10391B

C:\>xcopy /s X:\IA_Development_Disk 10391B
X:\IA_Development_Disk\ASM.EXE
X:\IA_Development_Disk\IALDOWN.EXE
X:\IA_Development_Disk\INSTALL.BAT
X:\IA_Development_Disk\64700\TABLES\AIAL.txt
X:\IA_Development_Disk\EXAMPLES\68010.BAT
X:\IA_Development_Disk\EXAMPLES\68010.CMD
X:\IA_Development_Disk\EXAMPLES\8085.BAT
X:\IA_Development_Disk\EXAMPLES\8085.CMD
X:\IA_Development_Disk\EXAMPLES\I68010.S
X:\IA_Development_Disk\EXAMPLES\I8085.S
X:\IA_Development_Disk\PROGRAMS\ASM.EXE
X:\IA_Development_Disk\PROGRAMS\IALDOWN.EXE
X:\IA_Development_Disk\TABLES\AIAL.txt
13 File(s) copied


C:\10391B>dir /s /b /a-d
C:\10391B\ASM.EXE
C:\10391B\IALDOWN.EXE
C:\10391B\INSTALL.BAT
C:\10391B\64700\TABLES\AIAL.txt
C:\10391B\EXAMPLES\68010.BAT
C:\10391B\EXAMPLES\68010.CMD
C:\10391B\EXAMPLES\8085.BAT
C:\10391B\EXAMPLES\8085.CMD
C:\10391B\EXAMPLES\I68010.S
C:\10391B\EXAMPLES\I8085.S
C:\10391B\PROGRAMS\ASM.EXE
C:\10391B\PROGRAMS\IALDOWN.EXE
C:\10391B\TABLES\AIAL.txt

C:\10391B>ren C:\10391B\64700\TABLES\AIAL.txt AIAL

C:\10391B>ren C:\10391B\TABLES\AIAL.txt AIAL

C:\10391B>dir /s /b /a-d
C:\10391B\ASM.EXE
C:\10391B\IALDOWN.EXE
C:\10391B\INSTALL.BAT
C:\10391B\64700\TABLES\AIAL
C:\10391B\EXAMPLES\68010.BAT
C:\10391B\EXAMPLES\68010.CMD
C:\10391B\EXAMPLES\8085.BAT
C:\10391B\EXAMPLES\8085.CMD
C:\10391B\EXAMPLES\I68010.S
C:\10391B\EXAMPLES\I8085.S
C:\10391B\PROGRAMS\ASM.EXE
C:\10391B\PROGRAMS\IALDOWN.EXE
C:\10391B\TABLES\AIAL



C:\10391B>CD EXAMPLES

C:\10391B\EXAMPLES>..\ASM I8085.S
asm: Termination, Unimplemented or invalid processor name (line     0)

C:\10391B\EXAMPLES>CD ..

C:\10391B>MD C:\HP64700

C:\10391B>XCOPY /S 64700 C:\HP64700
64700\TABLES\AIAL
1 File(s) copied

C:\10391B\EXAMPLES>DIR /S /B /A-D C:\HP64700
C:\HP64700\TABLES\AIAL

C:\10391B>CD EXAMPLES

C:\10391B\EXAMPLES>..\ASM I8085.S

C:\10391B\EXAMPLES>RD /S /Q C:\HP64700

C:\10391B\EXAMPLES>..\ASM I8085.S
asm: Termination, Unimplemented or invalid processor name (line     0)

C:\10391B\EXAMPLES>SET HPTABLES=C:\10391B\64700\TABLES\

C:\10391B\EXAMPLES>..\ASM I8085.S

C:\10391B\EXAMPLES>..\ASM /OX I8085.S > I8085.LST


[ahakman]

Thank You! I had the 10391B inverse assembler development package downloaded, but not installed yet. I think I could've figured it out from going back and reading some posts in this thread again, but as I said, it was late (like 3AM) and I had to get up for a mandatory statistics training course at 8:30 for work this morning (which taught me no statistics I didn't already know  ).

The only other thing I noticed is that the 68020 IA has a _i at the end of it's name indicating it needs special probing hardware. I found the manual for the E2426B 68020 probe shim from HP, and it looks like there's nothing special on the board other than 90k resistors in series with each of the signal lines, and a jumper to pull the cache disable pin on the processor low to disable the cache so you get a full code trace from the bus.
https://nscainc.com/wp-content/uploads/pdf/A_E2426B.pdf

That manual also mentions that there are 2 different IAs for 68020, the "regular" and the "enhanced". It says it used one vs the other depending on the version of software on the logic analyzer itself. I'm guessing the IA that's in the package here is the "enhanced" one?? Keysight has no files available for the E2426A / B probe on their site (of course)

[ahakman]

Ok, I got it built. I'm just installing the 5.90 version of the logic analyzer software in my VM to see if I can install the addin.

You really have to follow the directions in the manual very carefully. I was trying to figure out why I kept getting a bunch of path errors during the build, and was manually adding folders to the include path in visual studio, but then it got to a header file that just didn't exist, and I was like "WTF???"

Then I read the manual closer - open VS, create the project using the wizard (being sure to visit ALL 3 pages of the wizard), close VS, delete the project file, swap in the other project file, re-open VS, THEN Build. Just a slightly kludgy workaround they had there... ahhh, windows in the 90's / early 2000's - brings back not fond memories...

[gslick]

Ok, I got it built. I'm just installing the 5.90 version of the logic analyzer software in my VM to see if I can install the addin.

You really have to follow the directions in the manual very carefully. I was trying to figure out why I kept getting a bunch of path errors during the build, and was manually adding folders to the include path in visual studio, but then it got to a header file that just didn't exist, and I was like "WTF???"

Then I read the manual closer - open VS, create the project using the wizard (being sure to visit ALL 3 pages of the wizard), close VS, delete the project file, swap in the other project file, re-open VS, THEN Build. Just a slightly kludgy workaround they had there... ahhh, windows in the 90's / early 2000's - brings back not fond memories...

Yeah, a couple of other details I didn't mention yet:

First, before you use Visual Studio to create the first IAL wizard project, you need to modify this file:

C:\Program Files\Agilent Technologies\Logic Development\Analysis AddIn Wizard\wizard-files\Templates\1033\AnalysisAddIn_vcproj.txt

There are two lines in that file:

Code: [Select]

AdditionalDependencies="agAnalysisAddIn_i.idl;agAnalysisAddIn2_i.idl;"

Change both of those lines to:

Code: [Select]

AdditionalDependencies="agAnalysisAddIn_i.idl;agAnalysisAddIn2_i.idl;agAnalysisAddIn3_i.idl;"

It appears that there may be errors building an IAL wizard project if those changes are not made before using the wizard to create a new project.

And second, each time you use Visual Studio to create a new IAL wizard project, the newly created project directory should contain a .vcproj file, and a .vcproj.replace file. As the file name suggests, first close the new project, replace the .vcproj file with the .vcproj.replace file, and then reopen the new project. If you forget to do that the project will fail to build with the original .vcproj file.


After you successfully build an IAL wizard project dll, inside the project directory the IA wizard scripts should have created a directory with a create.bat file. That's what you run to create the installation directory. It will copy the IA dll to an installation directory that you specify by defining the shell variable ANALYSIS_DIRECTORY. It will also copy to that directory install.bat and uninstall.bat files, some .reg registry addition files, and RegisterAddIn.exe and UnregisterAddIn.exe utilities used by the install.bat and uninstall.bat files.

To actually install the IA dll you would run the install.bat file from the installation directory created by running the create.bat file.

As-is, the generated .reg registry addition files only work when the logic analyzer application is installed on a 32-bit version of Windows. They can be modified to work when the logic analyzer application is installed on a 64-bit version of Windows.

[ahakman]

Yes, when I was mucking around trying to install the LA suite 5.90.whatever, I had tons of issues, and ended up really borking up my VM image - good thing it's a VM image, and it was just a copy of a good image!

I did all of what you mentioned, except adding in the agAnalysisAddIn3_i.idl; dependency to the AnalysisAddIn_vcproj.txt file. The DLL still seemed to build fine.

I also figured out all the stuff about how to make the install directory from reading the batch files themselves. I copied the directory to the 16903A on a usb stick and ran the intall.bat file, and now it actually shows up in the tools menu (and my actual logic analyzer is running version 4.00.[whatever].

Now I have 2 questions:
Is is there a quick way to import the bus / pod assignments? If I try to add the IA analyzer, I get an error message saying (shortened / paraphrased) "The analysis tool has requested signal ADDR as input, but that signal isn't defined". I could define the bus layouts to the pods manually, but isn't there a way to do that automatically from some of the files in the .zip files at the beginning of this thread? It doesn't seem to like to import either the txt version of the config, or the .p binary version of the config. It's not that big of a deal - it took 2 minutes to define the buses by hand using the .txt version of the config from the zip file

The 68020 IA has 5 pods worth of signals defined. ADDR = 2 pods, DATA = 2 PODS, STAT = 1 POD. I have 2 cards that are 4 pods each, so the first card is entirely the address and data buses (as they're 32 bits each), and then the STAT bus needs to be on the first pod of the second card. So currently I have the cards independent of eachother, but with it setup that way, I can't assign signals or buses from more than one card to the IA at the same time. Is there a way to do this? Or is the only way to link the cards together with the linking cables into one larger analyzer? I would expect that I could just clock both cards from the same clock, and use them in state mode as if they're one larger card, even if they're not linked with the joiner cables, and then assign buses from pods on both cards into the signals the IA is looking for. Is this not the case??

[MarkL]

Unless you're trying to analyze two independent domains, the cards are supposed to be linked together.  This allows multiple cards to operate as one seemless unit, and it takes care of clocking, skew, pattern matching, and triggering across all the inputs.

I think you said in a previous post you had two 16752A cards.  You would need two flat-flex jumpers to combine the two cards.  If you don't have them, you can buy them as a set 16715-60001, or individually as 16715-61603.  There's a pair on ebay right now for $10 + shipping.

[ahakman]

On the 2 cards I repaired, I would have to replace the sockets on the cards for the linking cables as well - they're pretty cruddy looking and corroded.

Anyone know what the connector is on the board side so I could order new ones?

Would you trust these to work? I don't think I would... the only one that is maybe ok is card2 connector 2. The rest look pretty awful

Oddly enough I have 2 more cards here temporarily that are also broken and corroded very badly under the runners, but the linking connectors are perfect on those. Unfortunately those cards will be going back because they were sold as "Used (aka functional)" on ebay, both fail the self tests, and the seller seems to think his broken junk is worth more than I'm willing to pay for the privilege of spending hours under the microscope fixing them.

These things really are a PAIN at every step of the way...

[MarkL]

Those are not in great shape, but I've had worse.  I wouldn't plug anything into them the way they are.  You might ruin the connector on the flat-flex cable.

I would try using a soft bristle brush saturated in IPA (like a toothbrush), and try to gently scrub the green corrosion off the fingers.

If that doesn't work, and I know some people are going to hate this suggestion, you could try a very fine bristle brass brush.  I have had to resort to this in a few cases, but in my view it was a doomed connector anyway, so what did I have to lose.  I recall one connector where it was so bad I had to scrape the corrosion off with a needle finger by finger.  I made a mess of the gold plating, but it did work afterwards.

I've found the connectors on the top side of the board are usually in much better shape.  If you're good at SMD soldering, and you have good connectors on the top, you could try transplanting a pair to the bottom on one of the boards.  You have 8 connectors to work with, and you only need four to get a pair of boards connected (two on the top, and two on the bottom).

I will look around to see if I can figure out the manufacturer, but there are no identifying logos or other tell-tale marks.  The only thing I see is "RN 004" on the flat-flex side.  I seem to recall a connector manufacturer with the initials "RN" long ago, but I can't recall who it was.  But it's not clear that's even the manufacturer.

[ahakman]

I ended up doing exactly what you suggested - I spent a couple of hours this afternoon looking at board to board connectors at Digikey and Mouser and couldn't find a match, so it was on to plan B:

I spent at least a couple of hours under the microscope scraping each individual pin in the 2 connectors on the bottom side of one card with a sewing pin, and a very fine tipped "grinding pen" (if you watch Northridge Fix on youtube, you know what I'm talking about) bit just by hand. I also finished up by running a spatula with printer paper wrapped around it as a final "polish" back and forth in the central slot of the connector. That's a trick I learned many years ago - printer paper is just abrasive enough to use for cleaning up contacts without damaging any of the metal of the connector. Also used the pin and some cotton from a cotton bud and acetone to soak up all the mess, and some compressed air to blow out what was left.

First time I ran the cards together, I had 2 failing self tests, inter-chip resource bus and one of the clocking tests both failing on the slave board. Took it apart again and did a little more scraping, polishing with the printer paper on the spatula, and cleaning again with compressed air, and on the second try, it's working!

I did also use a tiny dremel sized brass brush too - again, by hand, not in any tool that would spin it, and I tried cleaning the contacts on the bottom connectors of the other board without doing any scraping first - it definitely didn't get some of the bigger "chunky" stuff off, but it looks quite a bit better. Scraping each pin individually is definitely the way to go. If I get some more boards in the future and need to use the bottom connectors on that board, I'll have to do some more manual scrapey-scrapey under the microscope to get those contacts in good shape.

All in all, the plating doesn't look perfect anymore, but it is working.

What an absolute journey it's been to get to this!



2 Cards linked together into one "analyzer", the IA compiled and inserted, and actually seeing all of the defined buses now! And 2 sets of the cables I bought showed up today too, so I'm technically ready to run this! Now I need to get the target system ready - that's a bit of a project in and of itself. Tomorrow - I'm way too tired today.

[MarkL]

Great - glad you got everything working!  Popping the stack...

Thanks for the ref on the "grinding pen".  Looks like a useful tool.   I'll have to grab one of those.

[ahakman]

On the Grinding Pen, the one Northridge sells you can find for about half price on Ali Express (of course).
I bought one from Ebay that looked like the same thing but with a different set of bits - I don't think it's the same thing at all. The bits in the ebay one seem considerably worse than the bits in the Northridge / Ali Express one.

I'm waiting on the Ali Express one to actually arrive to be able to compare it to the ebay one.

The bits from the ebay one did come in handy for this little job though...

If you want the good one and you want it reasonably quickly, just support Northridge Fix and buy it from him!

[MarkL]

...
If you want the good one and you want it reasonably quickly, just support Northridge Fix and buy it from him!

I'm going to do that.  There were a few other things in his store of interest, not to mention a nice metal bristle brush for "Circuit boards and corrosion removal".  Just what was needed!

Also, the name of the company with the RN logo (remembering from decades ago printed on wire-wrap IC sockets) was Robinson Nugent.  They are now owned by 3M, and inherited the 0.8mm connectors which are used on the analyzer boards for the interconnects.  See Pak 8 Plug Connectors and Pak 8 Socket Connectors here:

  https://www.3m.com/3M/en_US/p/c/electronics-components/interconnect-products/pcb-connectors/boardmount/i/electronics/

Or, go directly here for the sockets that are on the board:

  https://www.3m.com/3M/en_US/p/d/b30000132/

The part number looks like it would be P08-080-SLxx-A-G, where the xx depends on packaging and vacuum pickup options (see datasheet).  Quest Components has 92 available for US$5.70/ea according to octopart.com.  I've never ordered from them, so I don't know how well they cope with small orders.

Just posting the info in case anyone is ever looking for these again.

[ahakman]

Wow, amazing, you found the right connectors!

You have to be careful though, the one that Quest has for $5.70 each are P08-080-SL??-B-G - the B model is 3mm higher!
At Quest the P08-080-SL??-A that they have in stock is $38 ea.!!!! YIKES

[MarkL]

...
You have to be careful though, the one that Quest has for $5.70 each are P08-080-SL??-B-G - the B model is 3mm higher!
At Quest the P08-080-SL??-A that they have in stock is $38 ea.!!!! YIKES

Oops - thanks for noticing that on the quest listing!

An extra 3mm might be tolerated for the connectors on the top of the board, but that's not usually the ones needed.  If replacement is the only option, it might be better to look for a junked card to salvage a pair of connectors than pay $38 ea (ouch!).  16715A cards have the least capabilities in this family, and can show up fairly cheap as parts mules for the connectors and other parts in common like the comparators.

[AndersG]

On this topic, has anyone ever seen the HP1000 inverse assembler files? They seem to have existed, but apparently never released as a product and had no product number. You just had to ask for them nicely... I have some IAs for my 1631D, but they seem to be the ones that are floating around here, ie 8080, 68000 anf HPIB.

[cmax100000]

Does anyone have a learn string output from a HP 1630a with the inverse assembler loaded?  I have been looking at the configuration output from my LA and I wondered if I loaded a configuration output from another machine would work as if the IA were loaded in through the GPIB.

Thanks in advance.
I didn't see anything on GitHub. 

[AndersG]

You can load them that way. JJust flip a byte in the file. See http://www.dalton.ax/hp1631d/

If that does not work, then I can load an IA, but which one? and dump the learn string.

[cmax100000]

I looked at the info in that link and it is close to what I am looking for as I can see the "RC" in a couple of the files from the screen shots.  If I had to pick an IA I would like, 6809 or any of the 6800 series as I am familiar with Motorola assembly in that series.  In the absence of that, any IA will do for what I am trying to find out as it is the configuration learn string that I am messing around with.  It seems like the 1630 could be set up by hand if you had enough patience and experience.
Any help on this is greatly appreciated.

[AndersG]

OK. Did you notice the tool i built, for uploading and downloading screenshots? See a bit down on page: http://www.dalton.ax/gpib/

[cmax100000]

I didn't see that in the first one but I have now downloaded it and looked at it.  I have a very old setup using a 486 computer running DOS and VBDOS and the utility looks windows based.  All of my gpib access is done through VBDOS.  I have been able to read the learn strings to the computer and break them down somewhat into pods, polarities, clocks, state and timing channels, etc.  As I was doing this and reading the IA posts about the difficulty in getting original files read from a hp gpib drive loaded into a 1630 machine, I thought that maybe the machine was just being set up a certain way which would be readable, savable, and writable as a learn string configuration file.  I was hoping someone on the forum would have a learn string configuration file output from any loaded inverse assembler on a 1630X machine so that I could look and see exactly what settings were being modified so that the assembly language(or machine language) states were captured.  In a perfect world it would be on a 1630D or lower machine as I have byte by byte comparison code that shows the differences between two learn strings.
Hopefully, someone might have something close.
Thanks in advance

[ahakman]

Is the Agilent Logic Analysis Software 4.00.1006 cd / dvd image available anywhere? Keysight only has ver 3.67.1008 and 5.90.1110 ISOs available on their site.

5.90 is a PIA in many ways, and lots of people report it is much slower than ver 4 was.

My actual LA has 4.00.1006 on it, and I'd like to be able to install the same version on another box to look at the files offline without the LA (and it's annoying fans) running.

I have 3.67.1008 installed on a virtual machine that I was able to use to compile some IA's for my actual machine on, but if I open the save files from 4.00.1006 in 3.67.1008 on the virtual machine, it just crashes when it's opening the file.

Also if I export a CSV in 4.00 and try to import it into 3.67 (which you'd think would get around the problem of the binary file format), 3.67 complains about there being no license for import, and only imports the first few rows. WTF kind of stupidity is a "license for data import"?

[MarkMLl]

I didn't see that in the first one but I have now downloaded it and looked at it.  I have a very old setup using a 486 computer running DOS and VBDOS and the utility looks windows based.  All of my gpib access is done through VBDOS.  I have been able to read the learn strings to the computer and break them down somewhat into pods, polarities, clocks, state and timing channels, etc.  As I was doing this and reading the IA posts about the difficulty in getting original files read from a hp gpib drive loaded into a 1630 machine, I thought that maybe the machine was just being set up a certain way which would be readable, savable, and writable as a learn string configuration file.  I was hoping someone on the forum would have a learn string configuration file output from any loaded inverse assembler on a 1630X machine so that I could look and see exactly what settings were being modified so that the assembly language(or machine language) states were captured.  In a perfect world it would be on a 1630D or lower machine as I have byte by byte comparison code that shows the differences between two learn strings.
Hopefully, someone might have something close.
Thanks in advance

I've got code- so far unpublished- which uses a cheap GPIB interface to capture the state of an HP1630G to a .vcd file.

MarkMLl

[AndersG]

FWIW are the formats of the various 163X files documented in the programming manual.

[gotcha]

Hello,

I recently got a HP 1650A and HP 16500B. Currently, I'm focusing on the HP 1650A.

My initial target is to use an inverse assembler for the Z80.
I found various files, floppy disk images, but I'm still a bit confused.
For example, I found a Z80 related floppy for the 1650A here (http://www.bitsavers.org/bits/HP/1650/hp_1650), but it doesn't tell if it's for working with a preprocessor interface or not, and the details of STAT.

In my particular case, I don't have any preprocessor interface for the Z80 (that as far as I understood, processes the control signal from the Z80).
I just have standard flying probes.

Is there a config file and a IA file I can use for this case ? Also, which pins should I use for STAT ?

[MarkMLl]

FWIW are the formats of the various 163X files documented in the programming manual.

Yes, to the extent that you can extract enough configuration information to convert the file into e.g. a VCD. I've not, however, attempted to restore a configuration to an instrument.

MarkMLl

[gslick]

In my particular case, I don't have any preprocessor interface for the Z80 (that as far as I understood, processes the control signal from the Z80).
I just have standard flying probes.

Is there a config file and a IA file I can use for this case ? Also, which pins should I use for STAT ?

As mentioned here in this other thread, the original Z80 IA won't work correctly without the Z80 preprocessor:

https://www.eevblog.com/forum/testgear/older-logic-analyzer-question/msg4872758/#msg4872758

[gslick]

There were some posts in a different forum which referred to this thread with questions about building a 10391B style inverse assembler into a 32-bit x86 DLL version of the inverse assembler using the version 03.60.0002 of the IAAnalysisAddInWizard from the 03.67.1008 version of the LA software CD-ROM.

One question was whether such a 32-bit x86 DLL version of the inverse assembler was also compatible with the newer version 05.90.1104 of the logic analyzer application. The answer to that question is yes. Such an inverse assembler can be loaded on the newer version 05.90.1104 of the logic analyzer application, when the logic analyzer application is loaded on either 32-bit or 64-bit versions of Windows.

The screenshot below shows the 32-bit x86 DLL version of the inverse assembler built from the i6800_p.r contained in the invasm_v3.zip file in the first post of this thread loaded in the 05.90.1104 version of the logic analyzer application running on the 32-bit version of Windows XP. I was also able to load it in the 05.90.1104 version of the logic analyzer application running on the 64-bit version of Windows 10.

I could post the 32-bit x86 DLL version of the i6800_p inverse assembler files here if anyone want those.

[Hamster]

i would be interested, i guess i need to build a virtual machine so i can build the z80, 6809, 68000 dlls. ( i sourced a 6809 interface )

thanks for sharing!

[gslick]

i would be interested, i guess i need to build a virtual machine so i can build the z80, 6809, 68000 dlls. ( i sourced a 6809 interface )

thanks for sharing!

Attached is the 32-bit x86 DLL version of the i6800_p inverse assembler file that I built using the version 03.60.0002 of the IAAnalysisAddInWizard from the 03.67.1008 version of the LA software CD-ROM.

There is a 32-bit install directory and a 64-bit install directory. The contents of the 32-bit install directory is what is created by running the create.bat file in the build directory of the IA DLL after the IA DLL is built.

The copies of the files in the 64-bit install directory are exactly the same as the files in the 32-bit install directory, except that in the 64-bit install directory the Install.bat and Uninstall.bat files were edited be me to replace all instances of "Program Files" with "Program Files (x86)", and in the 64-bit install directory the ialAnalysisAddInIAL6800_P.reg file was edited by me to replace all instances of "HKEY_CLASSES_ROOT" with "HKEY_CLASSES_ROOT\Wow6432Node".

You probably need to run Install.bat as Administrator to copy the IA DLL to the "Program Files" or "Program Files (x86)", and add the settings to the registry. After running either the 32-bit or 64-bit Install.bat, as appropriate, to install the IA DLL, the sample configuration file IAL6800_P-16911A.xml that I created could be loaded into the logic analyzer application to set up the appropriate bus signal labels.

If anyone gives this a try with a 6800 or 6802, let me know if it works for you.

Since I'm already setup to build these IA DLLs, I could probably go ahead and build Z80, 6809, 68000 DLLs for you. Do you have preprocessor interfaces for all of those?

[Hamster]

I do have the following Interface Modules:
Z80,8086/8088,6809,68000,Z8001,80386
Currently looking for a 6800/02

I could use the 6502 file as well ( this one doesn't use a Interface Module )

I did test your 64 bit install, couple steps needed to be added:

1) Open a Command Window in Administrator Mode.
2) Change to directory
3) Run Install.

[Hamster]

WooHoo!

Ok, that was a pita to make the 64 bit install files!

gslick, thanks for the tips.. Now to test.

it will be nice to use my bench top 1690D and can retire these old 167X units.

[Hamster]

FYI, it if wasn't for your example 6800 install, i probably would of never figured it out.. 

[gslick]

WooHoo!

Ok, that was a pita to make the 64 bit install files!

gslick, thanks for the tips.. Now to test.

it will be nice to use my bench top 1690D and can retire these old 167X units.

Were you able to get the IA DLL build without making any changes to the AnalysisAddIn_vcproj file? When I have tried this a few times with the original AnalysisAddIn_vcproj file (the generated one that you rename to replace the other generated AnalysisAddIn_vcproj file) I have gotten build errors related to agAnalysisAddIn3_i.idl

I have had to add agAnalysisAddIn3_i.idl; to the end of the AdditionalDependencies="agAnalysisAddIn_i.idl;agAnalysisAddIn2_i.idl;" lines to resolve that.

I think someone else here said that the didn't have to do that and didn't get the agAnalysisAddIn3_i.idl errors. I'm not sure what might be going on there.


What host system are you using for the 1690AD? I forget if you can use anything beyond Windows 7 to get the correct 1394 host controller driver loaded. I also forget if it works with both 32-bit and 64-bit versions of Windows 7. A 1690AD with a small and fast somewhat modern PC can be a much better solution than an equivalent slow Windows XP based 1680AD with a small LCD, unless you really need a completely portable all in one analyzer.

[Hamster]

Yes, I had to add agAnalysisAddIn3_i.idl; to the proj file.

On the 1690D:

Windows 10 Pro, 64bit , You need to install the compatibility mode drivers on the 1394 card.

I am pretty sure i am running a PCIe card as well, but need to look in the computer to check.

https://www.startech.com/en-us/faq/firewire-cards-windows-legacy-driver-swap

[Hamster]

i also converted all my 1680D frames to win7 machines core2duo.. super fast and portable

[gslick]

Yes, I had to add agAnalysisAddIn3_i.idl; to the proj file.

On the 1690D:

Windows 10 Pro, 64bit , You need to install the compatibility mode drivers on the 1394 card.

Thanks for confirming that you were also seeing the agAnalysisAddIn3_i.idl issue that required a modification of the project file. I wasn't sure if I might have messed up and skipped something in the installation the would have normally prevented that.

Also thanks for confirming that you were able to get your 1690AD working with a Windows 10 host. I'll have to try that myself the next time I get out my 1690AD. I have Dell SFF PC that would make a good Windows 10 host for that.

----------

If anyone is looking for HP preprocessors that attach to 10269 interfaces, this seller on eBay currently has a few listed, although a close look at all of the listing photos is necessary as some of the DIP / PGA target probes are in bad condition. Normally there are a couple of layers of machine pin DIP / PGA sockets on the target probes, so if only the outermost layer has broken pins, the socket layers below the outermost one might be fine and the outmost socket could be removed and replaced.

HP HEWLETT PACKARD 64675 Interface Modules A and B for 68020 Microprocessors
https://www.ebay.com/itm/256411931727

HP HEWLETT PACKARD 10314D Interface Module for 80386 Microprocessors
https://www.ebay.com/itm/256411931693

HP HEWLETT PACKARD 64680A Interface Module for Z8001 Microprocessors
https://www.ebay.com/itm/256410735436

HP HEWLETT PACKARD 64657B Interface Module for 80286 Microprocessors
https://www.ebay.com/itm/266671416022

HP HEWLETT PACKARD E2409A Interface Module for 80286 Microprocessors
https://www.ebay.com/itm/266671415923

HP HEWLETT PACKARD 64670A Interface Module for 68000 Microprocessors
https://www.ebay.com/itm/266671415821

HP HEWLETT PACKARD 64681A Interface Module for Z8002 Microprocessors
https://www.ebay.com/itm/266663873168

HP HEWLETT PACKARD 64658A Interface Module for 80186/80188 Microprocessors
https://www.ebay.com/itm/256405092893

HP HEWLETT PACKARD 64673A Interface Module for 68008 Microprocessors
https://www.ebay.com/itm/266659715690

HP HEWLETT PACKARD 10314B Interface Module for 80386 Microprocessors
https://www.ebay.com/itm/256403930507

HP HEWLETT PACKARD 64655A Interface Module for 8085 Microprocessors
https://www.ebay.com/itm/266659714425

HP HEWLETT PACKARD 10343B SCSI Bus Preprocessor
https://www.ebay.com/itm/256406266462

[Hamster]

So, now need to make a nice cheat sheet for pod assignments on the 10269C

cXXXXX_p.txt will indicate the ADDR/DATA assignments, but not which pod goes where.

ie, what are POD1/2/3/4/5 correlate too for ADDR/DATA/STAT

ie, the 80186 uses

Label  0: ADDR     (20 bits):  A3: ........ ....****  A2: ******** ******** 
Label  1: DATA     (16 bits):  A1: ******** ******** 
Label  2: STAT     (10 bits):  A5: .....*** ........  A3: *****.** ........ 
Label  3: SIZE     ( 3 bits):  A3: *..*.... ........  A2: ........ .......* 
Label  4: S6       ( 1 bits):  A3: ..*..... ........ 
Label  5: COPROC   ( 9 bits):  A5: .....*** ........  A3: ***.*.** ........ 
Label  6: DMA CH   ( 6 bits):  A5: .....*** ........  A3: ***..... ........ 

Which is 65 bits, but doesn't indicate Which bits are were on POD1/2/3/4/5

the good thing is if your ADDR is 16 bits, but the IA needs 24 Bits, it will tell you !

Are we to assume A1 -> POD1 , A2 -> POD2, A3 -> POD3  ?

[gslick]

I built 32-bit x86 DLL versions of inverse assemblers from a subset of the .R files contained in the invasm_v3.zip file in the first post of this thread.

This involved a lot of tedious manual cut-n-pasting and editing so I wouldn't be surprised if there might be an error or two, and I haven't tried going through and loading all of them yet, but I'll go ahead and post this set now. If I find any errors, I will post updates with corrections. If anyone finds any errors before I do, let me know. Also, I haven't started creating sample configuration files for these yet.

IAL68000_I
IAL68000_P
IAL68008_I
IAL68008_P
IAL6800_I
IAL6800_P
IAL68010_I
IAL68010_P
IAL6809E_P
IAL6809_I
IAL6809_P
IAL8085_IP
IAL8086_I
IAL8088_I
IALNSC800_I
IALZ80_I

EDIT 3/12/2024:
I found one build error so far. The IAL68000_P project was built with the IAL6800_P .R file instead of the IAL68000_P .R file. I didn't catch that cut-n-paste error until I went through all of the IA files in this set and tried loading them one at a time into the logic analyzer application, then noticed that the Listing window for the IAL68000_P IA had the wrong IA column. I rebuilt the IAL68000_P project with the correct .R file. The attached IAL.ZIP file now has an hpAnalysisAddInIAL68000_P.dll file with a date of 03/12/2024.

[Hamster]

gslick, thanks! I will test them as i can, if i find errors, i can always rebuild or look into now that i can also make them, yeah, the vsproj template has some errors, and obviously lacks the 64 bit stuff, I was looking at it and was actually thinking of creating a real installed ( based on Inno Setup ) , it has a more powerful way of checking directories and seeing if things are installed 

i think windows' Program Files and Program Files (x86) was the dumbest ideas Microsoft ever came up with .

FYI , for reference:

Last letter of "P" means the IA file is for use with general purpose probing (e.g., flying leads).
Last letter of "I" means the IA file is for use with dedicated hardware interfaces (often called "preprocessors").

[MarkL]

So, now need to make a nice cheat sheet for pod assignments on the 10269C

cXXXXX_p.txt will indicate the ADDR/DATA assignments, but not which pod goes where.

ie, what are POD1/2/3/4/5 correlate too for ADDR/DATA/STAT

ie, the 80186 uses

Label  0: ADDR     (20 bits):  A3: ........ ....****  A2: ******** ******** 
Label  1: DATA     (16 bits):  A1: ******** ******** 
Label  2: STAT     (10 bits):  A5: .....*** ........  A3: *****.** ........ 
Label  3: SIZE     ( 3 bits):  A3: *..*.... ........  A2: ........ .......* 
Label  4: S6       ( 1 bits):  A3: ..*..... ........ 
Label  5: COPROC   ( 9 bits):  A5: .....*** ........  A3: ***.*.** ........ 
Label  6: DMA CH   ( 6 bits):  A5: .....*** ........  A3: ***..... ........ 

Which is 65 bits, but doesn't indicate Which bits are were on POD1/2/3/4/5

the good thing is if your ADDR is 16 bits, but the IA needs 24 Bits, it will tell you !

Are we to assume A1 -> POD1 , A2 -> POD2, A3 -> POD3  ?

I haven't tried the 80186 IA specifically, but it's been my experience with other processors that A1 -> POD1, etc., as you stated, and in the given bit positions.  Some examination of the labels or the disassembled code from gslick may be needed to determine the bit order of STAT and other encoded fields.  Fields like ADDR and DATA are MSB -> LSB, as you would expect.

EDIT: fix typo

[Hamster]

Yeah, I am thinking when i was having issues with my 1673 with the inverse assembler, it games me some weird messages about pod order, and i never got it to work correctly.

I have a bunch of systems that use these processors so it will be easy for me to check the setup / configs.. now i can actually use my LA for more fancy debugging with my Fluke System Trouble shooter.

I have a Professor Pac Arcade PCB Stack that has issues, and never been able to successfully figure out "where" its crashing out at when doing a ram test , as the fluke reports no issues.

It will fun stacking the IA + Fluke Pod to it

[Hamster]

also looking at the 80186 ( which is one i just picked out of thin air ) , seems Stat/CoProc/Dma Ch all use the same A5 Pod..  but no A4.. so POD4 shouldn't do anything on the IA module.

[gslick]

also looking at the 80186 ( which is one i just picked out of thin air ) , seems Stat/CoProc/Dma Ch all use the same A5 Pod..  but no A4.. so POD4 shouldn't do anything on the IA module.

I haven't found a full manual for the 64658A 10306B 80186/80188 Interface yet, which should have full details on the POD signal connections.

There are manuals available for some of the other preprocessor interfaces, which have full details on the POD signal connections. For example:

64657B 10312D 80286 Preprocessor Interface
http://www.bitsavers.org/test_equipment/hp/logic_analyzer_preprocessors/10312-90911_10312D_80286_Preprocessor_Operating_Manual_198902.pdf

E2409B 80286 Preprocessor Interface
http://www.bitsavers.org/test_equipment/hp/logic_analyzer_preprocessors/E2409-90903_E2409B_Intel_80286_Preprocessor_Interface_Users_Guide_Feb92.pdf

10314D 80386DX Preprocessor Interface
http://www.bitsavers.org/test_equipment/hp/logic_analyzer_preprocessors/10315_90915_10314D_Intel_80386DX_Preprocessor_Interface_Users_Guide_199202.pdf

[Hamster]

I have the Manuals for the z80, 68000 I will try to scan them when i put my hands on them, it has all the pin information in them.

Obviously this isn't needed for the _P IA Options ( non pre-processor )

[gslick]

I have the Manuals for the z80, 68000 I will try to scan them when i put my hands on them, it has all the pin information in them.

Obviously this isn't needed for the _P IA Options ( non pre-processor )

These two manuals have full schematics for the 64683A 10300B Z80 and 64670A 10311B 68000 Preprocessors:

http://www.bitsavers.org/test_equipment/hp/logic_analyzer_preprocessors/64683A_Z80_Interface_Module_Service_Brief_6483-90901_Jan_1983.pdf

http://www.bitsavers.org/test_equipment/hp/logic_analyzer_preprocessors/64670A_68000_Interface_Card_Service_Brief_64670-90901_Dec_1982.pdf

If anyone is curious, with preprocessor schematics and the Signal Routing tables B-1 and B-2 in the 10269C manual it can be seen exactly how the signals from the target microprocessor route though the preprocessor and the 10269C to the logic analyzer POD connections.

http://www.bitsavers.org/test_equipment/hp/logic_analyzer_preprocessors/10269-90910_General_Purpose_Probe_Interface_Aug87.pdf

[Hamster]

Based on what i see...

For Z80...  I assume State Machine Mode.. Rising Edge on CLK0 for Qualifier? or Falling Edge?

ADDR

A0  - J4 1 - POD 2 / 0
A1  - J4 2
A2  - J4 3
A3  - J4 4
A4  - J4 5
A5  - J4 6
A6  - J4 7
A7  - J4 8
A8  - J4 9
A9  - J4 10
A10 - J4 13
A11 - J4 14
A12 - J4 15
A13 - J4 16
A14 - J4 17
A15 - J4 18 - POD 2 / 18

DATA

D0 - J3 45 - POD 1 / 0
D1 - J3 46
D2 - J3 47
D3 - J3 48
D4 - J3 49
D5 - J3 50
D6 - J3 51
D7 - J3 52 .. POD 1 / 7


LWR - J3 53   .. POD 1 / 8  [STAT.0]
LIORG - J3 54          [STAT.1]
LRFSH - J3 55          [STAT.2]
LMI   - J3 56         [STAT.3]
LBUSRQ- J3 57         [BUSREQ]*DISABLED
LNMI  - J3 58         [NMI]*DISABLED
LHALT - J3 59         [HALT]*DISABLED
LINT  - J3 60 - POD 1 / 15   [INT]*DISABLED

LMREQ - CLK0/J3 23  -- POD 1 J CLK  ( Memory Request )
LIORQ  - CLK1/J3 21   -- POD 2 K CLK ( IO Request )
LRFSH  - CLK2/J3 17   -- POD 3 L CLK ( Refresh )

LBUSAK - J3 19       -- POD 3 / 0 ( BUS Ack ) ** not in .text file.

LWAIT  - WT5 -- NC ( if you wanted to see this, you need to run a jumper from WT5 over to WT3 or WT2 )

[gslick]

HP 10300B Zilog Z80 Preprocessor for the HP 1650A/51A and HP 16510A Logic Analyzers
Operating Manual, Part Number 10300-90911, February 1989

Table 2-1 Z80 Signal List

CPU Signal  CPU Pin Label       Pod Bit
-----------+-------+-----------+---+-----
LMREQ       19      (Clock)     1   J CLK
LIORQ       20      (Clock)     2   K CLK
LRFSH       28      (Clock)     3   L CLK

A0          30      ADDR        2    0
A1          31      ADDR        2    1
A2          32      ADDR        2    2
A3          33      ADDR        2    3
A4          34      ADDR        2    4
A5          35      ADDR        2    5
A6          36      ADDR        2    6
A7          37      ADDR        2    7
A8          38      ADDR        2    8
A9          39      ADDR        2    9
A10         40      ADDR        2   10
A11          1      ADDR        2   11
A12          2      ADDR        2   12
A13          3      ADDR        2   13
A14          4      ADDR        2   14
A15          5      ADDR        2   15

D0          14      DATA        1    0
D1          15      DATA        1    1
D2          12      DATA        1    2
D3           8      DATA        1    3
D4           7      DATA        1    4
D5           9      DATA        1    5
D6          10      DATA        1    6
D7          13      DATA        1    7

LWR         22      STAT        1    8
LIORQ       20      STAT        1    9
LRFSH       28      STAT        1   10
LM1         27      STAT        1   11
LBUSREQ     25      (Note 1)    1   12
LNMI        17      (Note 1)    1   13
LHALT       18      (Note 1)    1   14
LINT        16      (Note 1)    1   15

Note 1: These signals are not required for inverse assembly and do not appear on the STAT label. However, they may be useful for Z80 analysis.

Clock on (Falling Edge of Clock J + Falling Edge of Clock K)
LMREQ is inverted by the interface module for Clock J
LIORQ is inverted by the interface module for Clock K

To filter out Z80 refresh cycles:
Clock on (Falling Edge of Clock J + Falling Edge of Clock K) * Clock L
Capture data on the falling edge of the J or K clock only when the L clock (LFRSH) is high (not a refresh cycle).

[Hamster]

I would like two hours of my time cross refencing the docs you posted above and not the doc i can't seem to find...

Where did you find this document? And is there a scan available long with ones for the other IA Modules?

HP 10300B Zilog Z80 Preprocessor for the HP 1650A/51A and HP 16510A Logic Analyzers
Operating Manual, Part Number 10300-90911, February 1989

no amount of googling seems to be able to find said document.

[MarkL]

I spent a little time to adapt gslick's IZ80_I.S (the disassembled IZ80_I.R) so that /WR was interpreted normally (i.e., not inverted as it appears from the preprocessor).  This allows it to be used with general purpose probing.  I called it mz80_p.  Zip archive below with the source and the .R file as assembled by the HP 10391B development package.

I also found that the multiple 240/241 buffers in the preprocessor must have delays that are significant to the state clocking.  When using the rising edge of /MREQ and /IOREQ as the clock directly from the CPU, the address and other lines can start changing before those rising edges.  This interferes with a valid capture of state data.  Changes in the address, data, and other lines are actually initiated inside the CPU by the rising edge of Phi (the Z80 clock input).

To keep with the goal of using only general purpose probes and not adding gates to implement delays, Master/Slave clocking was activated which clocks all state data into the slave latches on the rising edge of Phi.  Then on the rising edge of the master clock, /MREQ or /IOREQ, the analyzer completes the state capture.  This seems to work reliably.

User gslick presented a way to filter out refresh cycles in the listing by using the /RFSH signal as a clock qualifier.  An alternative way is to use the Conditional Store feature, and only store those states which are not refreshes.  The end result is the same, but this way preserves a clock input for possibly something else.

Screen captures of various settings I used and output examples below.  I've probed all pins except power, but obviously this is not necessary.  Eventually I'll probably make an adapter to make this easier to set up.

I used mz80_p.r on a 16702B with a 16752A card, which needs to be imported by the IAL utility first.

Please post success or any problems with mz80_p if you try it.

EDIT:  Oops, forgot the zip file and fix typo....

[gslick]

At the same time you were doing that, I was working on the X86 DLL General Purpose Probe version for the 1680/1690/16800/16900 series.

One thing I did different was to set the Slave Clock to be both edges of the Z80 CPU clock. If I understand the Z80 timing diagrams correctly, opcode fetch and interrupt ack cycles end just after a rising edge of the Z80 CPU clock, while memory and I/O read and write cycles end just after a falling edge of the Z80 CPU clock

CPU Signal  CPU Pin Label       Pod Bit
-----------+-------+-----------+---+-----
CLK          6      CLK-J       1   J CLK
LMREQ       19      LMREQ-K     2   K CLK
LIORQ       20      LIORQ-L     3   L CLK
LRFSH       28      LRFSH-M     4   M CLK

A0          30      ADDR        2    0
A1          31      ADDR        2    1
A2          32      ADDR        2    2
A3          33      ADDR        2    3
A4          34      ADDR        2    4
A5          35      ADDR        2    5
A6          36      ADDR        2    6
A7          37      ADDR        2    7
A8          38      ADDR        2    8
A9          39      ADDR        2    9
A10         40      ADDR        2   10
A11          1      ADDR        2   11
A12          2      ADDR        2   12
A13          3      ADDR        2   13
A14          4      ADDR        2   14
A15          5      ADDR        2   15

D0          14      DATA        1    0
D1          15      DATA        1    1
D2          12      DATA        1    2
D3           8      DATA        1    3
D4           7      DATA        1    4
D5           9      DATA        1    5
D6          10      DATA        1    6
D7          13      DATA        1    7

LWR         22      STAT        1    8
LIORQ       20      STAT        1    9
LRFSH       28      STAT        1   10
LM1         27      STAT        1   11
LBUSREQ     25      (Note 1)    1   12
LNMI        17      (Note 1)    1   13
LHALT       18      (Note 1)    1   14
LINT        16      (Note 1)    1   15

Note 1: These signals are not required for inverse assembly and do not appear on the STAT label. However, they may be useful for Z80 analysis.

Slave Clock:
Both Edges of Clock J

Master Clock:
(Rising Edge of Clock K + Rising Edge of Clock L)
Filter Out Refresh Cycles:
(Rising Edge of Clock K + Rising Edge of Clock L) * Clock M

[gslick]

What do you call those 1-to-4 0.1 pin header breakout connectors? I couldn't guess the correct search term to find them. Where can you get them? I could have used some of those to make it easier to attach the doubled up flying lead connections to the DIP test clip.

[MarkL]

What do you call those 1-to-4 0.1 pin header breakout connectors? I couldn't guess the correct search term to find them. Where can you get them? I could have used some of those to make it easier to attach the doubled up flying lead connections to the DIP test clip.

The part number is HP 16515-27601 "GND CONNECTOR".  They're included with the 16517-68701 Master Board Accessory Kit and 16518-68701 Expander Board Accessory Kit., but only two per kit.  I haven't seen them anywhere else.  They're fairly handy and I'd buy a pile of them if I could find them in quantity.

I think you're right about the memory and I/O cycles.  It is a little different than the opcode fetch.  Using the rising edge of CLK cuts the sample window a little short, but it still seems to be sampled with plenty of margin.  Properly, though, I think you're right to sample on both edges.  I'll have to look a little more into this.

Did you try the IA I posted, or did you already have a version?  Just wanted to confirm it's working ok for others.  If you already modified the Z80 IA and posted it before, sorry I missed it.

[gslick]

Here are some sample Z80 waveforms I captured with Timing Zoom enabled so that both state and timing samples are available.

With the Slave Clock set to both the rising and falling edges of the CPU Clock, in the Opcode Fetch waveform sample the relevant Slave Clock edge is the rising edge of the CPU clock at the marker position T3-H, just prior to the Master Clock at the rising edge of LMREQ at the marker position MREQ-H.

With the Slave Clock set to both the rising and falling edges of the CPU Clock, in the Memory Read waveform sample the relevant Slave Clock edge is the falling edge of the CPU clock at the marker position T3-L, just prior to the Master Clock at the rising edge of LMREQ at the marker position MREQ-H.

If the Slave Clock was set to only the rising edge or only the falling edge of the CPU Clock, the timing margin to capture valid state data could be reduced by half of a clock period, which could possibly be an issue if the access times of devices in the target system were near the timing margin limits.

Zilog databook timing diagrams came from here:
http://www.bitsavers.org/components/zilog/z80/03-0029-01_Z80_CPU_Technical_Manual_1977.pdf

[MarkL]

The opcode fetch is a faster cycle than a regular memory fetch.  Below is the opcode fetch timing cycle without the wait states.  The first byte of the instruction is sampled by the CPU on the second rising edge of PHI after /MREQ falls.  In rough numbers, this allows 1.5 clock periods for access time.

A memory data read is sampled by the CPU on the second falling edge of PHI after /MREQ falls, allowing it roughly 2 clock cycles for access time.

Since the opcodes and operands necessarily share the same physical memory in the Z80 architecture, they therefore have the same access speed requirements.  The system must be designed to support the higher speed of the opcode fetch cycle.

So, LA slave sampling on the rising edge of PHI, with only 1.5 cycles of access time, should always work for memory.  I suppose it's possible that a Z80 system could be designed with slower memory that is only for data and never instructions, but I've never seen that.

However, in the case of an I/O read, the cycle time is roughly 2.5 cycles, and starts on a rising edge of PHI, which is later in phase than an opcode or memory cycle.  See I/O timing below (the "Tw" in the diagram is an automatically inserted wait state).  If the LA slave was sampling only on the rising edge of PHI, the peripheral read would have only 2 cycles to settle.  Giving it an extra half cycle to settle is probably not going to make a difference since peripheral registers, etc. are generally much faster to access than memory, but it would be wrong to assume this is always the case.

I think I'm convinced sampling on both edges of PHI is the right thing.

[MarkL]

One interesting thing in my timing capture is that the address lines start changing before the rising edge of /MREQ.  When using /MREQ * /IORQ as the only clock, which I tried first, it created nonsensical results in the state capture.  This is what led me to look at PHI to do the slave latch capture.

However, in your timing digram, the address lines are stable for at least 80ns (MemRead) to 200ns (OpFetch), leaving plenty of time to use /MREQ * /IORQ in master mode as the only clock (no slave).

With your previous analysis of buffer delays in the Z80 Interface Module:

  https://www.eevblog.com/forum/testgear/older-logic-analyzer-question/msg2525412/#msg2525412

I'm not sure how this would have ever worked for me, since /MREQ * /IORQ would occur even later because of the buffer delays.

One difference in my system is that I'm using a Zilog Z80H, which is the 8MHz variant (in contrast to the standard part speed of 4MHz).  It's not beyond reason that the external bus interface in the chip was modified for the higher speed and behaves a little differently.  The Z80H was introduced in 1982 (wikipedia), perhaps after the Interface Module was released?

At any rate, it doesn't change the approach to use master/slave clocking, or clocking on both edges of PHI.  In fact, it's required in my case.  Just thought it was interesting.

[Hamster]

This is great stuff  ! Love it.. I have two large driving arcades leaving and going to setup a proper station so i can test things out and dig in and help.

[gslick]

One interesting thing in my timing capture is that the address lines start changing before the rising edge of /MREQ.  When using /MREQ * /IORQ as the only clock, which I tried first, it created nonsensical results in the state capture.  This is what led me to look at PHI to do the slave latch capture.

However, in your timing digram, the address lines are stable for at least 80ns (MemRead) to 200ns (OpFetch), leaving plenty of time to use /MREQ * /IORQ in master mode as the only clock (no slave).

With your previous analysis of buffer delays in the Z80 Interface Module:

  https://www.eevblog.com/forum/testgear/older-logic-analyzer-question/msg2525412/#msg2525412

I'm not sure how this would have ever worked for me, since /MREQ * /IORQ would occur even later because of the buffer delays.

From https://www.eevblog.com/forum/testgear/older-logic-analyzer-question/msg2525412/#msg2525412

Once through a 74LS240 Inverting Octal Buffer and Line Driver:
PIN 19 /MREQ    CLOCK J

Once through a 74LS240 Inverting Octal Buffer and Line Driver:
PIN 20 /IORQ    CLOCK K

Twice through a 74LS240 Inverting Octal Buffer and Line Driver:
PIN 20 /IORQ    STAT BIT 1

Three times through a 74LS240 Inverting Octal Buffer and Line Driver:
PIN 22 /WR      STAT BIT 0

One result of that is that the /WR signal as used for a STAT bit should be delayed by two gate propagation delay periods relative to the /MREQ and /IOREQ signals as used for the J and K clocks.

Delaying the /WR signal before it is sampled at the /MREQ and /IOREQ signal edges as used for the J and K clocks when using the 10300B Z80 preprocessor might be important if the /WR signal transition at the CPU pin can occur before the /MREQ signal transition at the CPU pin.

That appears to be occurring in the trace that I previously acquired when I scrolled forward to a memory write cycle. The rising edge of the /WR signal appears to occur around 3.25ns before the rising edge of the /MREQ signal (with the Timing Zoom sampling resolution of 250ps).

[MarkL]

...
Delaying the /WR signal before it is sampled at the /MREQ and /IOREQ signal edges as used for the J and K clocks when using the 10300B Z80 preprocessor might be important if the /WR signal transition at the CPU pin can occur before the /MREQ signal transition at the CPU pin.

That appears to be occurring in the trace that I previously acquired when I scrolled forward to a memory write cycle. The rising edge of the /WR signal appears to occur around 3.25ns before the rising edge of the /MREQ signal (with the Timing Zoom sampling resolution of 250ps).

Going back in my captured data, I also see /WR going high (mumble) 8ns before /MREQ in some cases.  For example, the first address byte pushed on the stack in a CALL is that way, but the second address byte has /WR coincident with /MREQ, at least as far as 4ns TZ sampling can tell.  (I don't have the system set up anymore to get a more precise delay measurement.)

Fortunately, slave latch clocking on both edges of PHI saves us there too for the general probing case.

Side note: For some reason the reload of data did not restore the symbols for STAT_TZ.  It was certainly there when doing the capture.  Maybe a bug?  Oh well... that's not getting fixed.

[MarkL]

This is great stuff  ! Love it.. I have two large driving arcades leaving and going to setup a proper station so i can test things out and dig in and help.

All fun!  Glad it's helpful for you!

[gslick]

What do you call those 1-to-4 0.1 pin header breakout connectors? I couldn't guess the correct search term to find them. Where can you get them? I could have used some of those to make it easier to attach the doubled up flying lead connections to the DIP test clip.

The part number is HP 16515-27601 "GND CONNECTOR".  They're included with the 16517-68701 Master Board Accessory Kit and 16518-68701 Expander Board Accessory Kit., but only two per kit.  I haven't seen them anywhere else.  They're fairly handy and I'd buy a pile of them if I could find them in quantity.

Thanks for the part number.

This eBay listing photo shows two of those 16515-27601 in the item listing photo for $9.95, plus shipping. Not clear if two are included per item purchase, or only one:

Keysight 16515-27601 Ground Connector for 16517-68701 Accessory Kit
https://www.ebay.com/itm/354835319679

This eBay listing photo shows four of those in the item listing photo with some ground leads and some sort of probe for $19.95 (OBO), plus shipping. I assume in this listing everything in the item listing photo would be included. Not super cheap, but not an outrageous price if makes things easier to get probes set up.

Keysight 16515-68703 16515A 16516A 1 GHz Timing Probe Accessory Kit
https://www.ebay.com/itm/350517306271

[MarkL]

...
This eBay listing photo shows two of those 16515-27601 in the item listing photo for $9.95, plus shipping. Not clear if two are included per item purchase, or only one:

Keysight 16515-27601 Ground Connector for 16517-68701 Accessory Kit
https://www.ebay.com/itm/354835319679

This eBay listing photo shows four of those in the item listing photo with some ground leads and some sort of probe for $19.95 (OBO), plus shipping. I assume in this listing everything in the item listing photo would be included. Not super cheap, but not an outrageous price if makes things easier to get probes set up.

Keysight 16515-68703 16515A 16516A 1 GHz Timing Probe Accessory Kit
https://www.ebay.com/itm/350517306271

I saw the first listing and it seemed a bit pricey when you add in shipping, but I didn't know the ground connectors were also provided in the 16515-68703.  Thanks!

Those other leads in the pouch are ground extenders, 6" M-F and fit standard 25mil posts.  I have a few of those too, but I don't know where I got them.  Why HP has 6" ground leads in a GHz probe set seems strange, but they are a handy accessory.  With those included the package at the same price, I may have to get some.  I've purchased from Global Test before.  They tend to accept reasonable offers when buying a quantity, and they combine shipping.

[MarkL]

And that probe is probably one of these, below.  It has a 200 ohm series resistor inside ot it.  The non-pointy end is 0.1" spacing.  I have several of those too, but they don't fit anything I have.

I guess somewhere I must have inherited some of those 16515-68703 kits, or at least the contents of them.  A lot of the time these things are just thrown in with other LA accessories when buying on ebay.

[Nemesis1207]

Has anyone been able to successfully load inverse assemblers on the 1670G? I've been bashing away at this for a couple of days now without any real progress. I have the invasm_v3 files transferred over, and the unit seems to recognize them. The config files load in happily, but when I try and load the inverse assemblers, any of them, the unit hangs for 30 seconds or so then fails to load and/or crashes, like this:


I'm after the z80 and 68000 ones in particular, but it doesn't seem to matter what inverse assembler I pick as all the ones I've tried fail in the same manner. Any advice appreciated.

[Nemesis1207]

Never mind, got that sorted. I was loading files onto the unit via ftp, since the 1670G has a LAN port. I thought I'd setup my ftp client to transfer everything in binary mode (IE, don't try and do newline translation), but it turns out there was a sneaky setting to treat all files without extensions (like "i68000_p") as text, meaning it was corrupting the binaries. The inverse assemblers now appear to load. Just got to mess around with pod mappings now so they work properly. At least while going around in circles over the last two days I've got setup to build these things from source, so I'll be able to hack away at them.