Keysight announced new 110 GHz scopes

[Keysight DanielBogdanoff]

Hello,

my respect, this is great scope.

If a customer buy such a scope would an employee bring the scope and train the customer?

Best regards

egonotto

Thanks! You'd have to talk to your local application engineer (AE) about on-site support and setup time.

Daniel - congrats to you and the Keysight team on the UXR!  Super impressive achievement 

-Rich

Thanks, Rich!

Thanks for the post UNN and comments esp Daniel from K-S, would have been a fascinating development, would love to have been a 'fly on the wall'.
That is a LOT of data coming at you. 250GSa/S x4(channels) x10bits 

It's very impressive - 10Tb/s. Is it DDR or something more specialised? Lots of pins on the ASIC to drive that many memory banks in parallel. 

I think I'm allowed to say... it's a hybrid memory cube. 

[srce]

Thanks for the post UNN and comments esp Daniel from K-S, would have been a fascinating development, would love to have been a 'fly on the wall'.
That is a LOT of data coming at you. 250GSa/S x4(channels) x10bits 

It's very impressive - 10Tb/s. Is it DDR or something more specialised? Lots of pins on the ASIC to drive that many memory banks in parallel. 

I think I'm allowed to say... it's a hybrid memory cube. 

Interesting - not come across that before.

Here's a micron part
datasheet for anyone interested.

£400 for 2GB - 896 pin - 1.28Tb/s bandwidth. 4 x 16 SERDES links at 15Gb/s each. So you'd probably just need to have two of those per scope channel.

Nice 

[Berni]

Holy crap that is a speedy memory chip

But the chip is actually pretty cheap at such a price tag when you go find a FPGA that is callable of running this monster at full wack. The interface to it is 4 links, each having 8 to 16 pairs and TX and RX is separate. So that gives us 4 x 16 x 2 = 128 serdes channels! Even FPGAs with 4 serdes channels at these speeds cost an arm and a leg.

But seeing this has those 4 links... does that mean that this is also technically quad-port memory with all ports capable of individual write+read operation?

[Muxr]

If they are rolling their own ASICs they could have leveraged something like HBM2 as well with 256 GB/s per package.

[srce]

If they are rolling their own ASICs they could have leveraged something like HBM2 as well with 256 GB/s per package.

From a quick google - that looks harder to integrate though.

For HMC it looks like you have 128 differential data pins @ 15Gb/s (512 IO in total) in a BGA package - whereas HMB2 looks like 1024 data pins @ 2.4Gb/s (1696 IO in total as there's lots more control pins per channel) and the memory has to be integrated in package on an interposer. If you need two, I'd guess you're going to struggle with needing >3000 IO

[Brumby]

I'm still catching up with this....

It's actually doing real-time acquisition instead of reconstructing the signal from a frequency domain acquisition?  That's... astonishing.  Wow.  Just wow.  ASIC or not.  Just wow.

[vaualbus]

I'm just curious  to the overall system architecture.
So we know  that we have 4 boards each handling one channal,
Than there has to be another boeard for handling each channel 1.2Tb/s data.
I beat it is full of asic/fpga/DSP that converts that signal into I guess PCI 3.0 (or thunderboalt?) interface that go to the computer side.
I will beat that you use almost all of the pci lanes avaible from the processor (i7 or i9 by the way?).
Than I will beat there is yet another board handling reference clock for the four channel.
And a monster power supply of course.

[FrankBuss]

In case someone missed it:

https://www.eevblog.com/forum/testgear/something-amazing!-keysight-uxr-110ghz-256gss-10-bit-scope-teardown-exp/