Measuring low impedances with a VNA

[bson]

Interesting...  That greatly simplifies the test setup! 

[precaud]

For testing 'lytics, yes it does.

Over the last couple days I've had some interesting email discourse with the designer of the Cleverscope. He has added significant capability for Z measurement (several topologies/techniques) in their software. And wrestled with the difficulty of measuring low-Z at high freqs. He put it in context this way:

1mm of pcb track between the test point and the DUT adds roughly 1nH of inductance, which at 1MHz has an impedance of 6mOhm. At 10MHz, is it 60mOhm.

I haven't confirmed if his figures are exact, but the point stands. And as I have let it sink in, methinks perhaps I shouldn't fret too much about board-level single-digit Z measurement above 1MHz. Other than identifying gross anomalies and resonances, which isn't as exacting.

[Pitrsek]

To keep inductance low, you need closely spaced power plane/ground plane pair on multi-layer board. Once you have that, life is way easier for layout as well. With regular 1,5mm double side board, the inductance is too high even with ground plane. Actually this would make nice demonstration as well,hm... I need to book the VNA for some tests  . 

[Hydron]

For testing 'lytics, yes it does.

Over the last couple days I've had some interesting email discourse with the designer of the Cleverscope. He has added significant capability for Z measurement (several topologies/techniques) in their software. And wrestled with the difficulty of measuring low-Z at high freqs. He put it in context this way:

1mm of pcb track between the test point and the DUT adds roughly 1nH of inductance, which at 1MHz has an impedance of 6mOhm. At 10MHz, is it 60mOhm.

I haven't confirmed if his figures are exact, but the point stands. And as I have let it sink in, methinks perhaps I shouldn't fret too much about board-level single-digit Z measurement above 1MHz. Other than identifying gross anomalies and resonances, which isn't as exacting.

A run through Saturn PCB Toolkit (highly recommended free software) shows this is in the right ballpark (see attached pic).

With ground planes you get much higher C/lower L than a thin track, but it's still tricky to measure anything down in the milliohms.

I have been using a Cleverscope for looking at <20mohm impedances in the 300+ kHz region and it's not easy to get to the point where you're completely sure whether stuff is coming from a fixture or the DUT - small test setup changes can make a fair difference. The isolated sig-gen and a DC-50Mhz current clamp (tek a6302, not cheap even decades old) lets you cheat braid error though!

[precaud]

A run through Saturn PCB Toolkit (highly recommended free software) shows this is in the right ballpark (see attached pic).

Thanks for that, will check out that program.

I have been using a Cleverscope for looking at <20mohm impedances in the 300+ kHz region and it's not easy to get to the point where you're completely sure whether stuff is coming from a fixture or the DUT - small test setup changes can make a fair difference.

Yeah, this seems to be the case regardless of the instrument used.

The isolated sig-gen and a DC-50Mhz current clamp (tek a6302, not cheap even decades old) lets you cheat braid error though!

Isn't the isolated output alone sufficient to kill the braid error loop? That isolated-output gen is one of the very attractive things about the CS, for sure. Which ADC option are you using? Bart is pretty convinced that the 10-bit (with averaging) is fine for Z/phase below 1MHz.

[bson]

I winged a quick and dirty test fixture using whatever I had on hand, and calculated the ESR of a brand new 100uF 35V Nichicon PW to ~50mohm.  Looks ballpark.  (Trace is unrelated, I was still experimenting and I had a 20dB pad on the A input.)  The bare wires are ground interconnects, in addition to solder bridges on the copper side.

Should be fine at least to a few MHz, then it rolls off instead of climbs indefinitely.  I might spin an actual board for this, but for electrolytics it seems to work fine as is.



VNA |Z| trace, wiggle due to 1s sweep time as I was setting things up.  The instrument isn't on GPIB right now or I'd pull the trace data and work on that instead.



Calculator:

import sympy as s
import math, sys

Ra  = 50.    # Input A impedance (50/1M)
Rdiv=9.989 # Divider resistor
Pad = 0.     # dB, on R

def db(a): return math.pow(10., a/10.)

Z=s.Symbol('Z', complex=True)

def zpar(a,b): return (a*b)/(a+b)

def zdiv(a,b): return b/(a+b)

# T relative to R:
# T=Tr*Ta; we read A/R so measure T/Tr = Ta
T=zdiv(Rdiv, zpar(Z, Ra))

val = db(float(sys.argv[1]) - Pad)

print s.solve(s.Eq(T, val), Z)

The "pad" is on R, to permit use of higher power levels, but that didn't seem to make any difference and I stopped doing it (just made cal harder).  The impact of R_A is minimal.  But, unfortunately, since it's a divider it's not possible to simply measure a know quantity like a 1ohmish resistor and then scale relative to it.  (Well it is, it's just the error grows as Z gets closer to R_div.)  So I short cal'ed it to A=R by shorting out R_div.  (Again, the first trace above is before all this, when I was just happy to see the tub shape. )

python calcz.py -23.1
[0.0492131962124952]

I also experimented with biasing, but clearly the supply I used (HP 66312) doesn't have sufficient bandwidth; not to mention the risk of blowing an input (though my HP 3577A claims on the front that its trip protection is safe to 25V DC and I was only biasing the - terminal by -0.2V for the -5dBm signal level, but still...).  If I make a board I might stick a biggish CLC pi filter on it for biasing with an external supply.  Maybe.  I'm still looking to convince myself there is no dielectric polarization effect skewing the response.

The phase response in general though (missing from the first image) nicely shows X_C=X_L and hence a purely resistive residual impedance.



Not sure I should post here since I'm confident I got lots wrong and some nutter is going to accuse me of being a Trump-sized liar.   But, regardless, it was a fun little Sunday afternoon project and the measurements don't look totally off!

[RoGeorge]

calculated the ESR of a brand new 100uF 35V Nichicon PW to ~50mohm

It would be interesting to measure the same capacitor, then compare the measured ESR with the calculated one.

[bson]

calculated the ESR of a brand new 100uF 35V Nichicon PW to ~50mohm

It would be interesting to measure the same capacitor, then compare the measured ESR with the calculated one.

My Keysight U1733C gives me ~120mohm at 10kHz - it's unable to obtain a stable reading at 100kHz.  The cap datasheet promises max 100mohm @ 100kHz for the 35V size.
So, looks plausible... 

[precaud]

Should be fine at least to a few MHz, then it rolls off instead of climbs indefinitely.  I might spin an actual board for this, but for electrolytics it seems to work fine as is.

Looks good for a Q&D fixture. Accuracy vs frequency will be a function of the impedance. Unlikely to hold up into the "several MHz" range, except above 100mOhm. At 100kHz you're fine at 50mOhm. Definitely a good idea to short your terminals to see what the baseline is. If you can store that trace data in Real/Imag format and subtract it from new measurements, you'll have an effective Short compensation. That will extend the usable BW and improve accuracy.

The "pad" is on R, to permit use of higher power levels, but that didn't seem to make any difference and I stopped doing it (just made cal harder).

Yes, it helps when your analyzer has good dynamic range

Not sure I should post here since I'm confident I got lots wrong and some nutter is going to accuse me of being a Trump-sized liar.   But, regardless, it was a fun little Sunday afternoon project and the measurements don't look totally off!

No accusers here. Keep sharing your results. You now have one of the largest ESR meters available!   

[precaud]

I wanted to see what could be done with the Shunt-Thru technique using an FFT approach. Cleverscope gets good results doing so up to 1MHz with their 10-bit 100MSa/sec ADC. It so happens I have a Lecroy 9430 laying about (2-channel 10-bit 100MSa/sec DSO). So I decided to write a driver to control it, gather the data, and merge it into the software I already have working. It took a few days but it's working fine. That is, the data is transferring accurately. Question is: is the data itself accurate?

The source signal is a "Chirp sweep", the same signal used by the HP 3562A DSA for its transfer function measurements. I have HP software that creates these chirp sweeps and can load them into an arb generator, in this case a Wavetek 75A. The general idea is to make the period of the chirp exactly equal to the time record length, so that it is a "periodic" waveform and plays nice with FFT algorithms without using any windowing. 100 time domain averages were taken to improve signal to noise. This resulted in 12- to 13-bit data from the 10-bit ADC. The gain of the test channel was raised (by 100X) to give good SNR with the low test channel's signal levels. (This is one advantage over most VNA's which use the same gain on both inputs). Combined, these two should put us into the same 100dB dynamic range territory that is typical of VNA's in this freq range. Open/Short compensation is part of my software and was used.

The first plot below is of the same two 25 mOhm currrent sense resistors that I used earlier with the MS420K; one SMD, one axial. The plot is linear freq scale, 0 to 1MHz, 2kHz per point. We know that the axial resistor should start to show inductive behavior around 100kHz. It doesn't. And the [hase rising well before that. It doesn't. The Z should be rising with increasing frequency all the way to 1MHz and beyond. Above 500kHz, it rolls off the other way. The trace is a bit noisy too.

I have included the sweep of the same two R's in the Anritsu: same software, same fixtures, etc. (The relevant curves are the yellow and green ones.) The different is the measurement technique; filtered swept sine vs FFT'ed sweep.

An FFT'ed swpt sine approach might fare better. But it would be very slow; this measurement took less than 10 seconds, including averaging.

Needless to say, these results do not inspire confidence in the broadband FFT approach.

[precaud]

Now this is interesting.  With the kind of error seen, I would expect to see poor dynamic linearity at low levels. So I tested the transmission characteristics (using an HP 355D attenuator) from 0dB to -90dB. Basically straight lines down to -60dB. Noise, and ground loop error, starts to show at -80dB, and becomes really strong at -90dB. But the response is still pretty flat. I'm not seeing anything even at -80dB commensurate with the HF rolloff seen in the previous post's measurement. I'm thinking that perhaps high input capacitance on the 9430's inputs is the culprit.

Nevertheless, not bad for a 20-year-old 10-bit 100MSa/sec ADC, eh?   

[Pitrsek]

Do you still have the raw data from measurements?If you plot VNA and lecroy in same graph, and flip the lecroy upwards, how much off it is?
I would be very wary about FFT without any windowing, are you certain that everything is sample perfect synchronized?
I'm no expert on signal processing, but I did get fair share of FFT rubbish from wrongly aligned data(lt spice).

[bson]

The rising phase clearly is inductive reactance.  I can't think of any reason for |Z| to fall off, other than if there's a calculation error...

Here's my math...

The DUT impedance is Z and its admittance Y
The input port (L=load) admittance Y_L = 1/50 - jwC_L.
The divider resistor is R and its conductance G = 1/R

Vout/Vin = T = G/(G + Y + Y_L)

=> Y = G/T - G - Y_L

=> Z = 1/(G/T - G - Y_L) = 1/(1/(RT) - 1/R - 1/50 + jwC)

|jwC| disappears with 15pF at 1MHz (0.94uS), which gives:

Z = 1/(1/(RT) - 1/R - 1/50)

The 1/50 term impacts perhaps 0.1% and is probably not significant given all the other sources of uncertainty... 
T of course is the transfer function, the difference of the complex FFTs for acquisitions A and B or obtained with VNA phase detecting receivers (tracking the source).
Or it could be the real transfer function off trace data, |T|=|A|/|B|, but then only |Z| can be determined.

The falling |Z| given the rising phase really smells like a sign error...

[precaud]

Do you still have the raw data from measurements?If you plot VNA and lecroy in same graph, and flip the lecroy upwards, how much off it is?

You and BSON are thinking the same. It looks like a sign error. That was my first thought too and I checked the math subroutines. They are unchanged. I have been using these same subroutines for 35 years. I have pretty high confidence in them  These are the same routines used with the Anritsu MS420 results posted earlier. In fact I started with the same program file. The only significant changes are the data input routines. The MS420 outputs T/R in polar form; the 9430 FFT gives R and T Real/Imag results in rectangular coordinates. Once that is converted and divided, the math is all the same.

I don't have the raw data, I typically don't integrate load/save routines until I get the measurement happening correctly and the data structure defined.

I would be very wary about FFT without any windowing, are you certain that everything is sample perfect synchronized?

Understood. This signal is specifically designed to be used without windowing functions. Windowing would act like a bandpass filter. I can change the arb generator readout clock and watch the spectrum changes. The technique is quite forgiving of sample sync, as long as the sequence completes within the window and is consistent for both channels. The routine that generates it even allows you to specify a number of zero fill at the end. IIRC, I didn't use any here.

The rising phase clearly is inductive reactance.  I can't think of any reason for |Z| to fall off, other than if there's a calculation error...
The falling |Z| given the rising phase really smells like a sign error...

The interesting thing is, though; both are WAY off. The axial R should have +45º phase shift at about 200kHz. That's the second division from the left. It's nowhere close.

Even the short measurement (not shown) has only a very small inductive rise, which is clearly in error.

I'll double-check the math subroutines, but they're pretty straighforward. For example: in HTBasic, the complex division is:
: Zref and Zdut are complex arrays
:  MAT Mag=ABS(Zdut)           (MAT operates on the entire array. Mag and Phase hold the Test signal)
:  MAT Phase=ARG(Zdut)        (ABS and ARG convert rectangular to polar)
:  MAT Mag2=ABS(Zref)
:  MAT Phase2=ARG(Zref)    (Mag2 & Phase2 hold the Ref signal)
:  scan Mag2 (the real part of the denominator) for zero values and replace them with something really small (I use 1.E-12, equivalent to 1 picoOhm), division by 0 is a fatal error...
:  MAT Mag=Mag/Mag2           (with data in polar, divide the magnitudes)
:  MAT Phase=Phase-Phase2   (and subtract the angles)
:  then convert back to rectangular and stuff it back into the Zdut array

I could just use Zdut=Zdut/Zref but I have found that the polar routine generates less "garbage", i.e. handles phase wrap better. There are fewer division operations.

That's it. Open and Thru measurements use this same routine.

[Wolfgang]

Isn't Z(f) unbiased in your fixture

Yes

and isn't this problematic with a polarized device like an electrolytic cap?

Not in my experience. I experimented with this in the mid-90's using an HP 4274A, and saw no change in impedance of a 'lytic between biased and unbiased states. That was up to 100kHz. Is it different at, say, 1MHz and above? That I can't answer. But I rather doubt it.

Hi,

I am sure it *is* different. When I made some blocking cap from 1000uf/50 electrolytics, ESR and ESL caused a significant rise from ca. 2MHz to several Ohms. At lower frequencies, the impedance was just the ERS of less than 100mOhms.
Measured on a Keysight E5061B-3L5 VNA/Impedance Analyzer.

[precaud]

I am sure *is* different. When I made some blocking cap from 1000uf/50 electrolytics, ESR and ESL caused a significant rise from ca. 2MHz to several Ohms. At lower frequencies, the impedance was just the ERS of less than 100mOhms.

Interesting. I have a good HP 4275A with DC Bias option now, so I'll run some comparisons and see if I get the same results as you do.

BTW, I *did* solve the issue I was asking about in the thread, I just forgot to come back and write about it.   

Now its been so long, I can't remember what it was...

[precaud]

I just measured an Elna 1000uF 50V lytic from 10kHz to 10MHz in the 4275A. The differences in C and ESR with and without +5V DC bias are insignificant. This is typical of past results.

[Wolfgang]

Maybe I try with another brand.

[precaud]

Maybe also we should remind ourselves, a 1000uF 'lytic is not a capacitor at 2MHz. Typical phase zero crossing (and most meaningful ESR value) is in the 100kHz range. So if the calculated ESR is dropping at 2MHz, it only means that the cap is close to being purely inductive. I saw that in the Elna cap. By 10MHz the phase is +87.5º and ESR drops to 1/3 its value at 100kHz, suggesting that the ESR and ESL is resonating with some parallel C up there...

[Wolfgang]

Maybe also we should remind ourselves, a 1000uF 'lytic is not a capacitor at 2MHz. Typical phase zero crossing (and most meaningful ESR value) is in the 100kHz range. So if the calculated ESR is dropping at 2MHz, it only means that the cap is close to being purely inductive. I saw that in the Elna cap. By 10MHz the phase is +87.5º and ESR drops to 1/3 its value at 100kHz, suggesting that the ESR and ESL is resonating with some parallel C up there...

Hi,

I tried around a bit and found the following facts:

- The influence of DC *is* cap brand dependent, as is the SRF. I dont know what causes this. The effect is about 10% of ESR and SRF shift.
- SRFs of electrolytic caps 1000uF/50V depend a *lot* on make. Some large ones from Panasonic were very good, some no-name had a SRF of just a few 100kHz.

https://electronicprojectsforfun.wordpress.com/rf-measurement-techniques/making-power-supply-measurements-with-a-vector-network-analyzer/

has the setup for a BNC environment and normal lab power supplies.

Some news:

What it could be is that one sort of caps sat at the shelf for quite a while and drew some forming current. The other was a none-name brand ordered by a large electronics reseller.

[precaud]

- The influence of DC *is* cap brand dependent, as is the SRF. I dont know what causes this. The effect is about 10% of ESR and SRF shift.
- SRFs of electrolytic caps 1000uF/50V depend a *lot* on make. Some large ones from Panasonic were very good, some no-name had a SRF of just a few 100kHz.

Could be. I can't say it doesn't happen; only that I've never seen it (in 30+ years of looking...)

[Wolfgang]

I will let them sit charged for a while and repeat the measurement. Then I'll know, I will post curves when done.

[bson]

Interesting. I have a good HP 4275A with DC Bias option now, so I'll run some comparisons and see if I get the same results as you do.

BTW, I *did* solve the issue I was asking about in the thread, I just forgot to come back and write about it.   

Now its been so long, I can't remember what it was...

One possible experiment is to simply reverse the cap.  If it has different impedance depending on polarization, well then it stands to reason that biasing it is guaranteed to affect the impedance as well.  I've been meaning to try this sometime but just never got around to it...

[precaud]

One possible experiment is to simply reverse the cap.  If it has different impedance depending on polarization, well then it stands to reason that biasing it is guaranteed to affect the impedance as well.  I've been meaning to try this sometime but just never got around to it...

We await your results...

[Wolfgang]

Picotest injectors - yes, they are pricey. If you go for a bundle it gets a bit more reasonable. There is one "feature" of the injector that i did not manage to wrap my head around. The current sense port is "feedforward", ie. the signal is not about what is there, but about what should be there. Current sense output works even with disconnected load. I have on idea why did they designed it this way.  On the other side, it's nice for calibration

10Hz and 1mOhm - it's quite tough. Depending on dynamic range of your VNA, you might probably need to build a preamp. Ideally with differential input, to get rid of the braid error(If you feel like building something like that - let me know, I'd be glad to help - I could use it too, same goes for the current load). If I may ask, why do you need to go so low?  There is usually not much happening...

Apart from two sma(really nice if you can accommodate the space, I use a lot of edge mounted ones), I used diy probes from semirigid coax and some needles(as recommended in "right the first time" book) - it sucked.  I have a new version with spring loaded gold plated tip in works, I'll post pictures when it's done.

I've attached pics of my setup - short semi rigid line +  common mode transformer. Of course it could be improved, ie. directly from coax to bnc(no adapters) and semi flexible coax for the CM transforem(+box). PN of the core is W518-03. Measured are 4x0.1R 0603 in parallel. I'll try to get something smaller, to show you the braid error with this setup. Actually this is quite a bit better than old setup with WE emc ferite core.

Got the same problem. Below a certain terminal voltage, the monitor output is still there, but no actual current is flowing.
There is not a line in the specs about this.