REVIEW - Owon SDS7102 - A look at the SDS series from Owon

[R_G_B_]

My scope has the serial number SDS71021234 I updated it to firmware 3.8.
Its corrupted the text on the display its not chineese text its a scrambled looking graphic instead of letters and numbers. It was on firmware 2.7.1 before I up dated the firmware how do I get it back to this firmware its not on owon website?

[TomC]

R_G_B,

If it was me I would download the firmware again and try to do the update a second time. Based on your serial it seems that you should download the upgrade illustrated on the attachment. As far as other versions of the firmware, I've never tried to go back to an earlier version, so I'm not sure if that would help. I do have some earlier files in my PC as I'm a bit of a hoarder, but not 2.7.1. The earliest I've got is 3.1, if nothing else works and you want to take a chance I could upload it to onedrive.

PS. By the way, Chinese will look like graphics, not letters and numbers.

[R_G_B_]

Thanks TomC I sorted it.

Its the firmware not displaying the chinese text properly it was corrupted. Anyway I did the utility H5 as you described changed to English.

The Volts/Div  goes down to just 20mV I take it this is because of the noise issues?

Thanks

R_G_B

[TomC]

Thanks TomC I sorted it.

Its the firmware not displaying the chinese text properly it was corrupted. Anyway I did the utility H5 as you described changed to English.

The Volts/Div  goes down to just 20mV I take it this is because of the noise issues?

Thanks

R_G_B

With the probe setting in the Ch1 or Ch2 menu set to x10 you can only go down to 20mV/div. If you change the setting to x1 then you can go down to 2mV/Div. This scope doesn't sense the setting of the probe switch automatically.

[R_G_B_]

Yes I was to focused on problems with this and had forgot that I had set the scope probe to x10.

Thanks TOMC.

[VanitarNordic]

Have anybody checked that the waveform update rate problem has solved or not? I think it was maximum 35 per second.

[TomC]

I recently posted an experiment where I explore the possibility of using the SynthUSBII Signal generator and the CPDETLS-4000 power detector to get a better idea of the frequency response of a DSO beyond the manufacturer's specified bandwidth. Hopefully, this knowledge can help the user determine the amplitude of signals that exceed the DSO's specified bandwidth and thus extend the usefulness of inexpensive lower bandwidth DSOs.

The example DSO I used for this experiment is my Owon SDS7102 DSO, so this information may be useful for other SDS7102 owners. If you are interested click on the following link:

https://www.eevblog.com/forum/testgear/synthusbii-usb-rf-signal-generator-cpdetls-4000-rf-power-detector/msg870496/#msg870496

[Hydrawerk]

Have anybody checked that the waveform update rate problem has solved or not? I think it was maximum 35 per second.

That was a specification, not a problem. This scope was introduced in 2010, I think.

[TomC]

I recently posted an experiment where I explore the possibility of using the SynthUSBII Signal generator and the CPDETLS-4000 power detector to get a better idea of the frequency response of a DSO beyond the manufacturer's specified bandwidth. Hopefully, this knowledge can help the user determine the amplitude of signals that exceed the DSO's specified bandwidth and thus extend the usefulness of inexpensive lower bandwidth DSOs.

The example DSO I used for this experiment is my Owon SDS7102 DSO, so this information may be useful for other SDS7102 owners. If you are interested click on the following link:

https://www.eevblog.com/forum/testgear/synthusbii-usb-rf-signal-generator-cpdetls-4000-rf-power-detector/msg870496/#msg870496

I recently updated the Graphs and Spreadsheets associated to this post. If you are interested click on the following link:

https://www.eevblog.com/forum/testgear/synthusbii-usb-rf-signal-generator-cpdetls-4000-rf-power-detector/msg875416/#msg875416

[bob808]

Guys, any idea on the encryption for the files that come in the firmware archive?
I am trying to decrypt them but have no clue on the algorithm used. The keys are in the txt file.

[bob808]

Nevermind, I read some more and I understood that there's a tool in the firmware update package.
The problem is that I'd like to experiment a bit with calibrating the scope (sds6062). It's a bit out and seems like fun.
I managed to start the encryption/decryption tool but it's a mess.
For source I can only select a folder, and for destination only a file. And the decrypt button doesn't do anything actually.
Any pointers from someone who did this?
I only need to download the tx.txt file from the scope and adjust some parameters - reupload - repeat.

[Propretor]

Hi!
Please excuse my bad English. This is Google Translate.
I have heard that last oscilloscope models have a passive cooling system. That is not the cooler in them. Do you have someone photograph of a radiator? Which chip closes the radiator? I want to do, and at its SDS8202 passive cooling system.

[Propretor]

Sharing information on its completions SDS8202

1. Tired of cheap fan noise. I had to change. The original 60h60h10mm, 12V, 0.2A, powered by 8.4V. It was fixed at the bottom of the metal radiator. In order to reach and change, I had to disassemble 90% of the oscilloscope including a trail of the film, which is very much did not want to disconnect.
As a replacement was selected http://www.citilink.ru/catalog/computers_and_notebooks/parts/coolers/944770/
Which had good reviews on work and noise, but had 60h60h12mm sizes.
Despite the fact that there were doubts whether it will get thicker fan and even on top of the metal-housing land (so that you can replace it without total analysis of the oscilloscope), all successfully. Fans 12mm thickness fit overhead. I had just rewire the power connector from the fan, replacing it with the old one.
However, I think this is still a temporary solution, because I do not see anything too much energy-intensive, that is hitting the fan. Only 2 cases, which suggests to put in place an ordinary radiator fan, although the question remains open of the fastening of a radiator.
I would be very grateful to those who have shown the interior of the oscilloscope with a passive cooling system in the new revisions of the oscilloscope.

2. Current 15mA from the battery in the power supply in the off position, I also did not suit, with the result that I have been able to reduce it to 3mkA using SMD diode Schottky B320B, designed for permanent and 3A to 100A per pulse (which has been removed from the motherboard or graphics card).
It looks like this: (1 photo)
Rosin flux, which the power supply board was just filled, it was necessary to wash long and hard alcohol.
The voltage + VDD to the power supply unit connector terminals 5,6 and plug the battery, of course, it dropped to 8.23V. I began to look divider that controls the setting of + VDD. And here I was waiting for the first TH. The scheme, which I was not consistent with my power supply. (Figure 2)
My power supply is labeled PCB-T115-J Rev6 it lacks the LM393, LM358 is used instead of a quad LM124, a resistor, performing the same function are labeled differently, J2 switch is not paired contacts, but in general a lot of differences. However, I managed to find a resistor that is responsible for voltage control - it was R17, which was parallel to the empty space to install R18. the selection method has been found that setting in the ready-made holes resistor denominated 33kOm, managed to do exactly equal to + VDD 8.4V. (Photo 3 of this resistor location showed a red arrow).
However, the scheme is written that is also required to recalculate R34, R38 (the threshold of extinction of the red LED - charge indicator) for a complete revision. But on its power supply analogues of these resistors I found it was not possible. So the question is: Is someone these dividers on its power supply if they have the same PCB-T115-J Rev6 like me.

[vas455]

Hi Friend! who can send Nand Dump for owon sds7102 ?
after the firmware my eds102 i have yellow screen

how do I fix it?

[tautech]

Hi Friend! who can send Nand Dump for owon sds7102 ?
after the firmware my eds102 i have yellow screen

how do I fix it?

Welcome to the forum.

PM member OWON, their details are in this thread:
https://www.eevblog.com/forum/testgear/owon-xds3102a-oscilloscope-unpack-review/

[vas455]

PM member OWON, their details are in this thread:
https://www.eevblog.com/forum/testgear/owon-xds3102a-oscilloscope-unpack-review/

Thanks, but your link for OWON XDS3102A, but i have eds102cv it sds7102 for China

[tautech]

PM member OWON, their details are in this thread:
https://www.eevblog.com/forum/testgear/owon-xds3102a-oscilloscope-unpack-review/

Thanks, but your link for OWON XDS3102A, but i have eds102cv it sds7102 for China

OK, you are new to the forum so I'll make it clearer.
Robin from OWON when registering with EEVblog made his contact details available for us all, including you!
You can personal Message him through the forum or use the email link he's provided.

Contact details are in each of our profiles, Robins profile:
https://www.eevblog.com/forum/profile/?u=119064

Please let us know about the support he offers for your problem.

[vas455]

Thanks!

[vas455]

Problem solved, I used to dump on the other oscilloscope, and added in his own settings

If you have any questions, please contact me by e-mail: Vasiliy455@yandex.ru

[wingel]

Just a little teaser...  I have this dumb idea of porting Linux to my SDS7102 scope and have managed to get a Linux kernel running on Samsung S3C2416 CPU with a working serial port and frame buffer.

That was the easy part.  Adding support for all the other hardware is going to be a bit more tricky.  USB and ethernet ought to be fairly easy, they are either standard components inside the CPU or chips with exposed pins.  Figuring out how to program the FPGA and how the FPGA is connected to the ADC and the other DDR memory is going to be a lot harder since all those chips are BGA packages and I can't probe the pins.

This thread is really long and I haven't read every post yet and might have missed some so I'm wondering if anyone else has managed to find out interesting things about the hardware.  Has anyone done a dissassembly of the firmware and figured out how to program the FPGA or just happens to have access to an XRAY machine and can take a picture of the traces embedded in the PCB and under the BGA packages?

[nctnico]

I'd try and disassemble the original firmware to figure out how to access the acquisition hardware. It won't be easy though but if the hardware is decent others may chime in if you create a wiki-ish website about the project somewhere.

[wingel]

The stuff in the firmware isn't that much of a problem.  I can probably write most of that from scratch, it's mostly a couple of GPIO pins and a few SPI or I2C busses.  To program the FPGA they are most probably using slave parallel mode or JTAG and I'll probably have to a bit of disassembly to figure out how that works.

But all the interesting stuff, how the FPGA is connected to the ADC and to the DRAM is hidden in the FPGA bitstream.  And I have no idea at all how to disassemble that one.

[wingel]

Since I don't have a life I've written a few blog posts about reverse engineering the SDS7102 and getting Linux to boot on it:

http://blog.weinigel.se/2016/05/01/sds7102-hacking.html
http://blog.weinigel.se/2016/05/06/sds7102-hacking-2.html
http://blog.weinigel.se/2016/05/07/linux-on-sds7102.html

[pxl]

Since I don't have a life I've written a few blog posts about reverse engineering the SDS7102 and getting Linux to boot on it:

http://blog.weinigel.se/2016/05/01/sds7102-hacking.html
http://blog.weinigel.se/2016/05/06/sds7102-hacking-2.html
http://blog.weinigel.se/2016/05/07/linux-on-sds7102.html

It is really amazing, nice!

[wingel]

A lot of more words about the SDS7102 scope :-)

http://blog.weinigel.se/2016/05/14/disassembling-the-sds7102-bootloader.html
http://blog.weinigel.se/2016/05/15/sds7102-file-system.html
http://blog.weinigel.se/2016/05/16/sds7102-os-disassembly.html

I'm a bit stuck now though.   As far as I can tell they use the Xilinx MIG for talking to the DDR2 memory on bank 3 of the FPGA, but there seems to be no free pin for the RZQ signal which is in direct violation of the Xilinx MIG design rules.  But I'm getting ahead of myself.  I think I have enough material for another four blog posts or so and will get to that later.