Thank you for the teardown and the explanation of the RF path!
Note that KF5OBS hasn't described the signal path correctly in the video.
He's missed out the whole existence of the first conversion stage in the video and he seems to think it downconverts direct to a 140MHz IF. This is clearly incorrect. The PLL/LO section that confused him part way through the video is actually the LO for the first conversion stage.
I'm hoping that Shahriar from The SignalPath Blog also does a teardown video because it would be nice to see closeup images of the first IF section with its choice of IF1 filter ranges
These got missed in the KF5OBS video.
KF5OBS also says that the ADC samples at 125Msps in the video which is also incorrect. It appears to sample at 112Msps (because of the 112MHz clock oscillator module seen in the video) and this makes much more sense if you are trying for a 40MHz BW centred on a 140MHz IF. This scheme wouldn't work at 125Msps.
I put this info on his youtube channel comments section (plus a load more background info about the signal path) but he has decided to delete all the info from me. Maybe he thinks he is right and I'm wrong?