Author Topic: USB logic analyzer - what's the current "favorite" for ~150$? Hantek 4032L? (Read 16346 times)

Andy99 · « **Reply #25 on:** July 06, 2018, 03:46:54 pm »

I will add my 2cents about current status 4032l+sigrok+PV.
- External clock feature is already in mainline. It's available only for newer version of FPGA (>0). (FPGA could be updated without any problems.) One of the problem of external clock is, that upper layer doesn't know, which time based was captured. You can select only nearest frequency from drop-down menu. I have reported this problem in PV, and hope so, that will be fixed.
- 4032l has HW support from different trigger eg. BUS value, time... . These options are not available in PV now. After that, I could take a look on sigrok with implementation.
- USBXI could be implemented on sigrok, but I didn't find someone, who is requesting this feature.

Regarding to DSlogic, they have separated stream from mainline PV, which have better support. https://github.com/DreamSourceLab/DSView

SMB784 · « **Reply #26 on:** July 06, 2018, 03:59:09 pm »

Quote from: toli on July 06, 2018, 03:32:23 pm

Question is if this 0-5V range also holds for the CLK input vs just the 16 data channels. I think I've seen somewhere a mention that the CLK input is at 3.3V constant, but I can't seem to recall where it was.

BTW, you don't actually need >100MHz square wave to test these parameters. The threshold can be checked at low speed quite easily (and if I'm honest that's the more interesting parameter for me at the moment). For the maximum frequency test a sin wave will suffice. At these frequencies the rise time will limit square waves and they will look more like a sine anyway unless you take extra good care of the test setup. I've actually used sin wave input at 100MHz to the Cypress FX3 IC as a sampling clock because of a similar limitation, and its works like a charm with no issues at all (just add VDD/2 DC offset obviously ).

I would be very surprised if the clock input is limited at 3.3V. I will see if I can find out whether or not this is true.

I'll try the sine wave option, the offset will be the hard part though. I have a 1GHz signal generator, so I'll play around and see what I can come up with.

Rolo · « **Reply #27 on:** July 06, 2018, 04:00:23 pm »

It will not fit the $150 budget for 16 channels but as a tip to all, Saleae does offer significant discounts on their products. I recently bought a Logic8, got the Enthusiast discount after one request trough their "contact us" form.

https://blog.saleae.com/saleae-discounts/

toli · « **Reply #28 on:** July 07, 2018, 05:55:08 am »

Rolo, I have experience with their tools, they are very nice indeed. However, the price for something that will fit my needs is way out of the budget, so I'm not even considering them.

Regarding DSlogic - I have heard back from DSlab support, and they have confirmed the external clock is fixed at 3.3V level unfortunately.
I will say that the fact they have replied within a few hours is definitely a point in their favor. I haven't heard back from Hantek yet, and I've emailed them over 3 days ago.

maginnovision · « **Reply #29 on:** July 07, 2018, 06:07:52 am »

Quote from: toli on July 07, 2018, 05:55:08 am

Rolo, I have experience with their tools, they are very nice indeed. However, the price for something that will fit my needs is way out of the budget, so I'm not even considering them.

Regarding DSlogic - I have heard back from DSlab support, and they have confirmed the external clock is fixed at 3.3V level unfortunately.
I will say that the fact they have replied within a few hours is definitely a point in their favor. I haven't heard back from Hantek yet, and I've emailed them over 3 days ago.

I had emailed hantek some time ago and I think it took a week or two. The biggest difference is they seem to shift most of that sort of responsibility to dealers since they don't, as far as I know, sell directly. If you have issues after you buy one, or even now, maybe contact them. Even if they aren't responsive it'll probably be quicker turn around.

toli · « **Reply #30 on:** July 07, 2018, 07:11:17 am »

I'm not sure sellers of this item can answer technical questions though.

BTW, I've also asked DSlab about the maximum frequency at the external clock port, specifically asking if this can be stretched to 100MHz. They have replied with "about 50MHz". No idea if this is a "safe margin" sort of answer, or practical limit.
I can actually live with 50MHz, this is the fastest clock I've ever used for applications that need external clock for sampling. The fact I will need an external level shifter (which will result in different delay between clock and data) isn't great though.

I think I understand the abilities of the DSlogic Plus well now. Be it the software(s) abilities, and the HW limitations. It is actually something I can live with quite comfortably (except for the need for CLK level shifter that is somewhat annoying).

The Hantek which still seems to have better HW is somewhat of an unknown still.
First unknown is the practical limit on input BW of the signals. The 2.54mm header seems like it has GND on only one edge of the connector. This isn't optimal for digital signal with sharp edges. I'm also not sure what the AST0/1 connections are, I'd expect to see GND in this place:
https://sigrok.org/wimg/d/d7/Hantek4032L_BoxPortSide.png
So no idea how it'll handle a 100MHz clock/data despite the claimed 150MHz.
Second question has to do with this post I've seen online:
https://plus.google.com/113862568356151601304/posts/hknHqNw9Pbc
I couldn't find any other note of it, so there is always the possibility I'll run into such problems too.

Perhaps it would be better to "settle" for the DSlogic Plus, as they say "better the devil you know" $:-\$

toli · « **Reply #31 on:** July 13, 2018, 05:38:45 am »

There is some update with this topic, so I'd like to share my findings to help other forum members who might be looking for a USB LA in the future. I know I've had some trouble finding practical information to make the decision.

To sum this up, my main concern with the 4032L following all the other info I've received from the helpful member of this forum has been the actual maximum signal frequency it can handle. The claimed 150MHz seemed too optimistic for the way the output connector is arranged (with GND signal on only one edge of the connector). Lucky for me, member maginnovision was very helpful, and went ahead an ordered a few parts to allow him to test with various frequencies (and I would l like to take the opportunity to thank him once more for all the help). My concern was that the highest frequency won't even reach 100MHz (as I've posted in the last post), and that there are significant differences between channels since ch0 is close to the GND return path, while ch16 is very far from it.
maginnovision did quite a few measurements, but I won't detail them all, instead I will jump to the punch line. According to his findings, with the original leads provided with the 4032L, the maximum frequency you can use is ~90MHz on the channels closest to the GND pins, and ~60MHz on these at the other edge of the connector. This is all with only a single channel used at a time, and will obviously get somewhat worse with multiple channels used at the same time.

In comparison, as can be observed in the video I've posted in one of my previous posts, the DSlogic Plus with the shielded leads seems to support up to 200MHz frequency at the input. I don't need to go that high, only 50-100MHz at most, but I'd like to minimize the chance of missed edges, so the DSlogic seemed like the better option in this regard.
The main issue for me with the DSlogic remains the constant threshold on the CLK pin. However, this I can solve using a level shifter IC. The lower channel count is a point against it, but I can live with it for the foreseeable future. Therefore, I've decided in its favor and placed an order for the DSlogic plus from their website. I've contacted them via email and they have confirmed they are sending the Plus model, despite the site not being updated yet.

I would like to thank you all once more for the help, it was crucial in helping me make an educated decision instead of going on a hunch

1anX · « **Reply #32 on:** July 13, 2018, 07:40:47 am »

Thanks for all the feedback Toli!
I thought the DSLogic Plus along with their software was pretty good bang for the buck.
I think also that you may have helped a number of others wondering what to buy with your discussion and input in this thread.

abyrvalg · « **Reply #33 on:** July 15, 2018, 09:22:48 am »

I have both DSLogic Plus and Hantek 4032L here for comparison. What test method should I use to determine the bandwidth? Feeding a square wave and counting the edges? Or scoping the channels at FPGA inputs? Thinking about fitting a DSLogic’s test lead to 4032L also.

toli · « **Reply #34 on:** July 15, 2018, 09:27:33 am »

Yes, feed the signal and check what frequency you can use without missing edges/getting false edges.

I was also considering of getting the 4032L and printing a small PCB with proper GND flood and headers for shielded/twisted leads. However, after all the info I've received I just felt like the DSlogic is a safer bet for my current needs.

abyrvalg · « **Reply #35 on:** July 17, 2018, 02:56:12 pm »

A quick and dirty setup touching an FPGA devboard's 100MHz oscillator pad with HT4032L's test lead shows no problems acquiring a 100MHz signal. 400MS/s, 1M samples gives a stable 262144 (1MiB/4 exactly) edge count regardless of the channel used (tried A0 and A15 on the opposite sides of the connector). I have no generator to test higher frequencies quickly, but I'll cook some FPGA config for this (among with some pattern generation to test the external clocking).

Edit: 262144 is the number of periods, not edges (I had both measurements turned on).

maginnovision · « **Reply #36 on:** July 17, 2018, 03:11:17 pm »

Quote from: abyrvalg on July 17, 2018, 02:56:12 pm

A quick and dirty setup touching an FPGA devboard's 100MHz oscillator pad with HT4032L's test lead shows no problems acquiring a 100MHz signal. 400MS/s, 1M samples gives a stable 262144 (1MiB/4 exactly) edge count regardless of the channel used (tried A0 and A15 on the opposite sides of the connector). I have no generator to test higher frequencies quickly, but I'll cook some FPGA config for this (among with some pattern generation to test the external clocking).

Try 20MS and attach a screenshot.

abyrvalg · « **Reply #37 on:** July 17, 2018, 03:59:17 pm »

Yeah, getting the false edges now, 10485800+-2 instead of 10485760, both A0 or A15.

abyrvalg · « **Reply #38 on:** July 19, 2018, 04:47:29 pm »

DSLogic's result: stable 9998362 edges in 20M samples (DSLogic's M is 10^6, not 2^20). Unrelated clocks runaway?

Funny, it took more time to get the edge count from DSLogic's "polished" software. You can't set a measurement cursor to the first/last sample just by dragging it to the edge - on the left side it happily goes to some hidden negative time area and gets lost there, on the right side you need a highest detail zoom to reach the edge and then the measurement refuses to count the edges silently (solution: it doesn't like the right cursor being at the last sample, move it left a bit).

toli · « **Reply #39 on:** July 19, 2018, 04:50:01 pm »

The clocks are definitely not matched well enough to get absolute accuracy at such long record length. The only question is at what point you can see missed edges over a limited period of time.
To get "perfect" sync you'll need to sample with the external clock pins.

Edit:
just in case it wasn't clear what I meant to say, I'll add a few more words. If the clocks are even 1ppm out, you will get 1 cycle missed over 1Mcycles of these clocks. So this is absolutely understandable that the number isn't the round number you expect.
However, if you can find the ratio of the two clocks by sampling a signal that is low enough in frequency so that it is always detected properly, you can count on this ratio to remain almost unchanged for a short period of time. You can then use this info to try ramping up the input frequency until the counted number deviates noticeably from the expected number with the actual frequency ratio of the two instruments.

TK · « **Reply #40 on:** July 19, 2018, 06:07:45 pm »

If you need state mode sampling (match signal that changes based on a fixed clock) you need to use the external clock input. The logic analyzer will sample at every clock edge (rise or fall). If you are sampling in timing mode, you are going to repeat a certain state and miss others. It is not going to capture perfectly every single clock edge rise or/and fall.

wpwrak · « **Reply #41 on:** July 21, 2018, 09:27:24 pm »

Quote from: abraxa on July 05, 2018, 09:25:43 pm

Not even a single line of usable code because they not only didn't want to work with us, they actively sabotaged any effort of upstreaming anything.

Hmm, if they made derivative works of code that was distributed to them under the GPL, and refuse to make their changes available, then you may want to have a chat with the FSF/FSFE. Companies that thought they could get away with disregarding the GPL have been taken to court, and lost. See also https://en.wikipedia.org/wiki/Gpl-violations.org

Of course, if you're talking about code that isn't a derivative work, or if the original was licensed under different terms, then the situation would be different.

- Werner

wpwrak · « **Reply #42 on:** July 21, 2018, 09:34:34 pm »

Quote from: abyrvalg on July 17, 2018, 02:56:12 pm

A quick and dirty setup touching an FPGA devboard's 100MHz oscillator pad with HT4032L's test lead shows no problems acquiring a 100MHz signal.

A more accurate test would be to gate the signal to have an exactly known number of cycles. Then you can just trigger on the first edge, grab the sequence, check that the recording isn't cut off, have the cycles counted, and see if the numbers match. If you can use a PLL as clock source, you can also vary the frequency to see when exactly things get interesting.

- Werner

abyrvalg · « **Reply #43 on:** July 22, 2018, 08:33:07 am »

Oops, I didn’t posted the really important numbers: the edge count remained stable over ~10 attempts with DSLogic, but with 4032L there were deviations by more than 100 edges sometimes. Anyway, I’m planning to test it with a clock+counter signals in state mode later.

DSLogic code is open and being updated regularly, it’s just refactored in a way hindering automated merging - not a license violation formally, but looks a bit unfair to the original project.

toli · « **Reply #44 on:** July 26, 2018, 03:41:33 pm »

Just a small update, the DSlogic Plus has arrived here very quickly. Its much lighter than I've expected, but seems quite well made. The shielded leads are very nice, even if a bit too stiff. The hooks (as always) are of rather low quality, I will have to look for something nicer to get.

One thing I didn't like in v0.99 of DSview is the change from sample length to sample time. While it makes more sense in many cases, for some of my use cases it would have been better to have it as it was in older version. I hope they will allow users to select which they want to see in the next version.
edit:
seems like the second issue was a misunderstanding and not a bug. Post has been revised.

dpenev · « **Reply #45 on:** July 27, 2018, 03:06:07 pm »

Please post the issues in there github repository

Sent from my MI NOTE Pro using Tapatalk

toli · « **Reply #46 on:** July 27, 2018, 03:12:25 pm »

I've modified my previous post. The issue with the trigger appears to be the way they've meant for it to work, simply not what I'm used to.
The ability to select samples length instead of time is something I've asked them to add via email, but I'm not sure if they'll implement this. In the mean time I'm using v0.98 instead.

CB · « **Reply #47 on:** June 28, 2019, 08:41:35 am »

I understand the sentiment that using an open-sourced and GPL'ed package without giving back might seem "wrong" to some people, but on the other hand, this is the whole point of the public license. Most of the Internet runs on software of this kind, and does so without paying anything to the original developers (think Linus Torvalds or Richard Stallman amongst so many others).

Where the developers of Dream Source Labs fell down was in making use of Sigrok without including the GPL license. When called out on this, they subsequently fixed their errors, and made the source code available.

We shouldn't be angry because that's the way it is supposed to work.

giubin · « **Reply #48 on:** July 05, 2019, 08:29:09 am »

Quote from: 17_29bis on July 05, 2018, 08:17:20 pm

Bad things: the GUI (sigrok fork/ or "being inspired by sigrok") DSView v0.9.7.1 (2 or so years old) was the last public release (but I still prefer ti very much to the original sigrok GUI). The support forum is almost dead, I had a difficult time to setup an advanced trigger but found a work around through the usage of external trigger.

I've just ask trough email at DreamSourceLab for the DSLogic Plus and it's support, and this is the reply:

We are active, and will keep improving our project.
DSView software will be updated to be v1.0.0 version in the near feature.

Thanks,
The DreamSourceLab Tema

lfldp · « **Reply #49 on:** December 27, 2019, 10:13:42 am »

hello ive question
i have dslogic pro version (this is 50mhz version i think)
i cant get sniff 50mhz SPI FLASH communication by using it
mostly i getting junk no MOSI data only MISO when i capture on 100mhz bandwitch i getting MISO/MOSI result but is still not correct SPI log
what could be wrong in my setup ?


EEVblog Main Site	EEVblog on Youtube	EEVblog on Twitter	EEVblog on Facebook	EEVblog on Odysee

Author Topic: USB logic analyzer - what's the current "favorite" for ~150$? Hantek 4032L? (Read 16346 times)

Share me