Using Sigrok on Hantek 4032L

[dexters_lab]

Does anyone have any experience getting Sigrok to work with the Hantek 4032L logic analyser on Windows 7

no matter how much fiddling i do with zdiag, pulseview etc i can't get it to show up in the device list

the Hantek software works ok

any ideas? 

[Daruosha]

Just out of curiosity: Does it work with Saleae Loginc software?

[dexters_lab]

Their website says the hantek is supported

[Daruosha]

Their website says the hantek is supported

I doubt the 32 channel version works with Saleae Login, Does Saleae even support 32 channels?

[abyrvalg]

Not sure is this relevant to your Win7 case or not (I have Win8.1 x64), but I've tried today's PulseView version and it works:
Install PulseView
Run bundled Zadig
Check Options->List all devices
Select 4032L in device list
Driver -> WinUSB (v6.1.7600.16385)
Install driver
Run PulseView - it shows Hantek 4032L selected immediately

Check the driver type/version of 4032L in Device Manager before and after Zadig - it should change from ODM/hieroglyphs to libwdi.

Anyway, the support level from Sigrok is very basic at this moment, I would say it is a "Work in progress" rather than "Supported", but they work on 4032L (I'm taking part in some testing), hope to see more features soon.

Btw, Hantek doesn't advertise that, but they are releasing firmware updates for 4032L (you need to mail to their support to get one). I've got an FPGA update that enabled external clocking on my old unit.

[dexters_lab]

Not sure is this relevant to your Win7 case or not (I have Win8.1 x64), but I've tried today's PulseView version and it works:
Install PulseView
Run bundled Zadig
Check Options->List all devices
Select 4032L in device list
Driver -> WinUSB (v6.1.7600.16385)
Install driver
Run PulseView - it shows Hantek 4032L selected immediately

Check the driver type/version of 4032L in Device Manager before and after Zadig - it should change from ODM/hieroglyphs to libwdi.

Anyway, the support level from Sigrok is very basic at this moment, I would say it is a "Work in progress" rather than "Supported", but they work on 4032L (I'm taking part in some testing), hope to see more features soon.

Btw, Hantek doesn't advertise that, but they are releasing firmware updates for 4032L (you need to mail to their support to get one). I've got an FPGA update that enabled external clocking on my old unit.

thanks, i have been through the zadig steps but nothing shows in the pulseview app, pictures attached...

i don't know what 'ODM/hieroglyphs' are, sorry!

is there a specific forum or place to go and get some help?

[abraxa]

It's unfortunate that you're running into these issues and I wish I could provide assistance but I neither possess a Hantek device nor do I use PV on Windows, so I can only guess at this point. The best way to tell what PV is doing is to run pulseview.exe from the command line with the "-l 5" parameter and showing us the logs (Settings->Logging) after you attempted to scan for your device. (We'll create a shortcut in the start menu for this in the future.)

As for support, we have several ways to reach us: mailing list (https://lists.sourceforge.net/lists/listinfo/sigrok-devel), google+ (https://plus.google.com/communities/109843678338531936878) and IRC (http://webchat.freenode.net/?channels=%23sigrok&uio=MT1mYWxzZQ9a).
The mailing list is easiest but slowest while IRC is less convenient for those not used to IRC but certainly the quickest way to get a response.

[Andy99]

I am one of the 4032l@sigrok developers. You can use changes from last commits of libsigrok. I don't know, if they added those changes into last libsigrok release. Of course, You can build it by yourself. If you are not able to do it, I can support you as well .

Andy

[dexters_lab]

thanks Andy99 and to abraxa

i have actually stopped using the hantek at the moment and instead i am using some USB/RS232 converters which is actually a better solution for me anyway

i don't have a clue about building software i am afraid, it might be better if i just download the latest version when i next come to use the hantek

thank you for the efforts in getting sigrok working on the hantek BTW, the original hantek software is bloody awful! I have long been hoping for some alternative.

[Uwe Hermann]

Hi, the fixes by Andy99 (affected all Windows and some Linux systems) are merged indeed, and already available in the latest Windows installers we provide. I just downloaded the PulseView installer 5 minutes ago and did a few quick tests on Windows 10, 64bit, everything seems to work fine.

https://sigrok.org/wiki/Downloads

Cheers!

[dexters_lab]

Hi, the fixes by Andy99 (affected all Windows and some Linux systems) are merged indeed, and already available in the latest Windows installers we provide. I just downloaded the PulseView installer 5 minutes ago and did a few quick tests on Windows 10, 64bit, everything seems to work fine.

https://sigrok.org/wiki/Downloads

Cheers!

thanks, i'll give it another try when i get a chance

[dexters_lab]

i just took a few moments to re-install and still no luck

like before i have run Zadig and installed the driver but still no device shows in Pulseview

i've attached some screens and a log from pulseview, hopefully you can spot something?

Code: [Select]

sr: backend: libsigrok 0.6.0-git-2bd5d17/4:0:0 (rt: 0.6.0-git-2bd5d17/4:0:0).
sr: backend: Libs: glib 2.50.2 (rt: 2.50.2/5002:2), libzip 1.1.3, libserialport 0.1.1/1:0:1 (rt: 0.1.1/1:0:1), libusb-1.0 1.0.20.11003-rc3, libftdi 1.2.
sr: backend: Host: i686-w64-mingw32.static.posix, little-endian.
sr: backend: SCPI backends: TCP, serial, USBTMC.
sr: backend: Firmware search paths:
sr: resource: SIGROK_FIRMWARE_DIR environment variable not set, ignoring.
sr: backend: - C:\Users\DELETED\AppData\Local\sigrok-firmware
sr: backend: - C:\ProgramData\sigrok-firmware
sr: backend: - C:\Users\Public\Documents\sigrok-firmware
sr: backend: - C:\Program Files (x86)\sigrok\PulseView\share\sigrok-firmware
sr: backend: - C:\Program Files (x86)\sigrok\PulseView\share\sigrok-firmware
sr: backend: Sanity-checking all drivers.
sr: backend: Sanity-checking all input modules.
sr: backend: Sanity-checking all output modules.
sr: backend: Sanity-checking all transform modules.
srd: libsigrokdecode 0.6.0-git-cb67584/4:0:0 (rt: 0.6.0-git-cb67584/4:0:0).
srd: Libs: glib 2.50.2 (rt: 2.50.2/5002:2), Python 3.4.4 / 0x30404f0 (API 1013, ABI 3).
srd: Host: i686-w64-mingw32.static.posix, little-endian.
srd: Initializing libsigrokdecode.
srd: Adding 'C:\Program Files (x86)\sigrok\PulseView\share\libsigrokdecode\decoders' to module path.
srd: Adding 'C:\Program Files (x86)\sigrok\PulseView\share\libsigrokdecode\decoders' to module path.
srd: Protocol decoder search paths: - C:\Program Files (x86)\sigrok\PulseView\share\libsigrokdecode\decoders - C:\Program Files (x86)\sigrok\PulseView\share\libsigrokdecode\decoders
srd: Python system search paths: - C:\Program Files (x86)\sigrok\PulseView\share\libsigrokdecode\decoders - C:\Program Files (x86)\sigrok\PulseView\share\libsigrokdecode\decoders - C:\Program Files (x86)\sigrok\PulseView\python34.zip - C:\Program Files (x86)\sigrok\PulseView\DLLs - C:\Program Files (x86)\sigrok\PulseView\lib - C:\Program Files (x86)\sigrok\PulseView
sr: hwdriver: Scan found 0 devices (asix-sigma).
sr: hwdriver: Scan found 0 devices (chronovu-la).
sr: hwdriver: Scan found 1 devices (demo).
sr: hwdriver: Scan found 0 devices (dreamsourcelab-dslogic).
sr: hwdriver: Scan found 0 devices (ftdi-la).
sr: hwdriver: Scan found 0 devices (fx2lafw).
sr: hwdriver: Scan found 0 devices (gwinstek-gds-800).
sr: hwdriver: Scan found 0 devices (hameg-hmo).
sr: hwdriver: Scan found 0 devices (hantek-4032l).
sr: hwdriver: Scan found 0 devices (hantek-6xxx).
sr: hwdriver: Scan found 0 devices (hantek-dso).
sr: hwdriver: Scan found 0 devices (ikalogic-scanalogic2).
sr: hwdriver: Scan found 0 devices (ikalogic-scanaplus).
sr: hwdriver: Scan found 0 devices (lecroy-logicstudio).
sr: hwdriver: Scan found 0 devices (lecroy-xstream).
sr: hwdriver: Scan found 0 devices (ols).
sr: hwdriver: Scan found 0 devices (p-ols).
sr: hwdriver: Scan found 0 devices (rigol-ds).
sr: hwdriver: Scan found 0 devices (saleae-logic-pro).
sr: hwdriver: Scan found 0 devices (saleae-logic16).
sr: hwdriver: Scan found 0 devices (siglent-sds).
sr: hwdriver: Scan found 0 devices (sysclk-lwla).
sr: hwdriver: Scan found 0 devices (yokogawa-dlm).
sr: hwdriver: Scan found 0 devices (zeroplus-logic-cube).
sr: device: demo: Opening device instance.
sr: hwdriver: sr_config_list(): key 30002 (pattern) sdi 01942E60 cg A0 -> ['square', 'sine', 'triangle', 'sawtooth']
sr: hwdriver: sr_config_get(): key 30002 (pattern) sdi 01942E60 cg A0 -> 'square'
sr: hwdriver: sr_config_list(): key 30002 (pattern) sdi 01942E60 cg A1 -> ['square', 'sine', 'triangle', 'sawtooth']
sr: hwdriver: sr_config_get(): key 30002 (pattern) sdi 01942E60 cg A1 -> 'sine'
sr: hwdriver: sr_config_list(): key 30002 (pattern) sdi 01942E60 cg A2 -> ['square', 'sine', 'triangle', 'sawtooth']
sr: hwdriver: sr_config_get(): key 30002 (pattern) sdi 01942E60 cg A2 -> 'triangle'
sr: hwdriver: sr_config_list(): key 30002 (pattern) sdi 01942E60 cg A3 -> ['square', 'sine', 'triangle', 'sawtooth']
sr: hwdriver: sr_config_get(): key 30002 (pattern) sdi 01942E60 cg A3 -> 'sawtooth'
sr: hwdriver: sr_config_list(): key 30002 (pattern) sdi 01942E60 cg Logic -> ['sigrok', 'random', 'incremental', 'walking-one', 'walking-zero', 'all-low', 'all-high', 'squid']
sr: hwdriver: sr_config_get(): key 30002 (pattern) sdi 01942E60 cg Logic -> 'sigrok'
sr: hwdriver: sr_config_get(): key 50001 (limit_samples) sdi 01942E60 cg NULL -> uint64 0
sr: hwdriver: sr_config_set(): key 50001 (limit_samples) sdi 01942E60 cg NULL -> uint64 1000000
sr: hwdriver: sr_config_get(): key 50001 (limit_samples) sdi 01942E60 cg NULL -> uint64 1000000
sr: hwdriver: sr_config_list(): key 30000 (samplerate) sdi 01942E60 cg NULL -> {'samplerate-steps': }
sr: hwdriver: sr_config_get(): key 30000 (samplerate) sdi 01942E60 cg NULL -> uint64 200000
sr: hwdriver: sr_config_list(): key 30000 (samplerate) sdi 01942E60 cg NULL -> {'samplerate-steps': }
sr: hwdriver: sr_config_get(): key 30000 (samplerate) sdi 01942E60 cg NULL -> uint64 200000
sr: hwdriver: sr_config_list(): key 30002 (pattern) sdi 01942E60 cg A0 -> ['square', 'sine', 'triangle', 'sawtooth']
sr: hwdriver: sr_config_get(): key 30002 (pattern) sdi 01942E60 cg A0 -> 'square'
sr: hwdriver: sr_config_list(): key 30002 (pattern) sdi 01942E60 cg A1 -> ['square', 'sine', 'triangle', 'sawtooth']
sr: hwdriver: sr_config_get(): key 30002 (pattern) sdi 01942E60 cg A1 -> 'sine'
sr: hwdriver: sr_config_list(): key 30002 (pattern) sdi 01942E60 cg A2 -> ['square', 'sine', 'triangle', 'sawtooth']
sr: hwdriver: sr_config_get(): key 30002 (pattern) sdi 01942E60 cg A2 -> 'triangle'
sr: hwdriver: sr_config_list(): key 30002 (pattern) sdi 01942E60 cg A3 -> ['square', 'sine', 'triangle', 'sawtooth']
sr: hwdriver: sr_config_get(): key 30002 (pattern) sdi 01942E60 cg A3 -> 'sawtooth'
sr: hwdriver: sr_config_list(): key 30002 (pattern) sdi 01942E60 cg Logic -> ['sigrok', 'random', 'incremental', 'walking-one', 'walking-zero', 'all-low', 'all-high', 'squid']
sr: hwdriver: sr_config_get(): key 30002 (pattern) sdi 01942E60 cg Logic -> 'sigrok'
sr: hwdriver: sr_config_get(): key 50001 (limit_samples) sdi 01942E60 cg NULL -> uint64 1000000
sr: hwdriver: sr_config_list(): key 30000 (samplerate) sdi 01942E60 cg NULL -> {'samplerate-steps': }
sr: hwdriver: sr_config_get(): key 30000 (samplerate) sdi 01942E60 cg NULL -> uint64 200000
sr: hwdriver: Scan found 0 devices (hantek-4032l).
sr: hwdriver: Scan found 0 devices (hantek-4032l).
sr: hwdriver: Scan found 0 devices (hantek-4032l).
sr: hwdriver: sr_config_list(): key 30002 (pattern) sdi 01942E60 cg A0 -> ['square', 'sine', 'triangle', 'sawtooth']
sr: hwdriver: sr_config_get(): key 30002 (pattern) sdi 01942E60 cg A0 -> 'square'
sr: hwdriver: sr_config_list(): key 30002 (pattern) sdi 01942E60 cg A1 -> ['square', 'sine', 'triangle', 'sawtooth']
sr: hwdriver: sr_config_get(): key 30002 (pattern) sdi 01942E60 cg A1 -> 'sine'
sr: hwdriver: sr_config_list(): key 30002 (pattern) sdi 01942E60 cg A2 -> ['square', 'sine', 'triangle', 'sawtooth']
sr: hwdriver: sr_config_get(): key 30002 (pattern) sdi 01942E60 cg A2 -> 'triangle'
sr: hwdriver: sr_config_list(): key 30002 (pattern) sdi 01942E60 cg A3 -> ['square', 'sine', 'triangle', 'sawtooth']
sr: hwdriver: sr_config_get(): key 30002 (pattern) sdi 01942E60 cg A3 -> 'sawtooth'
sr: hwdriver: sr_config_list(): key 30002 (pattern) sdi 01942E60 cg Logic -> ['sigrok', 'random', 'incremental', 'walking-one', 'walking-zero', 'all-low', 'all-high', 'squid']
sr: hwdriver: sr_config_get(): key 30002 (pattern) sdi 01942E60 cg Logic -> 'sigrok'
sr: hwdriver: sr_config_get(): key 50001 (limit_samples) sdi 01942E60 cg NULL -> uint64 1000000
sr: hwdriver: sr_config_list(): key 30000 (samplerate) sdi 01942E60 cg NULL -> {'samplerate-steps': }
sr: hwdriver: sr_config_get(): key 30000 (samplerate) sdi 01942E60 cg NULL -> uint64 200000
sr: resource: SIGROK_FIRMWARE_DIR environment variable not set, ignoring.

[abyrvalg]

Strange. Check that your host controller is not NEC/Renesas (see the very beginning of this: https://github.com/libusb/libusb/wiki/Windows). Or try the other compatible driver from Zadig: libusbK.

[Daruosha]

I can confirm that the Hantek 4032L works beautifully with sigrok (on both Windows and Mac OSX) and i tossed the official (crap) software.

[dexters_lab]

i never managed to get mine to work 

[maginnovision]

I got mine to work as well, but windows 10. If only sigrok didn't crash on high memory sampling, and decoding it'd be ok. Still lose advanced trigger setup compared to the original software. If I weren't using 4k screens EVERYWHERE I would just use the hsntek software. It's not perfect but does what I'd need if I could see the data.

[dexters_lab]

in frustration i tried it on my old Win7 laptop yesterday and it does work so i do have a working option, there must be something on my main system it doesn't like

[Alexel]

Hi Guys.
I need to use a trigger in the Hantek 4032L to start the capture, but the current version of PV does not allow this.
I thought to solve this problem using sigrok-cli, but I can not start the capture.
Tried different options, for example such -

Code: [Select]

sigrok-cli --loglevel 3 --driver hantek-4032l --config 'samplerate = 10MHz: limit_samples = 2048: continuous = off: triggermatch = e: captureratio = 5' --output-file test1.srI understand that there are not enough parameters, for example the channel number for the trigger, but I do not understand how to describe it.

Could you give an example of running sigrok-cli using a trigger.

Thank you!

[abraxa]

I need to use a trigger in the Hantek 4032L to start the capture, but the current version of PV does not allow this.

PV does not allow... what exactly? What does "current version" mean to you?

I thought to solve this problem using sigrok-cli, but I can not start the capture.
Tried different options, for example such -

Code: [Select]

sigrok-cli --loglevel 3 --driver hantek-4032l --config 'samplerate = 10MHz: limit_samples = 2048: continuous = off: triggermatch = e: captureratio = 5' --output-file test1.srI understand that there are not enough parameters, for example the channel number for the trigger, but I do not understand how to describe it.

Could you give an example of running sigrok-cli using a trigger.

From the sigrok-cli manpage:

Code: [Select]

-t, --triggers <triggerlist>
    A comma-separated list of triggers to use, of the form <channel>=<trigger>. You can use the name or number of the channel, and the trigger itself is a series of characters:

    0 or 1: A low or high value on the pin.
    r or f: A rising or falling value on the pin. An r effectively corresponds to 01.
    e: Any kind of change on a pin (either a rising or a falling edge).

    Not every device supports all of these trigger types. Use the --show command to see which triggers your device supports.

btw, I'm not really sure whether using spaces to separate the settings for --config is supported. In case your settings aren't honored, I'd try removing the spaces.

[Alexel]

Thanks for the answer!

What does "current version" mean to you?

I meant the version that is available now for download at https://www.sigrok.org/wiki/Downloads

Code: [Select]

Windows:
Nightly installer binaries:
pulseview-NIGHTLY-32bit-static-release-installer.exe (debug build)
sigrok-cli-NIGHTLY-32bit-static-release-installer.exe (debug build)
Settings:


After many experiments, I managed to get the working keys:
sigrok-cli --loglevel 2 --driver hantek-4032l --config samplerate=50MHz --samples=1000000 --channels A0=D0,A1=CLK,A2=CMD --triggers CLK=e --output-file test1.sr

But failed to set voltage_threshold, to the keys
sigrok-cli --loglevel 2 --driver hantek-4032l --config "samplerate = 50MHz:voltage_threshold=2.5-2.5" -samples=1000000 --channels A0=D0,A1=CLK,A2=CMD --triggers CLK=e --output-file test1.cr
A message is displayed:
Failed to set device option 'voltage_threshold': not applicable.

From wiki page Hantek 4032L:
Hardware features support status
 + Buffered mode acquisition
 + Sample depth selection
 + Pretrigger depth selection
 + Internal clocking (timing mode)
 + External clocking (state mode) with edge (rising/falling/both) and clock channel (ACLK/BCLK) selection
+ Logic voltage threshold selection (independent for Axx and Bxx channel groups, possible to analyze dual standrard circuits)
 + Unconditional trigger
 + Trigger on signal edge (rising/falling/any)
 + Trigger on bus pattern match
 - Trigger on bus value within/out of range
 - Trigger on bus pattern condition (match/within/out of range) repeating for N consecutive samples
   where N is equal/within range/out of range
 - Trigger on bus pattern condition at specific signal edge
 - Trigger on any of the above conditions combined with pattern match on the previous/current/next sample
 - Use two trigger units in AND/OR combination
 - External trigger input/output signals

But the biggest HUGE problem is the speed of saving data from the device's memory to a file  when using sigrok-cli (PV downloads data from the device much faster). 1M samples are stored for approximately 1 minute. Thus, the whole memory of the device will be downloaded more than ONE HOUR!
Can this be somehow corrected?

[Carrington]

Hi Alexel, and welcome to the eevblog forum.

But the biggest HUGE problem is the speed of saving data from the device's memory to a file  when using sigrok-cli (PV downloads data from the device much faster). 1M samples are stored for approximately 1 minute. Thus, the whole memory of the device will be downloaded more than ONE HOUR!
Can this be somehow corrected?

I don't have a 4032L to try, but:
Have you tried to do the same under Linux? If so, it also take so long?
Could be an option import a csv file from the original hantek SW?

Cheers.

[Alexel]

Cheers, I do not have Linux installed to test your idea

The format of the CVS file kept by Hantek software does not coincide with the format of the PV (manual change is required), but the file size of the CVS for 65M samples is approximately 1 GB

[abyrvalg]

The trigger type you want (any edge) is selected by an icon near the signal name (left side) in PV.
Updating FPGA firmware from V0 to anything higher speeds the things up (see https://www.eevblog.com/forum/testgear/hantek-4032l-firmware-update/).
Cli is slower than PV on Linux too (single-threaded vs multi-threaded processing).

[Andy99]

Hi Alexel,
Could you please provide the FPGA version which are you using?

Code: [Select]

$ sigrok-cli -l 5 -d hantek-4032l --show
sr: [00:00.014059] device: hantek-4032l: Opening device instance.
sr: [00:00.082527] hantek-4032l: FPGA version: 0x4303. <-----
Newer features are supported for version >0x0000.

I have checked the voltage_threshold handling, there is no way to set this over sigrok-cli. Missing case in run_session@session.c. So setting this option is not bounded to FPGA version which you are using it.

[Alexel]

The trigger type you want (any edge) is selected by an icon near the signal name (left side) in PV.

Excuse me, I'm a loser! Did not pay attention to it.

Before asking questions to the respected community, I read everything I could find on the issue that interests me. The firmware FPGA in the device was 0x4303, after the update (with utility) became 0x4304.

Code: [Select]

sr: [00:00.047000] device: hantek-4032l: Opening device instance.
sr: [00:00.061000] hantek-4032l: FPGA version: 0x4304.
I found a way out of the situation, which more or less works - save from sigrok-cli in vcd format, and then import into PV. In this case, you need to describe twice the channels in '--channels' (this is probably solved by the settings for importing vcd to PV, but I have not figured it out yet).
And in case, if the samples are stored more than 50M, then the PV will crash.

My keys to sigrok-cli:
sigrok-cli --loglevel 2 --driver hantek-4032l --config samplerate=50MHz --samples=50000000 --channels A1=CLK,A2=CMD,A3=TMP0,A4=TMP1,A5=TMP2 --triggers CLK=e --output-format=vcd --output-file test2.vcd[/i]