Well the TLC374 were worse than the LM339, I've manged to improve the LM339, it looks like I had a crappy connection on the breadboard, I have it down to 250ns falling and 135ns rising response times which is OK for now, but I may look at this another time.
Differential line receivers which can be found in quads make good fast comparators for level translation applications.
I stongly suspect that the LM339s will be good enough at full speed, now I’ve gained some practical understanding and experience of the timings.
I have a dsPIC33EV256GM002 testing now which I am fairly confident will successfully run at the full 4004 clock speed.
This uses a slightly different methodology, I am generating the phi1 and phi2 from two output compares, and selectively interrupting preemptively phase 0 and phase 2 based on cycle count, using two other output compares, all using the same timebase.
Although it’s a 70MHz part, the interrupt latency (about 200ns) on the dsPIC33EV has proven unexpectedly bad compared to other Microchip 16 bitters, plus there is additional cycle overhead accessing non-CPU SFRs on this device in bit operations, I am not sure why the architecture is so dramatically different, typical hardware latency on other 16 bitters is 5 op cycles, it’s 14 on the dsPIC33EV. On the plus side it offers full alternate working register automatic context saving, so there’s no time spent doing software context saving. Due to the long interrupt latency, I am having to preemptively fire off the interrupts early.
Irrespective, this leaves about 60% of the time inside the main superloop, so plenty of time to service LCDs etc, although due to the reduced pin count I’m having to use I2C.