Author Topic: My Stackable Z80 project...  (Read 2325 times)

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Online Ian.M

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Re: My Stackable Z80 project...
« Reply #25 on: March 23, 2018, 11:24:45 am »
It may be easier for layout to put a nice wide Vcc trace right round the edge of the board.  Move those two Vcc pins to the other pin row of the connector to facilitate that.   

I specifically don't like the layout to the Z84C0020's Vcc pin.  It should have a decoupling cap with two vias to the ground plane right next to the pin. Angle the traces to adjacent pins to make room for that.  The other option is to put the decoupling on the back right next to the via that goes to the pin.
 

Offline alank2

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Re: My Stackable Z80 project...
« Reply #26 on: March 23, 2018, 01:00:57 pm »
I specifically don't like the layout to the Z84C0020's Vcc pin.  It should have a decoupling cap with two vias to the ground plane right next to the pin.

I should have mentioned - the Z80 bypass cap is not in place yet, but it will be.  I need to do a package/device for it in my library.

How much current can a 0.025" square pin carry?  I am thinking this will be 1A maximum.  I read something about these pins taking 3A!  I wonder about the connectors they plug into though.  Can I drop from 4 VCC pins to just 2 or 3?
 

Online Ian.M

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Re: My Stackable Z80 project...
« Reply #27 on: March 24, 2018, 08:09:47 pm »
Yes you can push 3A through some reputable brands of header pins and mating contacts, but that rating will assume the pin is soldered to a heavy ground plane,  both parts of the connector are brand new, and probably that there is a 'R' in the month!

In a real world application, with the risk of elevated ambient temperatures, skinny traces, contacts  that may have been mated/unmated repeatedly and have a little tarnish on them  and possibly the female contacts may be off-brand (worst case: thinner metal and reduced contact force and area), as a rule of thumb, I wouldn't expect trouble with overheating under 1A.

However, it isn't usually the connectors burning up that's the big issue, its the voltage drop across them under load.  If your ground pins are carrying significant current and if you have any TTL or TTL compatible CMOS on the board, or I2C stuff, their asymmetric logic thresholds make the logic '0' level particularly sensitive to ground offset and excess noise. 

Worst case, if you are short of pins, you can use as many as possible for Ground and distribute power at a higher voltage on fewer pins, regulating it down to the logic Vcc using a local LDO regulator on each board so the positive supply voltage drop is compensated for.
« Last Edit: March 24, 2018, 08:11:24 pm by Ian.M »
 

Offline alank2

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Re: My Stackable Z80 project...
« Reply #28 on: March 26, 2018, 02:55:37 am »
Thanks Ian - I went with 4 VCC pins which should be way overkill.

I'm adding the schematic for the SRAM board.

My "MMU" is very simple.  32K lower bank selected by the BANK signals, 32K higher bank is common.
 

Offline alank2

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Re: My Stackable Z80 project...
« Reply #29 on: March 28, 2018, 02:44:07 am »
Layouts for the Z80 board and SRAM board.

Yes...I forgot that you can mix/match address and data pins on the SRAM...  Looking at it though, I'm not sure a whole bunch would be gained from redoing it now.
 

Offline alank2

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Re: My Stackable Z80 project...
« Reply #30 on: April 11, 2018, 06:54:24 am »
A couple boards came in from Elecrow.  This should hopefully simplify my breadboard and make development easier when I can get back to this project (which won't be for a bit!)
 

Offline alank2

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Re: My Stackable Z80 project...
« Reply #31 on: April 17, 2018, 07:55:18 am »
Does all of this make sense?

This is the flip flop circuit I plan to use to allow Z80 IN/OUT/DMA with an AVR.

Z80 executes an OUT to 0x80-0x8F:

"0111" A7/A6/A5/A4 along with IORQ# asserted and FFCLEAR# deasserted trigger the flip flop through PRE#.
The flip flop output goes to a logic level N mosfet to assert WAIT# causing the Z80 to wait.
The AVR will notice FFSTATE# asserted on the flip flop and knows it is being addressed.
The AVR evaluates RD# or WR# to determine IN or OUT.

IN instruction:
The AVR grabs A8-A15, A0-A3 (we already know A4-A7) and determines what command the Z80 is trying to input.
The AVR sets data port to output and provides the data on D0-D7.
The AVR asserts BUSREQ# and then asserts FFCLEAR#.
The Z80 will be released from the wait, capture the data IN, and hold at BUSREQ# by asserting BUSACK#.
The AVR waits for BUSACK# assertion, then sets data port back to input.
If command requires DMA, the AVR can do it here.
The AVR deasserts FFCLEAR# (IORQ# is released now and it won't retrigger), then deasserts BUSREQ#.

OUT (with DMA):
The AVR grabs A8-A15, A0-A3 (we already know A4-A7) and determines what command the Z80 is trying to input.
The AVR grabs the data on D0-D7.
The AVR asserts BUSREQ# and then asserts FFCLEAR#.
The Z80 will be released from the wait, and hold at BUSREQ# by asserting BUSACK#.
The AVR waits for BUSACK# assertion.
The AVR can do the DMA here.
The AVR deasserts FFCLEAR# (IORQ# is released now and it won't retrigger), then deasserts BUSREQ#.

OUT (without DMA - if this works):
The AVR grabs A8-A15, A0-A3 (we already know A4-A7) and determines what command the Z80 is trying to input.
The AVR grabs the data on D0-D7.
The AVR asserts FFCLEAR#.
The Z80 will be released from the wait.
The AVR quickly waits for IORQ# to be deasserted and then deasserts FFCLEAR# before any other possible IN/OUT instruction can execute.

 

Offline alank2

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Re: My Stackable Z80 project...
« Reply #32 on: April 17, 2018, 12:28:49 pm »
PDF for the AVR board and all of its connections.  If anyone is still with me, take a look!
 

Offline alank2

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Re: My Stackable Z80 project...
« Reply #33 on: April 24, 2018, 10:45:33 am »
I got the board laid out.  When I started I was having my doubts as to whether I could do this with a 2 layer or would have to do 4 layer!

Hopefully with this I'll finally be able to get some development going on the software side as I get time.
 

Offline alank2

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Re: My Stackable Z80 project...
« Reply #34 on: May 06, 2018, 03:54:16 am »
I got the AVR board in and built - finally hooked it up to my logic analyzer so I can do some development on it.
 

Online Ian.M

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Re: My Stackable Z80 project...
« Reply #35 on: May 06, 2018, 05:11:21 am »
Great.   Nice to see its coming together.   I see you've got another topic: http://www.eevblog.com/forum/projects/10k-pullup-on-signal-takes-1us-to-take-it-back-high/ related to the AVR board.
 

Offline alank2

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Re: My Stackable Z80 project...
« Reply #36 on: May 06, 2018, 05:27:53 am »
Thanks Ian.

I'm going to try changing the 10K pullups to 3.3K and see if that cleans up the signals a bit.
 


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