Firstly you need to make sure you have a netclass for the group/s. These are normally generated automatically if somewhere on your schematic you lay down a bus (Place bus) and you add a net label that encompasses that group, something along the lines of data[15..0], where data0, data1 etc are net labels for the individual pins/wires
If, for example you wanted to make your data, address and control lines matched and you didn't already have bus's labelled as described above then simply place a bus connected to nothing with a net label including the [...] thingy. You then Place->Directives->PCB Layout and attach it to the bus wire, edit it adding the DRC rules you want.
The names of the control lines are not usually suitable for grouping with [...]. With those you can create a net class as Tim stated with the Place->Directives->NetClass. Double click it and give it a name such as ctrl_bus. Copy it and add it to all the control lines you wish to add to that class.
The only way I know how to add a PCB Layout directive to these (since you cant draw a bus and label it ctrl_bus) is to wire them into a harness and place the pcb layout directive on the signal harness wire