Hi all,
I'm using AD to create an FPGA board, and I need to either draw a polygon pour and use a signal layer or use a power plane with a split. I think I've managed to get the polygon pours correct, but I haven't managed to stumble into getting the plane layers to split.
Sorry if this is a very amateur question, but I've had a go of it for a while and can't make it move, if you will.
Thanks!