This is driving me bonkers. I have a PCB with some stringent isolation requirements. So, obviously, I need some rules. They seem to work, kinda, but also not. For simplicity, I disabled most rules except for these:

Basically, "regular" 0.2mm clearance, 6.1mm clearance on outer layers and 2.5mm on inner layers. So far so good. Now look at the picture. I took a trace from "IO3" and routed it towards "IO2". Obviously, the rules made me "hit the wall". You can see a 6.1mm clearance to a pad (SOIC IC) with "ISO2", which is correct. It also shows the clearance to a much closer pad, basically the TH pad of a Y2 cap. Clearance there is much less, less than 2.5mm even.

So... What the heck is going on?? From what I can tell, all TH constructs (including vias I think) are not taken into account for the clearance... So, why? And how can I fix it?