Altium DRC doesn't seem to catch via-to-metal spacing issues

[TheUnnamedNewbie]

So, I have a pcb with only blind microvias. The metals on different layers have different thicknesses and as a result each of my micro-vias and metals has different pitch/diameter/spacing.

I 'fixed' this by having a separate clearance rule for each layer. The rule would be something like 'Where first object matches InLayer('M1') and second object matches InLayer('M1')' . This seems to work fine for 99% of my design - but it doest seem to catch a lot of via annular ring clearance issues. Even though my DRC is clean in altium, the manufacturer says there are a lot of DRC errors still remaining. EG the via below, which is too close to the metals on the left and right, clearly violates the DRC rules, yet the DRC results are clean for that metal layer.

[thinkfat]

Rule might not trigger because the via and the second object are on the same net? Is there a 'same net' constraint you could use or formulate a manufacturing constraint and not an electrical rule?

[TheUnnamedNewbie]

The via and surrounding copper is not the same net here, so that is not the issue

[voltsandjolts]

This is the age old game where the OP provides a bare minimum of information and then everyone else submits their guesses as to the problem.

How about providing a minimal PCBdoc that shows the problem?

[JohnG]

The clearance between your via and the trace on that layer is not being checked by the specified clearance rule because the via is on the Multilayer, not on the individual internal signal layers like you have defined in your clearance rule.

I bet it's this. I got bitten by this, and it took a lot to figure this out, even with support from Altium.

Cheers,
John